1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_FRAME_BITMAP_ACK_H_ 27 #define _RX_FRAME_BITMAP_ACK_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 14 32 33 #define NUM_OF_QWORDS_RX_FRAME_BITMAP_ACK 7 34 35 36 struct rx_frame_bitmap_ack { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t no_bitmap_available : 1, // [0:0] 39 explicit_ack : 1, // [1:1] 40 explict_ack_type : 3, // [4:2] 41 ba_bitmap_size : 2, // [6:5] 42 reserved_0a : 3, // [9:7] 43 ba_tid : 4, // [13:10] 44 sta_full_aid : 13, // [26:14] 45 reserved_0b : 5; // [31:27] 46 uint32_t addr1_31_0 : 32; // [31:0] 47 uint32_t addr1_47_32 : 16, // [15:0] 48 addr2_15_0 : 16; // [31:16] 49 uint32_t addr2_47_16 : 32; // [31:0] 50 uint32_t ba_ts_ctrl : 16, // [15:0] 51 ba_ts_seq : 16; // [31:16] 52 uint32_t ba_ts_bitmap_31_0 : 32; // [31:0] 53 uint32_t ba_ts_bitmap_63_32 : 32; // [31:0] 54 uint32_t ba_ts_bitmap_95_64 : 32; // [31:0] 55 uint32_t ba_ts_bitmap_127_96 : 32; // [31:0] 56 uint32_t ba_ts_bitmap_159_128 : 32; // [31:0] 57 uint32_t ba_ts_bitmap_191_160 : 32; // [31:0] 58 uint32_t ba_ts_bitmap_223_192 : 32; // [31:0] 59 uint32_t ba_ts_bitmap_255_224 : 32; // [31:0] 60 uint32_t tlv64_padding : 32; // [31:0] 61 #else 62 uint32_t reserved_0b : 5, // [31:27] 63 sta_full_aid : 13, // [26:14] 64 ba_tid : 4, // [13:10] 65 reserved_0a : 3, // [9:7] 66 ba_bitmap_size : 2, // [6:5] 67 explict_ack_type : 3, // [4:2] 68 explicit_ack : 1, // [1:1] 69 no_bitmap_available : 1; // [0:0] 70 uint32_t addr1_31_0 : 32; // [31:0] 71 uint32_t addr2_15_0 : 16, // [31:16] 72 addr1_47_32 : 16; // [15:0] 73 uint32_t addr2_47_16 : 32; // [31:0] 74 uint32_t ba_ts_seq : 16, // [31:16] 75 ba_ts_ctrl : 16; // [15:0] 76 uint32_t ba_ts_bitmap_31_0 : 32; // [31:0] 77 uint32_t ba_ts_bitmap_63_32 : 32; // [31:0] 78 uint32_t ba_ts_bitmap_95_64 : 32; // [31:0] 79 uint32_t ba_ts_bitmap_127_96 : 32; // [31:0] 80 uint32_t ba_ts_bitmap_159_128 : 32; // [31:0] 81 uint32_t ba_ts_bitmap_191_160 : 32; // [31:0] 82 uint32_t ba_ts_bitmap_223_192 : 32; // [31:0] 83 uint32_t ba_ts_bitmap_255_224 : 32; // [31:0] 84 uint32_t tlv64_padding : 32; // [31:0] 85 #endif 86 }; 87 88 89 /* Description NO_BITMAP_AVAILABLE 90 91 When set, RXPCU does not have any info available for the 92 requested user. 93 94 RXPCU will set the TA/RA, addresses with the devices OWN 95 address. 96 All other fields are set to 0 97 98 TXPCU will just blindly follow RXPCUs info. 99 (only for status reporting is TXPCU using this). 100 101 Note that this field and field "Explicit_ack" can not be 102 simultaneously set. 103 <legal all> 104 */ 105 106 #define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET 0x0000000000000000 107 #define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB 0 108 #define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB 0 109 #define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK 0x0000000000000001 110 111 112 /* Description EXPLICIT_ACK 113 114 When set, no BA is needed for this STA. Instead just a single 115 ACK indication 116 117 Note that this field and field "No_bitmap_available" can 118 not be simultaneously set. 119 120 Also note that RXPCU might not know if the response that 121 TXPCU is generating is a single ACK or M(sta) BA. 122 For that reason, RXPCU shall also properly fill in all the 123 BA related fields. TXPCU will based on the explicit ack 124 type and in case of BA type response, blindely copy the 125 required BA related fields and not change their contents: 126 127 The related fields are: 128 Ba_tid 129 ba_ts_ctrl 130 ba_ts_seq 131 ba_ts_bitmap_... 132 133 <legal all> 134 */ 135 136 #define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET 0x0000000000000000 137 #define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB 1 138 #define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB 1 139 #define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK 0x0000000000000002 140 141 142 /* Description EXPLICT_ACK_TYPE 143 144 Field only valid when Explicit_ack is set 145 146 Note that TXPCU only needs to evaluate this field in case 147 of generating a multi (STA) BA 148 149 <enum 0 ack_for_single_data_frame> set when only a single 150 data frame was received that indicated explicitly a 'normal' 151 ack (no BA) to be sent. 152 <enum 1 ack_for_management> set when a management frame 153 was received 154 <enum 2 ack_for_PSPOLL> set when a PS_POLL frame was received 155 156 <enum 3 ack_for_assoc_request> set when an association request 157 was received from an unassociated STA. 158 <enum 4 ack_for_all_frames> set when RXPCU determined that 159 all frames have been properly received. 160 <legal 0-4> 161 */ 162 163 #define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET 0x0000000000000000 164 #define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB 2 165 #define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB 4 166 #define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK 0x000000000000001c 167 168 169 /* Description BA_BITMAP_SIZE 170 171 Field not valid when "No_bitmap_available" or "Explicit_ack" 172 is set. 173 174 175 <enum 0 BA_bitmap_32 > Bitmap size set to window of 32 176 <enum 1 BA_bitmap_64 > Bitmap size set to window of 64 177 <enum 2 BA_bitmap_128 > Bitmap size set to window of 128 178 179 <enum 3 BA_bitmap_256 > Bitmap size set to window of 256 180 181 182 <legal 0-3> 183 */ 184 185 #define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 186 #define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 187 #define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 188 #define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 189 190 191 /* Description RESERVED_0A 192 193 <legal 0> 194 */ 195 196 #define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 197 #define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB 7 198 #define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB 9 199 #define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK 0x0000000000000380 200 201 202 /* Description BA_TID 203 204 The tid for the BA 205 */ 206 207 #define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 208 #define RX_FRAME_BITMAP_ACK_BA_TID_LSB 10 209 #define RX_FRAME_BITMAP_ACK_BA_TID_MSB 13 210 #define RX_FRAME_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 211 212 213 /* Description STA_FULL_AID 214 215 The full AID of this station. 216 */ 217 218 #define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 219 #define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB 14 220 #define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB 26 221 #define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 222 223 224 /* Description RESERVED_0B 225 226 <legal 0> 227 */ 228 229 #define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 230 #define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB 27 231 #define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB 31 232 #define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK 0x00000000f8000000 233 234 235 /* Description ADDR1_31_0 236 237 lower 32 bits of addr1 of the received frame 238 */ 239 240 #define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000000 241 #define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB 32 242 #define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB 63 243 #define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff00000000 244 245 246 /* Description ADDR1_47_32 247 248 upper 16 bits of addr1 of the received frame 249 */ 250 251 #define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 252 #define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB 0 253 #define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB 15 254 #define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK 0x000000000000ffff 255 256 257 /* Description ADDR2_15_0 258 259 lower 16 bits of addr2 of the received frame 260 */ 261 262 #define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 263 #define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB 16 264 #define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB 31 265 #define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK 0x00000000ffff0000 266 267 268 /* Description ADDR2_47_16 269 270 upper 32 bits of addr2 of the received frame 271 */ 272 273 #define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000008 274 #define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB 32 275 #define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB 63 276 #define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff00000000 277 278 279 /* Description BA_TS_CTRL 280 281 Transmit BA control 282 RXPCU assumes the C-BA format, NOT M-BA format. 283 In case TXPCU is responding with M-BA, TXPCU will ignore 284 this field. TXPCU will generate it 285 */ 286 287 #define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 288 #define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB 0 289 #define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB 15 290 #define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK 0x000000000000ffff 291 292 293 /* Description BA_TS_SEQ 294 295 Transmit BA sequence number. 296 */ 297 298 #define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 299 #define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB 16 300 #define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB 31 301 #define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK 0x00000000ffff0000 302 303 304 /* Description BA_TS_BITMAP_31_0 305 306 Transmit BA bitmap[31:0] 307 */ 308 309 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000010 310 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 32 311 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 63 312 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff00000000 313 314 315 /* Description BA_TS_BITMAP_63_32 316 317 Transmit BA bitmap[63:32] 318 */ 319 320 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 321 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 322 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 323 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0x00000000ffffffff 324 325 326 /* Description BA_TS_BITMAP_95_64 327 328 Transmit BA bitmap[95:64] 329 */ 330 331 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000018 332 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 32 333 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 63 334 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff00000000 335 336 337 /* Description BA_TS_BITMAP_127_96 338 339 Transmit BA bitmap[127:96] 340 */ 341 342 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 343 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 344 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 345 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0x00000000ffffffff 346 347 348 /* Description BA_TS_BITMAP_159_128 349 350 Transmit BA bitmap[159:128] 351 */ 352 353 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000020 354 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 32 355 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 63 356 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff00000000 357 358 359 /* Description BA_TS_BITMAP_191_160 360 361 Transmit BA bitmap[191:160] 362 */ 363 364 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 365 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 366 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 367 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0x00000000ffffffff 368 369 370 /* Description BA_TS_BITMAP_223_192 371 372 Transmit BA bitmap[223:192] 373 */ 374 375 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000028 376 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 32 377 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 63 378 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff00000000 379 380 381 /* Description BA_TS_BITMAP_255_224 382 383 Transmit BA bitmap[255:224] 384 */ 385 386 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 387 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 388 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 389 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0x00000000ffffffff 390 391 392 /* Description TLV64_PADDING 393 394 Automatic DWORD padding inserted while converting TLV32 395 to TLV64 for 64 bit ARCH 396 <legal 0> 397 */ 398 399 #define RX_FRAME_BITMAP_ACK_TLV64_PADDING_OFFSET 0x0000000000000030 400 #define RX_FRAME_BITMAP_ACK_TLV64_PADDING_LSB 32 401 #define RX_FRAME_BITMAP_ACK_TLV64_PADDING_MSB 63 402 #define RX_FRAME_BITMAP_ACK_TLV64_PADDING_MASK 0xffffffff00000000 403 404 405 406 #endif // RX_FRAME_BITMAP_ACK 407