1*5113495bSYour Name 2*5113495bSYour Name /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name 18*5113495bSYour Name 19*5113495bSYour Name 20*5113495bSYour Name 21*5113495bSYour Name 22*5113495bSYour Name 23*5113495bSYour Name 24*5113495bSYour Name 25*5113495bSYour Name 26*5113495bSYour Name #ifndef _RX_MPDU_DETAILS_H_ 27*5113495bSYour Name #define _RX_MPDU_DETAILS_H_ 28*5113495bSYour Name #if !defined(__ASSEMBLER__) 29*5113495bSYour Name #endif 30*5113495bSYour Name 31*5113495bSYour Name #include "rx_mpdu_desc_info.h" 32*5113495bSYour Name #include "buffer_addr_info.h" 33*5113495bSYour Name #define NUM_OF_DWORDS_RX_MPDU_DETAILS 4 34*5113495bSYour Name 35*5113495bSYour Name 36*5113495bSYour Name struct rx_mpdu_details { 37*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38*5113495bSYour Name struct buffer_addr_info msdu_link_desc_addr_info; 39*5113495bSYour Name struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 40*5113495bSYour Name #else 41*5113495bSYour Name struct buffer_addr_info msdu_link_desc_addr_info; 42*5113495bSYour Name struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 43*5113495bSYour Name #endif 44*5113495bSYour Name }; 45*5113495bSYour Name 46*5113495bSYour Name 47*5113495bSYour Name /* Description MSDU_LINK_DESC_ADDR_INFO 48*5113495bSYour Name 49*5113495bSYour Name Consumer: REO/SW/FW 50*5113495bSYour Name Producer: RXDMA 51*5113495bSYour Name 52*5113495bSYour Name Details of the physical address of the MSDU link descriptor 53*5113495bSYour Name that contains pointers to MSDUs related to this MPDU 54*5113495bSYour Name */ 55*5113495bSYour Name 56*5113495bSYour Name 57*5113495bSYour Name /* Description BUFFER_ADDR_31_0 58*5113495bSYour Name 59*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 60*5113495bSYour Name descriptor OR Link Descriptor 61*5113495bSYour Name 62*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 63*5113495bSYour Name <legal all> 64*5113495bSYour Name */ 65*5113495bSYour Name 66*5113495bSYour Name #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 67*5113495bSYour Name #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 68*5113495bSYour Name #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 69*5113495bSYour Name #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 70*5113495bSYour Name 71*5113495bSYour Name 72*5113495bSYour Name /* Description BUFFER_ADDR_39_32 73*5113495bSYour Name 74*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 75*5113495bSYour Name descriptor OR Link Descriptor 76*5113495bSYour Name 77*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 78*5113495bSYour Name <legal all> 79*5113495bSYour Name */ 80*5113495bSYour Name 81*5113495bSYour Name #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 82*5113495bSYour Name #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 83*5113495bSYour Name #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 84*5113495bSYour Name #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 85*5113495bSYour Name 86*5113495bSYour Name 87*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 88*5113495bSYour Name 89*5113495bSYour Name Consumer: WBM 90*5113495bSYour Name Producer: SW/FW 91*5113495bSYour Name 92*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 93*5113495bSYour Name 94*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 95*5113495bSYour Name descriptor OR link descriptor that is being pointed to 96*5113495bSYour Name shall be returned after the frame has been processed. It 97*5113495bSYour Name is used by WBM for routing purposes. 98*5113495bSYour Name 99*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 100*5113495bSYour Name to the WMB buffer idle list 101*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 102*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 103*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 104*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 105*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 106*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 107*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 108*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 109*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 110*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 111*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 112*5113495bSYour Name ring 0 113*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 114*5113495bSYour Name ring 1 115*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 116*5113495bSYour Name ring 2 117*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 118*5113495bSYour Name ring 3 119*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 120*5113495bSYour Name ring 4 121*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 122*5113495bSYour Name ring 5 123*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 124*5113495bSYour Name ring 6 125*5113495bSYour Name 126*5113495bSYour Name <legal 0-12> 127*5113495bSYour Name */ 128*5113495bSYour Name 129*5113495bSYour Name #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 130*5113495bSYour Name #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 131*5113495bSYour Name #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 132*5113495bSYour Name #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 133*5113495bSYour Name 134*5113495bSYour Name 135*5113495bSYour Name /* Description SW_BUFFER_COOKIE 136*5113495bSYour Name 137*5113495bSYour Name Cookie field exclusively used by SW. 138*5113495bSYour Name 139*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 140*5113495bSYour Name 141*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 142*5113495bSYour Name value on to other descriptors together with the physical 143*5113495bSYour Name address 144*5113495bSYour Name 145*5113495bSYour Name Field can be used by SW to for example associate the buffers 146*5113495bSYour Name physical address with the virtual address 147*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 148*5113495bSYour Name 149*5113495bSYour Name 150*5113495bSYour Name NOTE1: 151*5113495bSYour Name The three most significant bits can have a special meaning 152*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 153*5113495bSYour Name and field transmit_bw_restriction is set 154*5113495bSYour Name 155*5113495bSYour Name In case of NON punctured transmission: 156*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 157*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 158*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 159*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 160*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 161*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 162*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 163*5113495bSYour Name 164*5113495bSYour Name In case of punctured transmission: 165*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 166*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 167*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 168*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 169*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 170*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 171*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 172*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 173*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 174*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 175*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 176*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 177*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 178*5113495bSYour Name 179*5113495bSYour Name Note: a punctured transmission is indicated by the presence 180*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 181*5113495bSYour Name 182*5113495bSYour Name <legal all> 183*5113495bSYour Name */ 184*5113495bSYour Name 185*5113495bSYour Name #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 186*5113495bSYour Name #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 187*5113495bSYour Name #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 188*5113495bSYour Name #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 189*5113495bSYour Name 190*5113495bSYour Name 191*5113495bSYour Name /* Description RX_MPDU_DESC_INFO_DETAILS 192*5113495bSYour Name 193*5113495bSYour Name Consumer: REO/SW/FW 194*5113495bSYour Name Producer: RXDMA 195*5113495bSYour Name 196*5113495bSYour Name General information related to the MPDU that should be passed 197*5113495bSYour Name on from REO entrance ring to the REO destination ring 198*5113495bSYour Name */ 199*5113495bSYour Name 200*5113495bSYour Name 201*5113495bSYour Name /* Description MSDU_COUNT 202*5113495bSYour Name 203*5113495bSYour Name Consumer: REO/SW/FW 204*5113495bSYour Name Producer: RXDMA 205*5113495bSYour Name 206*5113495bSYour Name The number of MSDUs within the MPDU 207*5113495bSYour Name <legal all> 208*5113495bSYour Name */ 209*5113495bSYour Name 210*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 211*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 212*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 213*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 214*5113495bSYour Name 215*5113495bSYour Name 216*5113495bSYour Name /* Description FRAGMENT_FLAG 217*5113495bSYour Name 218*5113495bSYour Name Consumer: REO/SW/FW 219*5113495bSYour Name Producer: RXDMA 220*5113495bSYour Name 221*5113495bSYour Name When set, this MPDU is a fragment and REO should forward 222*5113495bSYour Name this fragment MPDU to the REO destination ring without 223*5113495bSYour Name any reorder checks, pn checks or bitmap update. This implies 224*5113495bSYour Name that REO is forwarding the pointer to the MSDU link descriptor. 225*5113495bSYour Name The destination ring is coming from a programmable register 226*5113495bSYour Name setting in REO 227*5113495bSYour Name 228*5113495bSYour Name <legal all> 229*5113495bSYour Name */ 230*5113495bSYour Name 231*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 232*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 233*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 234*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 235*5113495bSYour Name 236*5113495bSYour Name 237*5113495bSYour Name /* Description MPDU_RETRY_BIT 238*5113495bSYour Name 239*5113495bSYour Name Consumer: REO/SW/FW 240*5113495bSYour Name Producer: RXDMA 241*5113495bSYour Name 242*5113495bSYour Name The retry bit setting from the MPDU header of the received 243*5113495bSYour Name frame 244*5113495bSYour Name <legal all> 245*5113495bSYour Name */ 246*5113495bSYour Name 247*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 248*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 249*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 250*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 251*5113495bSYour Name 252*5113495bSYour Name 253*5113495bSYour Name /* Description AMPDU_FLAG 254*5113495bSYour Name 255*5113495bSYour Name Consumer: REO/SW/FW 256*5113495bSYour Name Producer: RXDMA 257*5113495bSYour Name 258*5113495bSYour Name When set, the MPDU was received as part of an A-MPDU. 259*5113495bSYour Name <legal all> 260*5113495bSYour Name */ 261*5113495bSYour Name 262*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 263*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 264*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 265*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 266*5113495bSYour Name 267*5113495bSYour Name 268*5113495bSYour Name /* Description BAR_FRAME 269*5113495bSYour Name 270*5113495bSYour Name Consumer: REO/SW/FW 271*5113495bSYour Name Producer: RXDMA 272*5113495bSYour Name 273*5113495bSYour Name When set, the received frame is a BAR frame. After processing, 274*5113495bSYour Name this frame shall be pushed to SW or deleted. 275*5113495bSYour Name <legal all> 276*5113495bSYour Name */ 277*5113495bSYour Name 278*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 279*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 280*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 281*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 282*5113495bSYour Name 283*5113495bSYour Name 284*5113495bSYour Name /* Description PN_FIELDS_CONTAIN_VALID_INFO 285*5113495bSYour Name 286*5113495bSYour Name Consumer: REO/SW/FW 287*5113495bSYour Name Producer: RXDMA 288*5113495bSYour Name 289*5113495bSYour Name Copied here by RXDMA from RX_MPDU_END 290*5113495bSYour Name When not set, REO will Not perform a PN sequence number 291*5113495bSYour Name check 292*5113495bSYour Name */ 293*5113495bSYour Name 294*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 295*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 296*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 297*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 298*5113495bSYour Name 299*5113495bSYour Name 300*5113495bSYour Name /* Description RAW_MPDU 301*5113495bSYour Name 302*5113495bSYour Name Field only valid when first_msdu_in_mpdu_flag is set. 303*5113495bSYour Name 304*5113495bSYour Name When set, the contents in the MSDU buffer contains a 'RAW' 305*5113495bSYour Name MPDU. This 'RAW' MPDU might be spread out over multiple 306*5113495bSYour Name MSDU buffers. 307*5113495bSYour Name <legal all> 308*5113495bSYour Name */ 309*5113495bSYour Name 310*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 311*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 312*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 313*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 314*5113495bSYour Name 315*5113495bSYour Name 316*5113495bSYour Name /* Description MORE_FRAGMENT_FLAG 317*5113495bSYour Name 318*5113495bSYour Name The More Fragment bit setting from the MPDU header of the 319*5113495bSYour Name received frame 320*5113495bSYour Name 321*5113495bSYour Name <legal all> 322*5113495bSYour Name */ 323*5113495bSYour Name 324*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 325*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 326*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 327*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 328*5113495bSYour Name 329*5113495bSYour Name 330*5113495bSYour Name /* Description SRC_INFO 331*5113495bSYour Name 332*5113495bSYour Name Source (virtual) device/interface info. associated with 333*5113495bSYour Name this peer 334*5113495bSYour Name 335*5113495bSYour Name This field gets passed on by REO to PPE in the EDMA descriptor 336*5113495bSYour Name ('REO_TO_PPE_RING'). 337*5113495bSYour Name 338*5113495bSYour Name Hamilton v1 used this for 'vdev_id' instead. 339*5113495bSYour Name <legal all> 340*5113495bSYour Name */ 341*5113495bSYour Name 342*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 343*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 344*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 345*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 346*5113495bSYour Name 347*5113495bSYour Name 348*5113495bSYour Name /* Description MPDU_QOS_CONTROL_VALID 349*5113495bSYour Name 350*5113495bSYour Name When set, the MPDU has a QoS control field. 351*5113495bSYour Name 352*5113495bSYour Name In case of ndp or phy_err, this field will never be set. 353*5113495bSYour Name 354*5113495bSYour Name <legal all> 355*5113495bSYour Name */ 356*5113495bSYour Name 357*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 358*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 359*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 360*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 361*5113495bSYour Name 362*5113495bSYour Name 363*5113495bSYour Name /* Description TID 364*5113495bSYour Name 365*5113495bSYour Name Field only valid when mpdu_qos_control_valid is set 366*5113495bSYour Name 367*5113495bSYour Name The TID field in the QoS control field 368*5113495bSYour Name <legal all> 369*5113495bSYour Name */ 370*5113495bSYour Name 371*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 372*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 373*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 374*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 375*5113495bSYour Name 376*5113495bSYour Name 377*5113495bSYour Name /* Description PEER_META_DATA 378*5113495bSYour Name 379*5113495bSYour Name Meta data that SW has programmed in the Peer table entry 380*5113495bSYour Name of the transmitting STA. 381*5113495bSYour Name <legal all> 382*5113495bSYour Name */ 383*5113495bSYour Name 384*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c 385*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 386*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 387*5113495bSYour Name #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 388*5113495bSYour Name 389*5113495bSYour Name 390*5113495bSYour Name 391*5113495bSYour Name #endif // RX_MPDU_DETAILS 392