1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_MPDU_DETAILS_H_ 27 #define _RX_MPDU_DETAILS_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "rx_mpdu_desc_info.h" 32 #include "buffer_addr_info.h" 33 #define NUM_OF_DWORDS_RX_MPDU_DETAILS 4 34 35 36 struct rx_mpdu_details { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 struct buffer_addr_info msdu_link_desc_addr_info; 39 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 40 #else 41 struct buffer_addr_info msdu_link_desc_addr_info; 42 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 43 #endif 44 }; 45 46 47 /* Description MSDU_LINK_DESC_ADDR_INFO 48 49 Consumer: REO/SW/FW 50 Producer: RXDMA 51 52 Details of the physical address of the MSDU link descriptor 53 that contains pointers to MSDUs related to this MPDU 54 */ 55 56 57 /* Description BUFFER_ADDR_31_0 58 59 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 60 descriptor OR Link Descriptor 61 62 In case of 'NULL' pointer, this field is set to 0 63 <legal all> 64 */ 65 66 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 67 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 68 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 69 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 70 71 72 /* Description BUFFER_ADDR_39_32 73 74 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 75 descriptor OR Link Descriptor 76 77 In case of 'NULL' pointer, this field is set to 0 78 <legal all> 79 */ 80 81 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 82 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 83 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 84 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 85 86 87 /* Description RETURN_BUFFER_MANAGER 88 89 Consumer: WBM 90 Producer: SW/FW 91 92 In case of 'NULL' pointer, this field is set to 0 93 94 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 95 descriptor OR link descriptor that is being pointed to 96 shall be returned after the frame has been processed. It 97 is used by WBM for routing purposes. 98 99 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 100 to the WMB buffer idle list 101 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 102 to the WBM idle link descriptor idle list, where the chip 103 0 WBM is chosen in case of a multi-chip config 104 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 105 to the chip 1 WBM idle link descriptor idle list 106 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 107 to the chip 2 WBM idle link descriptor idle list 108 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 109 returned to chip 3 WBM idle link descriptor idle list 110 <enum 4 FW_BM> This buffer shall be returned to the FW 111 <enum 5 SW0_BM> This buffer shall be returned to the SW, 112 ring 0 113 <enum 6 SW1_BM> This buffer shall be returned to the SW, 114 ring 1 115 <enum 7 SW2_BM> This buffer shall be returned to the SW, 116 ring 2 117 <enum 8 SW3_BM> This buffer shall be returned to the SW, 118 ring 3 119 <enum 9 SW4_BM> This buffer shall be returned to the SW, 120 ring 4 121 <enum 10 SW5_BM> This buffer shall be returned to the SW, 122 ring 5 123 <enum 11 SW6_BM> This buffer shall be returned to the SW, 124 ring 6 125 126 <legal 0-12> 127 */ 128 129 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 130 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 131 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 132 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 133 134 135 /* Description SW_BUFFER_COOKIE 136 137 Cookie field exclusively used by SW. 138 139 In case of 'NULL' pointer, this field is set to 0 140 141 HW ignores the contents, accept that it passes the programmed 142 value on to other descriptors together with the physical 143 address 144 145 Field can be used by SW to for example associate the buffers 146 physical address with the virtual address 147 The bit definitions as used by SW are within SW HLD specification 148 149 150 NOTE1: 151 The three most significant bits can have a special meaning 152 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 153 and field transmit_bw_restriction is set 154 155 In case of NON punctured transmission: 156 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 157 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 158 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 159 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 160 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 161 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 162 Sw_buffer_cookie[19:18] = 2'b11: reserved 163 164 In case of punctured transmission: 165 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 166 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 167 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 168 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 169 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 170 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 171 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 172 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 173 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 174 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 175 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 176 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 177 Sw_buffer_cookie[19:18] = 2'b11: reserved 178 179 Note: a punctured transmission is indicated by the presence 180 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 181 182 <legal all> 183 */ 184 185 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 186 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 187 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 188 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 189 190 191 /* Description RX_MPDU_DESC_INFO_DETAILS 192 193 Consumer: REO/SW/FW 194 Producer: RXDMA 195 196 General information related to the MPDU that should be passed 197 on from REO entrance ring to the REO destination ring 198 */ 199 200 201 /* Description MSDU_COUNT 202 203 Consumer: REO/SW/FW 204 Producer: RXDMA 205 206 The number of MSDUs within the MPDU 207 <legal all> 208 */ 209 210 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 211 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 212 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 213 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 214 215 216 /* Description FRAGMENT_FLAG 217 218 Consumer: REO/SW/FW 219 Producer: RXDMA 220 221 When set, this MPDU is a fragment and REO should forward 222 this fragment MPDU to the REO destination ring without 223 any reorder checks, pn checks or bitmap update. This implies 224 that REO is forwarding the pointer to the MSDU link descriptor. 225 The destination ring is coming from a programmable register 226 setting in REO 227 228 <legal all> 229 */ 230 231 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 232 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 233 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 234 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 235 236 237 /* Description MPDU_RETRY_BIT 238 239 Consumer: REO/SW/FW 240 Producer: RXDMA 241 242 The retry bit setting from the MPDU header of the received 243 frame 244 <legal all> 245 */ 246 247 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 248 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 249 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 250 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 251 252 253 /* Description AMPDU_FLAG 254 255 Consumer: REO/SW/FW 256 Producer: RXDMA 257 258 When set, the MPDU was received as part of an A-MPDU. 259 <legal all> 260 */ 261 262 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 263 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 264 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 265 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 266 267 268 /* Description BAR_FRAME 269 270 Consumer: REO/SW/FW 271 Producer: RXDMA 272 273 When set, the received frame is a BAR frame. After processing, 274 this frame shall be pushed to SW or deleted. 275 <legal all> 276 */ 277 278 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 279 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 280 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 281 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 282 283 284 /* Description PN_FIELDS_CONTAIN_VALID_INFO 285 286 Consumer: REO/SW/FW 287 Producer: RXDMA 288 289 Copied here by RXDMA from RX_MPDU_END 290 When not set, REO will Not perform a PN sequence number 291 check 292 */ 293 294 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 295 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 296 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 297 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 298 299 300 /* Description RAW_MPDU 301 302 Field only valid when first_msdu_in_mpdu_flag is set. 303 304 When set, the contents in the MSDU buffer contains a 'RAW' 305 MPDU. This 'RAW' MPDU might be spread out over multiple 306 MSDU buffers. 307 <legal all> 308 */ 309 310 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 311 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 312 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 313 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 314 315 316 /* Description MORE_FRAGMENT_FLAG 317 318 The More Fragment bit setting from the MPDU header of the 319 received frame 320 321 <legal all> 322 */ 323 324 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 325 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 326 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 327 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 328 329 330 /* Description SRC_INFO 331 332 Source (virtual) device/interface info. associated with 333 this peer 334 335 This field gets passed on by REO to PPE in the EDMA descriptor 336 ('REO_TO_PPE_RING'). 337 338 Hamilton v1 used this for 'vdev_id' instead. 339 <legal all> 340 */ 341 342 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 343 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 344 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 345 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 346 347 348 /* Description MPDU_QOS_CONTROL_VALID 349 350 When set, the MPDU has a QoS control field. 351 352 In case of ndp or phy_err, this field will never be set. 353 354 <legal all> 355 */ 356 357 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 358 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 359 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 360 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 361 362 363 /* Description TID 364 365 Field only valid when mpdu_qos_control_valid is set 366 367 The TID field in the QoS control field 368 <legal all> 369 */ 370 371 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 372 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 373 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 374 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 375 376 377 /* Description PEER_META_DATA 378 379 Meta data that SW has programmed in the Peer table entry 380 of the transmitting STA. 381 <legal all> 382 */ 383 384 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c 385 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 386 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 387 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 388 389 390 391 #endif // RX_MPDU_DETAILS 392