1*5113495bSYour Name 2*5113495bSYour Name /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name 18*5113495bSYour Name 19*5113495bSYour Name 20*5113495bSYour Name 21*5113495bSYour Name 22*5113495bSYour Name 23*5113495bSYour Name 24*5113495bSYour Name 25*5113495bSYour Name 26*5113495bSYour Name #ifndef _RX_MPDU_END_H_ 27*5113495bSYour Name #define _RX_MPDU_END_H_ 28*5113495bSYour Name #if !defined(__ASSEMBLER__) 29*5113495bSYour Name #endif 30*5113495bSYour Name 31*5113495bSYour Name #define NUM_OF_DWORDS_RX_MPDU_END 4 32*5113495bSYour Name 33*5113495bSYour Name #define NUM_OF_QWORDS_RX_MPDU_END 2 34*5113495bSYour Name 35*5113495bSYour Name 36*5113495bSYour Name struct rx_mpdu_end { 37*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38*5113495bSYour Name uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] 39*5113495bSYour Name sw_frame_group_id : 7, // [8:2] 40*5113495bSYour Name reserved_0 : 7, // [15:9] 41*5113495bSYour Name phy_ppdu_id : 16; // [31:16] 42*5113495bSYour Name uint32_t reserved_1a : 11, // [10:0] 43*5113495bSYour Name unsup_ktype_short_frame : 1, // [11:11] 44*5113495bSYour Name rx_in_tx_decrypt_byp : 1, // [12:12] 45*5113495bSYour Name overflow_err : 1, // [13:13] 46*5113495bSYour Name mpdu_length_err : 1, // [14:14] 47*5113495bSYour Name tkip_mic_err : 1, // [15:15] 48*5113495bSYour Name decrypt_err : 1, // [16:16] 49*5113495bSYour Name unencrypted_frame_err : 1, // [17:17] 50*5113495bSYour Name pn_fields_contain_valid_info : 1, // [18:18] 51*5113495bSYour Name fcs_err : 1, // [19:19] 52*5113495bSYour Name msdu_length_err : 1, // [20:20] 53*5113495bSYour Name rxdma0_destination_ring : 3, // [23:21] 54*5113495bSYour Name rxdma1_destination_ring : 3, // [26:24] 55*5113495bSYour Name decrypt_status_code : 3, // [29:27] 56*5113495bSYour Name rx_bitmap_not_updated : 1, // [30:30] 57*5113495bSYour Name reserved_1b : 1; // [31:31] 58*5113495bSYour Name uint32_t reserved_2a : 15, // [14:0] 59*5113495bSYour Name rxpcu_mgmt_sequence_nr_valid : 1, // [15:15] 60*5113495bSYour Name rxpcu_mgmt_sequence_nr : 16; // [31:16] 61*5113495bSYour Name uint32_t rxframe_assert_mlo_timestamp : 32; // [31:0] 62*5113495bSYour Name #else 63*5113495bSYour Name uint32_t phy_ppdu_id : 16, // [31:16] 64*5113495bSYour Name reserved_0 : 7, // [15:9] 65*5113495bSYour Name sw_frame_group_id : 7, // [8:2] 66*5113495bSYour Name rxpcu_mpdu_filter_in_category : 2; // [1:0] 67*5113495bSYour Name uint32_t reserved_1b : 1, // [31:31] 68*5113495bSYour Name rx_bitmap_not_updated : 1, // [30:30] 69*5113495bSYour Name decrypt_status_code : 3, // [29:27] 70*5113495bSYour Name rxdma1_destination_ring : 3, // [26:24] 71*5113495bSYour Name rxdma0_destination_ring : 3, // [23:21] 72*5113495bSYour Name msdu_length_err : 1, // [20:20] 73*5113495bSYour Name fcs_err : 1, // [19:19] 74*5113495bSYour Name pn_fields_contain_valid_info : 1, // [18:18] 75*5113495bSYour Name unencrypted_frame_err : 1, // [17:17] 76*5113495bSYour Name decrypt_err : 1, // [16:16] 77*5113495bSYour Name tkip_mic_err : 1, // [15:15] 78*5113495bSYour Name mpdu_length_err : 1, // [14:14] 79*5113495bSYour Name overflow_err : 1, // [13:13] 80*5113495bSYour Name rx_in_tx_decrypt_byp : 1, // [12:12] 81*5113495bSYour Name unsup_ktype_short_frame : 1, // [11:11] 82*5113495bSYour Name reserved_1a : 11; // [10:0] 83*5113495bSYour Name uint32_t rxpcu_mgmt_sequence_nr : 16, // [31:16] 84*5113495bSYour Name rxpcu_mgmt_sequence_nr_valid : 1, // [15:15] 85*5113495bSYour Name reserved_2a : 15; // [14:0] 86*5113495bSYour Name uint32_t rxframe_assert_mlo_timestamp : 32; // [31:0] 87*5113495bSYour Name #endif 88*5113495bSYour Name }; 89*5113495bSYour Name 90*5113495bSYour Name 91*5113495bSYour Name /* Description RXPCU_MPDU_FILTER_IN_CATEGORY 92*5113495bSYour Name 93*5113495bSYour Name Field indicates what the reason was that this MPDU frame 94*5113495bSYour Name was allowed to come into the receive path by RXPCU 95*5113495bSYour Name <enum 0 rxpcu_filter_pass> This MPDU passed the normal frame 96*5113495bSYour Name filter programming of rxpcu 97*5113495bSYour Name <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 98*5113495bSYour Name regular frame filter and would have been dropped, were 99*5113495bSYour Name it not for the frame fitting into the 'monitor_client' category. 100*5113495bSYour Name 101*5113495bSYour Name <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 102*5113495bSYour Name regular frame filter and also did not pass the rxpcu_monitor_client 103*5113495bSYour Name filter. It would have been dropped accept that it did pass 104*5113495bSYour Name the 'monitor_other' category. 105*5113495bSYour Name <enum 3 rxpcu_filter_pass_monitor_ovrd> This MPDU passed 106*5113495bSYour Name the normal frame filter programming of RXPCU but additionally 107*5113495bSYour Name fit into the 'monitor_override_client' category. 108*5113495bSYour Name <legal 0-3> 109*5113495bSYour Name */ 110*5113495bSYour Name 111*5113495bSYour Name #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 112*5113495bSYour Name #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 113*5113495bSYour Name #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 114*5113495bSYour Name #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 115*5113495bSYour Name 116*5113495bSYour Name 117*5113495bSYour Name /* Description SW_FRAME_GROUP_ID 118*5113495bSYour Name 119*5113495bSYour Name SW processes frames based on certain classifications. This 120*5113495bSYour Name field indicates to what sw classification this MPDU is 121*5113495bSYour Name mapped. 122*5113495bSYour Name The classification is given in priority order 123*5113495bSYour Name 124*5113495bSYour Name <enum 0 sw_frame_group_NDP_frame> 125*5113495bSYour Name 126*5113495bSYour Name <enum 1 sw_frame_group_Multicast_data> 127*5113495bSYour Name <enum 2 sw_frame_group_Unicast_data> 128*5113495bSYour Name <enum 3 sw_frame_group_Null_data > This includes mpdus of 129*5113495bSYour Name type Data Null. 130*5113495bSYour Name Hamilton v1 included QoS Data Null as well here. 131*5113495bSYour Name <enum 38 sw_frame_group_QoS_Null_data> This includes QoS 132*5113495bSYour Name Null frames except in UL MU or TB PPDUs. 133*5113495bSYour Name <enum 39 sw_frame_group_QoS_Null_data_TB> This includes 134*5113495bSYour Name QoS Null frames in UL MU or TB PPDUs. 135*5113495bSYour Name 136*5113495bSYour Name <enum 4 sw_frame_group_mgmt_0000 > 137*5113495bSYour Name <enum 5 sw_frame_group_mgmt_0001 > 138*5113495bSYour Name <enum 6 sw_frame_group_mgmt_0010 > 139*5113495bSYour Name <enum 7 sw_frame_group_mgmt_0011 > 140*5113495bSYour Name <enum 8 sw_frame_group_mgmt_0100 > 141*5113495bSYour Name <enum 9 sw_frame_group_mgmt_0101 > 142*5113495bSYour Name <enum 10 sw_frame_group_mgmt_0110 > 143*5113495bSYour Name <enum 11 sw_frame_group_mgmt_0111 > 144*5113495bSYour Name <enum 12 sw_frame_group_mgmt_1000 > 145*5113495bSYour Name <enum 13 sw_frame_group_mgmt_1001 > 146*5113495bSYour Name <enum 14 sw_frame_group_mgmt_1010 > 147*5113495bSYour Name <enum 15 sw_frame_group_mgmt_1011 > 148*5113495bSYour Name <enum 16 sw_frame_group_mgmt_1100 > 149*5113495bSYour Name <enum 17 sw_frame_group_mgmt_1101 > 150*5113495bSYour Name <enum 18 sw_frame_group_mgmt_1110 > 151*5113495bSYour Name <enum 19 sw_frame_group_mgmt_1111 > 152*5113495bSYour Name 153*5113495bSYour Name <enum 20 sw_frame_group_ctrl_0000 > 154*5113495bSYour Name <enum 21 sw_frame_group_ctrl_0001 > 155*5113495bSYour Name <enum 22 sw_frame_group_ctrl_0010 > 156*5113495bSYour Name <enum 23 sw_frame_group_ctrl_0011 > 157*5113495bSYour Name <enum 24 sw_frame_group_ctrl_0100 > 158*5113495bSYour Name <enum 25 sw_frame_group_ctrl_0101 > 159*5113495bSYour Name <enum 26 sw_frame_group_ctrl_0110 > 160*5113495bSYour Name <enum 27 sw_frame_group_ctrl_0111 > 161*5113495bSYour Name <enum 28 sw_frame_group_ctrl_1000 > 162*5113495bSYour Name <enum 29 sw_frame_group_ctrl_1001 > 163*5113495bSYour Name <enum 30 sw_frame_group_ctrl_1010 > 164*5113495bSYour Name <enum 31 sw_frame_group_ctrl_1011 > 165*5113495bSYour Name <enum 32 sw_frame_group_ctrl_1100 > 166*5113495bSYour Name <enum 33 sw_frame_group_ctrl_1101 > 167*5113495bSYour Name <enum 34 sw_frame_group_ctrl_1110 > 168*5113495bSYour Name <enum 35 sw_frame_group_ctrl_1111 > 169*5113495bSYour Name 170*5113495bSYour Name <enum 36 sw_frame_group_unsupported> This covers type 3 171*5113495bSYour Name and protocol version != 0 172*5113495bSYour Name 173*5113495bSYour Name <enum 37 sw_frame_group_phy_error> PHY reported an error 174*5113495bSYour Name 175*5113495bSYour Name 176*5113495bSYour Name <legal 0-39> 177*5113495bSYour Name */ 178*5113495bSYour Name 179*5113495bSYour Name #define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 180*5113495bSYour Name #define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2 181*5113495bSYour Name #define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8 182*5113495bSYour Name #define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc 183*5113495bSYour Name 184*5113495bSYour Name 185*5113495bSYour Name /* Description RESERVED_0 186*5113495bSYour Name 187*5113495bSYour Name <legal 0> 188*5113495bSYour Name */ 189*5113495bSYour Name 190*5113495bSYour Name #define RX_MPDU_END_RESERVED_0_OFFSET 0x0000000000000000 191*5113495bSYour Name #define RX_MPDU_END_RESERVED_0_LSB 9 192*5113495bSYour Name #define RX_MPDU_END_RESERVED_0_MSB 15 193*5113495bSYour Name #define RX_MPDU_END_RESERVED_0_MASK 0x000000000000fe00 194*5113495bSYour Name 195*5113495bSYour Name 196*5113495bSYour Name /* Description PHY_PPDU_ID 197*5113495bSYour Name 198*5113495bSYour Name A ppdu counter value that PHY increments for every PPDU 199*5113495bSYour Name received. The counter value wraps around 200*5113495bSYour Name <legal all> 201*5113495bSYour Name */ 202*5113495bSYour Name 203*5113495bSYour Name #define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 204*5113495bSYour Name #define RX_MPDU_END_PHY_PPDU_ID_LSB 16 205*5113495bSYour Name #define RX_MPDU_END_PHY_PPDU_ID_MSB 31 206*5113495bSYour Name #define RX_MPDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 207*5113495bSYour Name 208*5113495bSYour Name 209*5113495bSYour Name /* Description RESERVED_1A 210*5113495bSYour Name 211*5113495bSYour Name <legal 0> 212*5113495bSYour Name */ 213*5113495bSYour Name 214*5113495bSYour Name #define RX_MPDU_END_RESERVED_1A_OFFSET 0x0000000000000000 215*5113495bSYour Name #define RX_MPDU_END_RESERVED_1A_LSB 32 216*5113495bSYour Name #define RX_MPDU_END_RESERVED_1A_MSB 42 217*5113495bSYour Name #define RX_MPDU_END_RESERVED_1A_MASK 0x000007ff00000000 218*5113495bSYour Name 219*5113495bSYour Name 220*5113495bSYour Name /* Description UNSUP_KTYPE_SHORT_FRAME 221*5113495bSYour Name 222*5113495bSYour Name This bit will be '1' when WEP or TKIP or WAPI key type is 223*5113495bSYour Name received for 11ah short frame. Crypto will bypass the 224*5113495bSYour Name received packet without decryption to RxOLE after setting 225*5113495bSYour Name this bit. 226*5113495bSYour Name */ 227*5113495bSYour Name 228*5113495bSYour Name #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x0000000000000000 229*5113495bSYour Name #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 43 230*5113495bSYour Name #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 43 231*5113495bSYour Name #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x0000080000000000 232*5113495bSYour Name 233*5113495bSYour Name 234*5113495bSYour Name /* Description RX_IN_TX_DECRYPT_BYP 235*5113495bSYour Name 236*5113495bSYour Name Indicates that RX packet is not decrypted as Crypto is busy 237*5113495bSYour Name with TX packet processing. 238*5113495bSYour Name */ 239*5113495bSYour Name 240*5113495bSYour Name #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 241*5113495bSYour Name #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 44 242*5113495bSYour Name #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 44 243*5113495bSYour Name #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000100000000000 244*5113495bSYour Name 245*5113495bSYour Name 246*5113495bSYour Name /* Description OVERFLOW_ERR 247*5113495bSYour Name 248*5113495bSYour Name RXPCU Receive FIFO ran out of space to receive the full 249*5113495bSYour Name MPDU. Therefor this MPDU is terminated early and is thus 250*5113495bSYour Name corrupted. 251*5113495bSYour Name 252*5113495bSYour Name This MPDU will not be ACKed. 253*5113495bSYour Name RXPCU might still be able to correctly receive the following 254*5113495bSYour Name MPDUs in the PPDU if enough fifo space became available 255*5113495bSYour Name in time 256*5113495bSYour Name */ 257*5113495bSYour Name 258*5113495bSYour Name #define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000000 259*5113495bSYour Name #define RX_MPDU_END_OVERFLOW_ERR_LSB 45 260*5113495bSYour Name #define RX_MPDU_END_OVERFLOW_ERR_MSB 45 261*5113495bSYour Name #define RX_MPDU_END_OVERFLOW_ERR_MASK 0x0000200000000000 262*5113495bSYour Name 263*5113495bSYour Name 264*5113495bSYour Name /* Description MPDU_LENGTH_ERR 265*5113495bSYour Name 266*5113495bSYour Name Set by RXPCU if the expected MPDU length does not correspond 267*5113495bSYour Name with the actually received number of bytes in the MPDU. 268*5113495bSYour Name 269*5113495bSYour Name */ 270*5113495bSYour Name 271*5113495bSYour Name #define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 272*5113495bSYour Name #define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 46 273*5113495bSYour Name #define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 46 274*5113495bSYour Name #define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x0000400000000000 275*5113495bSYour Name 276*5113495bSYour Name 277*5113495bSYour Name /* Description TKIP_MIC_ERR 278*5113495bSYour Name 279*5113495bSYour Name Set by RX CRYPTO when CRYPTO detected a TKIP MIC error for 280*5113495bSYour Name this MPDU 281*5113495bSYour Name */ 282*5113495bSYour Name 283*5113495bSYour Name #define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000000 284*5113495bSYour Name #define RX_MPDU_END_TKIP_MIC_ERR_LSB 47 285*5113495bSYour Name #define RX_MPDU_END_TKIP_MIC_ERR_MSB 47 286*5113495bSYour Name #define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x0000800000000000 287*5113495bSYour Name 288*5113495bSYour Name 289*5113495bSYour Name /* Description DECRYPT_ERR 290*5113495bSYour Name 291*5113495bSYour Name Set by RX CRYPTO when CRYPTO detected a decrypt error for 292*5113495bSYour Name this MPDU or CRYPTO received an encrypted frame, but did 293*5113495bSYour Name not get a valid corresponding key id in the peer entry. 294*5113495bSYour Name 295*5113495bSYour Name */ 296*5113495bSYour Name 297*5113495bSYour Name #define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x0000000000000000 298*5113495bSYour Name #define RX_MPDU_END_DECRYPT_ERR_LSB 48 299*5113495bSYour Name #define RX_MPDU_END_DECRYPT_ERR_MSB 48 300*5113495bSYour Name #define RX_MPDU_END_DECRYPT_ERR_MASK 0x0001000000000000 301*5113495bSYour Name 302*5113495bSYour Name 303*5113495bSYour Name /* Description UNENCRYPTED_FRAME_ERR 304*5113495bSYour Name 305*5113495bSYour Name Set by RX CRYPTO when CRYPTO detected an unencrypted frame 306*5113495bSYour Name while in the peer entry field 'All_frames_shall_be_encrypted' 307*5113495bSYour Name is set. 308*5113495bSYour Name */ 309*5113495bSYour Name 310*5113495bSYour Name #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 311*5113495bSYour Name #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 49 312*5113495bSYour Name #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 49 313*5113495bSYour Name #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0002000000000000 314*5113495bSYour Name 315*5113495bSYour Name 316*5113495bSYour Name /* Description PN_FIELDS_CONTAIN_VALID_INFO 317*5113495bSYour Name 318*5113495bSYour Name Set by RX CRYPTO to indicate that there is a valid PN field 319*5113495bSYour Name present in this MPDU 320*5113495bSYour Name */ 321*5113495bSYour Name 322*5113495bSYour Name #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000000000000 323*5113495bSYour Name #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 50 324*5113495bSYour Name #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 50 325*5113495bSYour Name #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x0004000000000000 326*5113495bSYour Name 327*5113495bSYour Name 328*5113495bSYour Name /* Description FCS_ERR 329*5113495bSYour Name 330*5113495bSYour Name Set by RXPCU when there is an FCS error detected for this 331*5113495bSYour Name MPDU 332*5113495bSYour Name NOTE that when this field is set, all other (error) field 333*5113495bSYour Name settings should be ignored as modules could have made wrong 334*5113495bSYour Name decisions based on the corrupted data. 335*5113495bSYour Name */ 336*5113495bSYour Name 337*5113495bSYour Name #define RX_MPDU_END_FCS_ERR_OFFSET 0x0000000000000000 338*5113495bSYour Name #define RX_MPDU_END_FCS_ERR_LSB 51 339*5113495bSYour Name #define RX_MPDU_END_FCS_ERR_MSB 51 340*5113495bSYour Name #define RX_MPDU_END_FCS_ERR_MASK 0x0008000000000000 341*5113495bSYour Name 342*5113495bSYour Name 343*5113495bSYour Name /* Description MSDU_LENGTH_ERR 344*5113495bSYour Name 345*5113495bSYour Name Set by RXOLE when there is an msdu length error detected 346*5113495bSYour Name in at least 1 of the MSDUs embedded within the MPDU 347*5113495bSYour Name */ 348*5113495bSYour Name 349*5113495bSYour Name #define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 350*5113495bSYour Name #define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 52 351*5113495bSYour Name #define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 52 352*5113495bSYour Name #define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x0010000000000000 353*5113495bSYour Name 354*5113495bSYour Name 355*5113495bSYour Name /* Description RXDMA0_DESTINATION_RING 356*5113495bSYour Name 357*5113495bSYour Name The ring to which RXDMA0 shall push the frame, assuming 358*5113495bSYour Name no MPDU level errors are detected. In case of MPDU level 359*5113495bSYour Name errors, RXDMA0 might change the RXDMA0 destination 360*5113495bSYour Name 361*5113495bSYour Name <enum 0 rxdma_release_ring > RXDMA0 shall push the frame 362*5113495bSYour Name to the Release ring. Effectively this means the frame needs 363*5113495bSYour Name to be dropped. 364*5113495bSYour Name 365*5113495bSYour Name <enum 1 rxdma2fw_pmac0_ring > RXDMA0 shall push the frame 366*5113495bSYour Name to the FW ring for PMAC0. 367*5113495bSYour Name 368*5113495bSYour Name <enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to 369*5113495bSYour Name the SW ring 370*5113495bSYour Name 371*5113495bSYour Name <enum 3 rxdma2reo_ring > RXDMA0 shall push the frame to 372*5113495bSYour Name the REO entrance ring 373*5113495bSYour Name 374*5113495bSYour Name <enum 4 rxdma2fw_pmac1_ring> RXDMA0 shall push the frame 375*5113495bSYour Name to the FW ring for PMAC1. 376*5113495bSYour Name 377*5113495bSYour Name <enum 5 rxdma2reo_remote0_ring> RXDMA0 shall push the frame 378*5113495bSYour Name to the first MLO REO entrance ring. 379*5113495bSYour Name 380*5113495bSYour Name <enum 6 rxdma2reo_remote1_ring> RXDMA0 shall push the frame 381*5113495bSYour Name to the second MLO REO entrance ring. 382*5113495bSYour Name 383*5113495bSYour Name <legal 0 - 6> 384*5113495bSYour Name */ 385*5113495bSYour Name 386*5113495bSYour Name #define RX_MPDU_END_RXDMA0_DESTINATION_RING_OFFSET 0x0000000000000000 387*5113495bSYour Name #define RX_MPDU_END_RXDMA0_DESTINATION_RING_LSB 53 388*5113495bSYour Name #define RX_MPDU_END_RXDMA0_DESTINATION_RING_MSB 55 389*5113495bSYour Name #define RX_MPDU_END_RXDMA0_DESTINATION_RING_MASK 0x00e0000000000000 390*5113495bSYour Name 391*5113495bSYour Name 392*5113495bSYour Name /* Description RXDMA1_DESTINATION_RING 393*5113495bSYour Name 394*5113495bSYour Name The ring to which RXDMA1 shall push the frame, assuming 395*5113495bSYour Name no MPDU level errors are detected. In case of MPDU level 396*5113495bSYour Name errors, RXDMA1 might change the RXDMA destination 397*5113495bSYour Name 398*5113495bSYour Name <enum 0 rxdma_release_ring > DO NOT USE. 399*5113495bSYour Name 400*5113495bSYour Name <enum 1 rxdma2fw_pmac0_ring > DO NOT USE. 401*5113495bSYour Name 402*5113495bSYour Name <enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to 403*5113495bSYour Name the SW ring 404*5113495bSYour Name 405*5113495bSYour Name <enum 3 rxdma2reo_ring > DO NOT USE. 406*5113495bSYour Name 407*5113495bSYour Name <enum 4 rxdma2fw_pmac1_ring> DO NOT USE. 408*5113495bSYour Name 409*5113495bSYour Name <enum 5 rxdma2reo_remote0_ring> DO NOT USE. 410*5113495bSYour Name 411*5113495bSYour Name <enum 6 rxdma2reo_remote1_ring> DO NOT USE. 412*5113495bSYour Name 413*5113495bSYour Name <legal 0 - 6> 414*5113495bSYour Name */ 415*5113495bSYour Name 416*5113495bSYour Name #define RX_MPDU_END_RXDMA1_DESTINATION_RING_OFFSET 0x0000000000000000 417*5113495bSYour Name #define RX_MPDU_END_RXDMA1_DESTINATION_RING_LSB 56 418*5113495bSYour Name #define RX_MPDU_END_RXDMA1_DESTINATION_RING_MSB 58 419*5113495bSYour Name #define RX_MPDU_END_RXDMA1_DESTINATION_RING_MASK 0x0700000000000000 420*5113495bSYour Name 421*5113495bSYour Name 422*5113495bSYour Name /* Description DECRYPT_STATUS_CODE 423*5113495bSYour Name 424*5113495bSYour Name Field provides insight into the decryption performed 425*5113495bSYour Name 426*5113495bSYour Name <enum 0 decrypt_ok> Frame had protection enabled and decrypted 427*5113495bSYour Name properly 428*5113495bSYour Name <enum 1 decrypt_unprotected_frame > Frame is unprotected 429*5113495bSYour Name and hence bypassed 430*5113495bSYour Name <enum 2 decrypt_data_err > Frame has protection enabled 431*5113495bSYour Name and could not be properly decrypted due to MIC/ICV mismatch 432*5113495bSYour Name etc. 433*5113495bSYour Name <enum 3 decrypt_key_invalid > Frame has protection enabled 434*5113495bSYour Name but the key that was required to decrypt this frame was 435*5113495bSYour Name not valid 436*5113495bSYour Name <enum 4 decrypt_peer_entry_invalid > Frame has protection 437*5113495bSYour Name enabled but the key that was required to decrypt this frame 438*5113495bSYour Name was not valid 439*5113495bSYour Name <enum 5 decrypt_other > Reserved for other indications 440*5113495bSYour Name 441*5113495bSYour Name <legal 0 - 5> 442*5113495bSYour Name */ 443*5113495bSYour Name 444*5113495bSYour Name #define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000000 445*5113495bSYour Name #define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 59 446*5113495bSYour Name #define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 61 447*5113495bSYour Name #define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x3800000000000000 448*5113495bSYour Name 449*5113495bSYour Name 450*5113495bSYour Name /* Description RX_BITMAP_NOT_UPDATED 451*5113495bSYour Name 452*5113495bSYour Name Frame is received, but RXPCU could not update the receive 453*5113495bSYour Name bitmap due to (temporary) fifo contraints. 454*5113495bSYour Name <legal all> 455*5113495bSYour Name */ 456*5113495bSYour Name 457*5113495bSYour Name #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000000 458*5113495bSYour Name #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 62 459*5113495bSYour Name #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 62 460*5113495bSYour Name #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x4000000000000000 461*5113495bSYour Name 462*5113495bSYour Name 463*5113495bSYour Name /* Description RESERVED_1B 464*5113495bSYour Name 465*5113495bSYour Name <legal 0> 466*5113495bSYour Name */ 467*5113495bSYour Name 468*5113495bSYour Name #define RX_MPDU_END_RESERVED_1B_OFFSET 0x0000000000000000 469*5113495bSYour Name #define RX_MPDU_END_RESERVED_1B_LSB 63 470*5113495bSYour Name #define RX_MPDU_END_RESERVED_1B_MSB 63 471*5113495bSYour Name #define RX_MPDU_END_RESERVED_1B_MASK 0x8000000000000000 472*5113495bSYour Name 473*5113495bSYour Name 474*5113495bSYour Name /* Description RESERVED_2A 475*5113495bSYour Name 476*5113495bSYour Name <legal 0> 477*5113495bSYour Name */ 478*5113495bSYour Name 479*5113495bSYour Name #define RX_MPDU_END_RESERVED_2A_OFFSET 0x0000000000000008 480*5113495bSYour Name #define RX_MPDU_END_RESERVED_2A_LSB 0 481*5113495bSYour Name #define RX_MPDU_END_RESERVED_2A_MSB 14 482*5113495bSYour Name #define RX_MPDU_END_RESERVED_2A_MASK 0x0000000000007fff 483*5113495bSYour Name 484*5113495bSYour Name 485*5113495bSYour Name /* Description RXPCU_MGMT_SEQUENCE_NR_VALID 486*5113495bSYour Name 487*5113495bSYour Name This field gets set by RXPCU when the received management 488*5113495bSYour Name frame is destined to this device, passes FCS and is categorized 489*5113495bSYour Name as one for which RXPCU should assign a rxpcu_mgmt_sequence_number. 490*5113495bSYour Name After assigning a number, the RXPCU will increment the sequence 491*5113495bSYour Name number for the next management frame that meets these criteria. 492*5113495bSYour Name 493*5113495bSYour Name 494*5113495bSYour Name <legal all> 495*5113495bSYour Name */ 496*5113495bSYour Name 497*5113495bSYour Name #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x0000000000000008 498*5113495bSYour Name #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15 499*5113495bSYour Name #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15 500*5113495bSYour Name #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x0000000000008000 501*5113495bSYour Name 502*5113495bSYour Name 503*5113495bSYour Name /* Description RXPCU_MGMT_SEQUENCE_NR 504*5113495bSYour Name 505*5113495bSYour Name Field only valid when rxpcu_mgmt_sequence_nr_valid is set 506*5113495bSYour Name 507*5113495bSYour Name 508*5113495bSYour Name This RXPCU generated sequence number is assigned to this 509*5113495bSYour Name management frame. It is used by FW and host SW for management 510*5113495bSYour Name frame reordering across multiple bands/links. 511*5113495bSYour Name 512*5113495bSYour Name <legal all> 513*5113495bSYour Name */ 514*5113495bSYour Name 515*5113495bSYour Name #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x0000000000000008 516*5113495bSYour Name #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16 517*5113495bSYour Name #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31 518*5113495bSYour Name #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0x00000000ffff0000 519*5113495bSYour Name 520*5113495bSYour Name 521*5113495bSYour Name /* Description RXFRAME_ASSERT_MLO_TIMESTAMP 522*5113495bSYour Name 523*5113495bSYour Name 'mlo_global_timestamp' that indicates when for the PPDU 524*5113495bSYour Name that contained this MPDU, the 'rx_frame' signal got asserted. 525*5113495bSYour Name 526*5113495bSYour Name 527*5113495bSYour Name This field is always valid, irrespective of the frame being 528*5113495bSYour Name related to MLO reception or not. It is used by FW and host 529*5113495bSYour Name SW for management frame reordering purposes. 530*5113495bSYour Name 531*5113495bSYour Name <legal all> 532*5113495bSYour Name */ 533*5113495bSYour Name 534*5113495bSYour Name #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_OFFSET 0x0000000000000008 535*5113495bSYour Name #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_LSB 32 536*5113495bSYour Name #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MSB 63 537*5113495bSYour Name #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MASK 0xffffffff00000000 538*5113495bSYour Name 539*5113495bSYour Name 540*5113495bSYour Name 541*5113495bSYour Name #endif // RX_MPDU_END 542