1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_MPDU_END_H_ 27 #define _RX_MPDU_END_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_RX_MPDU_END 4 32 33 #define NUM_OF_QWORDS_RX_MPDU_END 2 34 35 36 struct rx_mpdu_end { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] 39 sw_frame_group_id : 7, // [8:2] 40 reserved_0 : 7, // [15:9] 41 phy_ppdu_id : 16; // [31:16] 42 uint32_t reserved_1a : 11, // [10:0] 43 unsup_ktype_short_frame : 1, // [11:11] 44 rx_in_tx_decrypt_byp : 1, // [12:12] 45 overflow_err : 1, // [13:13] 46 mpdu_length_err : 1, // [14:14] 47 tkip_mic_err : 1, // [15:15] 48 decrypt_err : 1, // [16:16] 49 unencrypted_frame_err : 1, // [17:17] 50 pn_fields_contain_valid_info : 1, // [18:18] 51 fcs_err : 1, // [19:19] 52 msdu_length_err : 1, // [20:20] 53 rxdma0_destination_ring : 3, // [23:21] 54 rxdma1_destination_ring : 3, // [26:24] 55 decrypt_status_code : 3, // [29:27] 56 rx_bitmap_not_updated : 1, // [30:30] 57 reserved_1b : 1; // [31:31] 58 uint32_t reserved_2a : 15, // [14:0] 59 rxpcu_mgmt_sequence_nr_valid : 1, // [15:15] 60 rxpcu_mgmt_sequence_nr : 16; // [31:16] 61 uint32_t rxframe_assert_mlo_timestamp : 32; // [31:0] 62 #else 63 uint32_t phy_ppdu_id : 16, // [31:16] 64 reserved_0 : 7, // [15:9] 65 sw_frame_group_id : 7, // [8:2] 66 rxpcu_mpdu_filter_in_category : 2; // [1:0] 67 uint32_t reserved_1b : 1, // [31:31] 68 rx_bitmap_not_updated : 1, // [30:30] 69 decrypt_status_code : 3, // [29:27] 70 rxdma1_destination_ring : 3, // [26:24] 71 rxdma0_destination_ring : 3, // [23:21] 72 msdu_length_err : 1, // [20:20] 73 fcs_err : 1, // [19:19] 74 pn_fields_contain_valid_info : 1, // [18:18] 75 unencrypted_frame_err : 1, // [17:17] 76 decrypt_err : 1, // [16:16] 77 tkip_mic_err : 1, // [15:15] 78 mpdu_length_err : 1, // [14:14] 79 overflow_err : 1, // [13:13] 80 rx_in_tx_decrypt_byp : 1, // [12:12] 81 unsup_ktype_short_frame : 1, // [11:11] 82 reserved_1a : 11; // [10:0] 83 uint32_t rxpcu_mgmt_sequence_nr : 16, // [31:16] 84 rxpcu_mgmt_sequence_nr_valid : 1, // [15:15] 85 reserved_2a : 15; // [14:0] 86 uint32_t rxframe_assert_mlo_timestamp : 32; // [31:0] 87 #endif 88 }; 89 90 91 /* Description RXPCU_MPDU_FILTER_IN_CATEGORY 92 93 Field indicates what the reason was that this MPDU frame 94 was allowed to come into the receive path by RXPCU 95 <enum 0 rxpcu_filter_pass> This MPDU passed the normal frame 96 filter programming of rxpcu 97 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 98 regular frame filter and would have been dropped, were 99 it not for the frame fitting into the 'monitor_client' category. 100 101 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 102 regular frame filter and also did not pass the rxpcu_monitor_client 103 filter. It would have been dropped accept that it did pass 104 the 'monitor_other' category. 105 <enum 3 rxpcu_filter_pass_monitor_ovrd> This MPDU passed 106 the normal frame filter programming of RXPCU but additionally 107 fit into the 'monitor_override_client' category. 108 <legal 0-3> 109 */ 110 111 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 112 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 113 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 114 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 115 116 117 /* Description SW_FRAME_GROUP_ID 118 119 SW processes frames based on certain classifications. This 120 field indicates to what sw classification this MPDU is 121 mapped. 122 The classification is given in priority order 123 124 <enum 0 sw_frame_group_NDP_frame> 125 126 <enum 1 sw_frame_group_Multicast_data> 127 <enum 2 sw_frame_group_Unicast_data> 128 <enum 3 sw_frame_group_Null_data > This includes mpdus of 129 type Data Null. 130 Hamilton v1 included QoS Data Null as well here. 131 <enum 38 sw_frame_group_QoS_Null_data> This includes QoS 132 Null frames except in UL MU or TB PPDUs. 133 <enum 39 sw_frame_group_QoS_Null_data_TB> This includes 134 QoS Null frames in UL MU or TB PPDUs. 135 136 <enum 4 sw_frame_group_mgmt_0000 > 137 <enum 5 sw_frame_group_mgmt_0001 > 138 <enum 6 sw_frame_group_mgmt_0010 > 139 <enum 7 sw_frame_group_mgmt_0011 > 140 <enum 8 sw_frame_group_mgmt_0100 > 141 <enum 9 sw_frame_group_mgmt_0101 > 142 <enum 10 sw_frame_group_mgmt_0110 > 143 <enum 11 sw_frame_group_mgmt_0111 > 144 <enum 12 sw_frame_group_mgmt_1000 > 145 <enum 13 sw_frame_group_mgmt_1001 > 146 <enum 14 sw_frame_group_mgmt_1010 > 147 <enum 15 sw_frame_group_mgmt_1011 > 148 <enum 16 sw_frame_group_mgmt_1100 > 149 <enum 17 sw_frame_group_mgmt_1101 > 150 <enum 18 sw_frame_group_mgmt_1110 > 151 <enum 19 sw_frame_group_mgmt_1111 > 152 153 <enum 20 sw_frame_group_ctrl_0000 > 154 <enum 21 sw_frame_group_ctrl_0001 > 155 <enum 22 sw_frame_group_ctrl_0010 > 156 <enum 23 sw_frame_group_ctrl_0011 > 157 <enum 24 sw_frame_group_ctrl_0100 > 158 <enum 25 sw_frame_group_ctrl_0101 > 159 <enum 26 sw_frame_group_ctrl_0110 > 160 <enum 27 sw_frame_group_ctrl_0111 > 161 <enum 28 sw_frame_group_ctrl_1000 > 162 <enum 29 sw_frame_group_ctrl_1001 > 163 <enum 30 sw_frame_group_ctrl_1010 > 164 <enum 31 sw_frame_group_ctrl_1011 > 165 <enum 32 sw_frame_group_ctrl_1100 > 166 <enum 33 sw_frame_group_ctrl_1101 > 167 <enum 34 sw_frame_group_ctrl_1110 > 168 <enum 35 sw_frame_group_ctrl_1111 > 169 170 <enum 36 sw_frame_group_unsupported> This covers type 3 171 and protocol version != 0 172 173 <enum 37 sw_frame_group_phy_error> PHY reported an error 174 175 176 <legal 0-39> 177 */ 178 179 #define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 180 #define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2 181 #define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8 182 #define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc 183 184 185 /* Description RESERVED_0 186 187 <legal 0> 188 */ 189 190 #define RX_MPDU_END_RESERVED_0_OFFSET 0x0000000000000000 191 #define RX_MPDU_END_RESERVED_0_LSB 9 192 #define RX_MPDU_END_RESERVED_0_MSB 15 193 #define RX_MPDU_END_RESERVED_0_MASK 0x000000000000fe00 194 195 196 /* Description PHY_PPDU_ID 197 198 A ppdu counter value that PHY increments for every PPDU 199 received. The counter value wraps around 200 <legal all> 201 */ 202 203 #define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 204 #define RX_MPDU_END_PHY_PPDU_ID_LSB 16 205 #define RX_MPDU_END_PHY_PPDU_ID_MSB 31 206 #define RX_MPDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 207 208 209 /* Description RESERVED_1A 210 211 <legal 0> 212 */ 213 214 #define RX_MPDU_END_RESERVED_1A_OFFSET 0x0000000000000000 215 #define RX_MPDU_END_RESERVED_1A_LSB 32 216 #define RX_MPDU_END_RESERVED_1A_MSB 42 217 #define RX_MPDU_END_RESERVED_1A_MASK 0x000007ff00000000 218 219 220 /* Description UNSUP_KTYPE_SHORT_FRAME 221 222 This bit will be '1' when WEP or TKIP or WAPI key type is 223 received for 11ah short frame. Crypto will bypass the 224 received packet without decryption to RxOLE after setting 225 this bit. 226 */ 227 228 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x0000000000000000 229 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 43 230 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 43 231 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x0000080000000000 232 233 234 /* Description RX_IN_TX_DECRYPT_BYP 235 236 Indicates that RX packet is not decrypted as Crypto is busy 237 with TX packet processing. 238 */ 239 240 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 241 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 44 242 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 44 243 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000100000000000 244 245 246 /* Description OVERFLOW_ERR 247 248 RXPCU Receive FIFO ran out of space to receive the full 249 MPDU. Therefor this MPDU is terminated early and is thus 250 corrupted. 251 252 This MPDU will not be ACKed. 253 RXPCU might still be able to correctly receive the following 254 MPDUs in the PPDU if enough fifo space became available 255 in time 256 */ 257 258 #define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000000 259 #define RX_MPDU_END_OVERFLOW_ERR_LSB 45 260 #define RX_MPDU_END_OVERFLOW_ERR_MSB 45 261 #define RX_MPDU_END_OVERFLOW_ERR_MASK 0x0000200000000000 262 263 264 /* Description MPDU_LENGTH_ERR 265 266 Set by RXPCU if the expected MPDU length does not correspond 267 with the actually received number of bytes in the MPDU. 268 269 */ 270 271 #define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 272 #define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 46 273 #define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 46 274 #define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x0000400000000000 275 276 277 /* Description TKIP_MIC_ERR 278 279 Set by RX CRYPTO when CRYPTO detected a TKIP MIC error for 280 this MPDU 281 */ 282 283 #define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000000 284 #define RX_MPDU_END_TKIP_MIC_ERR_LSB 47 285 #define RX_MPDU_END_TKIP_MIC_ERR_MSB 47 286 #define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x0000800000000000 287 288 289 /* Description DECRYPT_ERR 290 291 Set by RX CRYPTO when CRYPTO detected a decrypt error for 292 this MPDU or CRYPTO received an encrypted frame, but did 293 not get a valid corresponding key id in the peer entry. 294 295 */ 296 297 #define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x0000000000000000 298 #define RX_MPDU_END_DECRYPT_ERR_LSB 48 299 #define RX_MPDU_END_DECRYPT_ERR_MSB 48 300 #define RX_MPDU_END_DECRYPT_ERR_MASK 0x0001000000000000 301 302 303 /* Description UNENCRYPTED_FRAME_ERR 304 305 Set by RX CRYPTO when CRYPTO detected an unencrypted frame 306 while in the peer entry field 'All_frames_shall_be_encrypted' 307 is set. 308 */ 309 310 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 311 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 49 312 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 49 313 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0002000000000000 314 315 316 /* Description PN_FIELDS_CONTAIN_VALID_INFO 317 318 Set by RX CRYPTO to indicate that there is a valid PN field 319 present in this MPDU 320 */ 321 322 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000000000000 323 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 50 324 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 50 325 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x0004000000000000 326 327 328 /* Description FCS_ERR 329 330 Set by RXPCU when there is an FCS error detected for this 331 MPDU 332 NOTE that when this field is set, all other (error) field 333 settings should be ignored as modules could have made wrong 334 decisions based on the corrupted data. 335 */ 336 337 #define RX_MPDU_END_FCS_ERR_OFFSET 0x0000000000000000 338 #define RX_MPDU_END_FCS_ERR_LSB 51 339 #define RX_MPDU_END_FCS_ERR_MSB 51 340 #define RX_MPDU_END_FCS_ERR_MASK 0x0008000000000000 341 342 343 /* Description MSDU_LENGTH_ERR 344 345 Set by RXOLE when there is an msdu length error detected 346 in at least 1 of the MSDUs embedded within the MPDU 347 */ 348 349 #define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 350 #define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 52 351 #define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 52 352 #define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x0010000000000000 353 354 355 /* Description RXDMA0_DESTINATION_RING 356 357 The ring to which RXDMA0 shall push the frame, assuming 358 no MPDU level errors are detected. In case of MPDU level 359 errors, RXDMA0 might change the RXDMA0 destination 360 361 <enum 0 rxdma_release_ring > RXDMA0 shall push the frame 362 to the Release ring. Effectively this means the frame needs 363 to be dropped. 364 365 <enum 1 rxdma2fw_pmac0_ring > RXDMA0 shall push the frame 366 to the FW ring for PMAC0. 367 368 <enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to 369 the SW ring 370 371 <enum 3 rxdma2reo_ring > RXDMA0 shall push the frame to 372 the REO entrance ring 373 374 <enum 4 rxdma2fw_pmac1_ring> RXDMA0 shall push the frame 375 to the FW ring for PMAC1. 376 377 <enum 5 rxdma2reo_remote0_ring> RXDMA0 shall push the frame 378 to the first MLO REO entrance ring. 379 380 <enum 6 rxdma2reo_remote1_ring> RXDMA0 shall push the frame 381 to the second MLO REO entrance ring. 382 383 <legal 0 - 6> 384 */ 385 386 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_OFFSET 0x0000000000000000 387 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_LSB 53 388 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_MSB 55 389 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_MASK 0x00e0000000000000 390 391 392 /* Description RXDMA1_DESTINATION_RING 393 394 The ring to which RXDMA1 shall push the frame, assuming 395 no MPDU level errors are detected. In case of MPDU level 396 errors, RXDMA1 might change the RXDMA destination 397 398 <enum 0 rxdma_release_ring > DO NOT USE. 399 400 <enum 1 rxdma2fw_pmac0_ring > DO NOT USE. 401 402 <enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to 403 the SW ring 404 405 <enum 3 rxdma2reo_ring > DO NOT USE. 406 407 <enum 4 rxdma2fw_pmac1_ring> DO NOT USE. 408 409 <enum 5 rxdma2reo_remote0_ring> DO NOT USE. 410 411 <enum 6 rxdma2reo_remote1_ring> DO NOT USE. 412 413 <legal 0 - 6> 414 */ 415 416 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_OFFSET 0x0000000000000000 417 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_LSB 56 418 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_MSB 58 419 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_MASK 0x0700000000000000 420 421 422 /* Description DECRYPT_STATUS_CODE 423 424 Field provides insight into the decryption performed 425 426 <enum 0 decrypt_ok> Frame had protection enabled and decrypted 427 properly 428 <enum 1 decrypt_unprotected_frame > Frame is unprotected 429 and hence bypassed 430 <enum 2 decrypt_data_err > Frame has protection enabled 431 and could not be properly decrypted due to MIC/ICV mismatch 432 etc. 433 <enum 3 decrypt_key_invalid > Frame has protection enabled 434 but the key that was required to decrypt this frame was 435 not valid 436 <enum 4 decrypt_peer_entry_invalid > Frame has protection 437 enabled but the key that was required to decrypt this frame 438 was not valid 439 <enum 5 decrypt_other > Reserved for other indications 440 441 <legal 0 - 5> 442 */ 443 444 #define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000000 445 #define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 59 446 #define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 61 447 #define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x3800000000000000 448 449 450 /* Description RX_BITMAP_NOT_UPDATED 451 452 Frame is received, but RXPCU could not update the receive 453 bitmap due to (temporary) fifo contraints. 454 <legal all> 455 */ 456 457 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000000 458 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 62 459 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 62 460 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x4000000000000000 461 462 463 /* Description RESERVED_1B 464 465 <legal 0> 466 */ 467 468 #define RX_MPDU_END_RESERVED_1B_OFFSET 0x0000000000000000 469 #define RX_MPDU_END_RESERVED_1B_LSB 63 470 #define RX_MPDU_END_RESERVED_1B_MSB 63 471 #define RX_MPDU_END_RESERVED_1B_MASK 0x8000000000000000 472 473 474 /* Description RESERVED_2A 475 476 <legal 0> 477 */ 478 479 #define RX_MPDU_END_RESERVED_2A_OFFSET 0x0000000000000008 480 #define RX_MPDU_END_RESERVED_2A_LSB 0 481 #define RX_MPDU_END_RESERVED_2A_MSB 14 482 #define RX_MPDU_END_RESERVED_2A_MASK 0x0000000000007fff 483 484 485 /* Description RXPCU_MGMT_SEQUENCE_NR_VALID 486 487 This field gets set by RXPCU when the received management 488 frame is destined to this device, passes FCS and is categorized 489 as one for which RXPCU should assign a rxpcu_mgmt_sequence_number. 490 After assigning a number, the RXPCU will increment the sequence 491 number for the next management frame that meets these criteria. 492 493 494 <legal all> 495 */ 496 497 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x0000000000000008 498 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15 499 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15 500 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x0000000000008000 501 502 503 /* Description RXPCU_MGMT_SEQUENCE_NR 504 505 Field only valid when rxpcu_mgmt_sequence_nr_valid is set 506 507 508 This RXPCU generated sequence number is assigned to this 509 management frame. It is used by FW and host SW for management 510 frame reordering across multiple bands/links. 511 512 <legal all> 513 */ 514 515 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x0000000000000008 516 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16 517 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31 518 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0x00000000ffff0000 519 520 521 /* Description RXFRAME_ASSERT_MLO_TIMESTAMP 522 523 'mlo_global_timestamp' that indicates when for the PPDU 524 that contained this MPDU, the 'rx_frame' signal got asserted. 525 526 527 This field is always valid, irrespective of the frame being 528 related to MLO reception or not. It is used by FW and host 529 SW for management frame reordering purposes. 530 531 <legal all> 532 */ 533 534 #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_OFFSET 0x0000000000000008 535 #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_LSB 32 536 #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MSB 63 537 #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MASK 0xffffffff00000000 538 539 540 541 #endif // RX_MPDU_END 542