xref: /wlan-driver/fw-api/hw/qca5332/rx_mpdu_link_ptr.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1*5113495bSYour Name 
2*5113495bSYour Name /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3*5113495bSYour Name  *
4*5113495bSYour Name  * Permission to use, copy, modify, and/or distribute this software for any
5*5113495bSYour Name  * purpose with or without fee is hereby granted, provided that the above
6*5113495bSYour Name  * copyright notice and this permission notice appear in all copies.
7*5113495bSYour Name  *
8*5113495bSYour Name  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9*5113495bSYour Name  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10*5113495bSYour Name  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11*5113495bSYour Name  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12*5113495bSYour Name  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13*5113495bSYour Name  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14*5113495bSYour Name  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15*5113495bSYour Name  */
16*5113495bSYour Name 
17*5113495bSYour Name 
18*5113495bSYour Name 
19*5113495bSYour Name 
20*5113495bSYour Name 
21*5113495bSYour Name 
22*5113495bSYour Name 
23*5113495bSYour Name 
24*5113495bSYour Name 
25*5113495bSYour Name 
26*5113495bSYour Name #ifndef _RX_MPDU_LINK_PTR_H_
27*5113495bSYour Name #define _RX_MPDU_LINK_PTR_H_
28*5113495bSYour Name #if !defined(__ASSEMBLER__)
29*5113495bSYour Name #endif
30*5113495bSYour Name 
31*5113495bSYour Name #include "buffer_addr_info.h"
32*5113495bSYour Name #define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2
33*5113495bSYour Name 
34*5113495bSYour Name 
35*5113495bSYour Name struct rx_mpdu_link_ptr {
36*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
37*5113495bSYour Name              struct   buffer_addr_info                                          mpdu_link_desc_addr_info;
38*5113495bSYour Name #else
39*5113495bSYour Name              struct   buffer_addr_info                                          mpdu_link_desc_addr_info;
40*5113495bSYour Name #endif
41*5113495bSYour Name };
42*5113495bSYour Name 
43*5113495bSYour Name 
44*5113495bSYour Name /* Description		MPDU_LINK_DESC_ADDR_INFO
45*5113495bSYour Name 
46*5113495bSYour Name 			Details of the physical address of an MPDU link descriptor
47*5113495bSYour Name 
48*5113495bSYour Name */
49*5113495bSYour Name 
50*5113495bSYour Name 
51*5113495bSYour Name /* Description		BUFFER_ADDR_31_0
52*5113495bSYour Name 
53*5113495bSYour Name 			Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
54*5113495bSYour Name 			 descriptor OR Link Descriptor
55*5113495bSYour Name 
56*5113495bSYour Name 			In case of 'NULL' pointer, this field is set to 0
57*5113495bSYour Name 			<legal all>
58*5113495bSYour Name */
59*5113495bSYour Name 
60*5113495bSYour Name #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET           0x00000000
61*5113495bSYour Name #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB              0
62*5113495bSYour Name #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB              31
63*5113495bSYour Name #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK             0xffffffff
64*5113495bSYour Name 
65*5113495bSYour Name 
66*5113495bSYour Name /* Description		BUFFER_ADDR_39_32
67*5113495bSYour Name 
68*5113495bSYour Name 			Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
69*5113495bSYour Name 			 descriptor OR Link Descriptor
70*5113495bSYour Name 
71*5113495bSYour Name 			In case of 'NULL' pointer, this field is set to 0
72*5113495bSYour Name 			<legal all>
73*5113495bSYour Name */
74*5113495bSYour Name 
75*5113495bSYour Name #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET          0x00000004
76*5113495bSYour Name #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB             0
77*5113495bSYour Name #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB             7
78*5113495bSYour Name #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK            0x000000ff
79*5113495bSYour Name 
80*5113495bSYour Name 
81*5113495bSYour Name /* Description		RETURN_BUFFER_MANAGER
82*5113495bSYour Name 
83*5113495bSYour Name 			Consumer: WBM
84*5113495bSYour Name 			Producer: SW/FW
85*5113495bSYour Name 
86*5113495bSYour Name 			In case of 'NULL' pointer, this field is set to 0
87*5113495bSYour Name 
88*5113495bSYour Name 			Indicates to which buffer manager the buffer OR MSDU_EXTENSION
89*5113495bSYour Name 			 descriptor OR link descriptor that is being pointed to
90*5113495bSYour Name 			shall be returned after the frame has been processed. It
91*5113495bSYour Name 			 is used by WBM for routing purposes.
92*5113495bSYour Name 
93*5113495bSYour Name 			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
94*5113495bSYour Name 			 to the WMB buffer idle list
95*5113495bSYour Name 			<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
96*5113495bSYour Name 			 to the WBM idle link descriptor idle list, where the chip
97*5113495bSYour Name 			 0 WBM is chosen in case of a multi-chip config
98*5113495bSYour Name 			<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
99*5113495bSYour Name 			 to the chip 1 WBM idle link descriptor idle list
100*5113495bSYour Name 			<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
101*5113495bSYour Name 			 to the chip 2 WBM idle link descriptor idle list
102*5113495bSYour Name 			<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
103*5113495bSYour Name 			returned to chip 3 WBM idle link descriptor idle list
104*5113495bSYour Name 			<enum 4 FW_BM> This buffer shall be returned to the FW
105*5113495bSYour Name 			<enum 5 SW0_BM> This buffer shall be returned to the SW,
106*5113495bSYour Name 			ring 0
107*5113495bSYour Name 			<enum 6 SW1_BM> This buffer shall be returned to the SW,
108*5113495bSYour Name 			ring 1
109*5113495bSYour Name 			<enum 7 SW2_BM> This buffer shall be returned to the SW,
110*5113495bSYour Name 			ring 2
111*5113495bSYour Name 			<enum 8 SW3_BM> This buffer shall be returned to the SW,
112*5113495bSYour Name 			ring 3
113*5113495bSYour Name 			<enum 9 SW4_BM> This buffer shall be returned to the SW,
114*5113495bSYour Name 			ring 4
115*5113495bSYour Name 			<enum 10 SW5_BM> This buffer shall be returned to the SW,
116*5113495bSYour Name 			ring 5
117*5113495bSYour Name 			<enum 11 SW6_BM> This buffer shall be returned to the SW,
118*5113495bSYour Name 			ring 6
119*5113495bSYour Name 
120*5113495bSYour Name 			<legal 0-12>
121*5113495bSYour Name */
122*5113495bSYour Name 
123*5113495bSYour Name #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET      0x00000004
124*5113495bSYour Name #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB         8
125*5113495bSYour Name #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB         11
126*5113495bSYour Name #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK        0x00000f00
127*5113495bSYour Name 
128*5113495bSYour Name 
129*5113495bSYour Name /* Description		SW_BUFFER_COOKIE
130*5113495bSYour Name 
131*5113495bSYour Name 			Cookie field exclusively used by SW.
132*5113495bSYour Name 
133*5113495bSYour Name 			In case of 'NULL' pointer, this field is set to 0
134*5113495bSYour Name 
135*5113495bSYour Name 			HW ignores the contents, accept that it passes the programmed
136*5113495bSYour Name 			 value on to other descriptors together with the physical
137*5113495bSYour Name 			 address
138*5113495bSYour Name 
139*5113495bSYour Name 			Field can be used by SW to for example associate the buffers
140*5113495bSYour Name 			 physical address with the virtual address
141*5113495bSYour Name 			The bit definitions as used by SW are within SW HLD specification
142*5113495bSYour Name 
143*5113495bSYour Name 
144*5113495bSYour Name 			NOTE1:
145*5113495bSYour Name 			The three most significant bits can have a special meaning
146*5113495bSYour Name 			 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
147*5113495bSYour Name 			and field transmit_bw_restriction is set
148*5113495bSYour Name 
149*5113495bSYour Name 			In case of NON punctured transmission:
150*5113495bSYour Name 			Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
151*5113495bSYour Name 			Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
152*5113495bSYour Name 			Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
153*5113495bSYour Name 			Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
154*5113495bSYour Name 			Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
155*5113495bSYour Name 			Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
156*5113495bSYour Name 			Sw_buffer_cookie[19:18] = 2'b11: reserved
157*5113495bSYour Name 
158*5113495bSYour Name 			In case of punctured transmission:
159*5113495bSYour Name 			Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
160*5113495bSYour Name 			Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
161*5113495bSYour Name 			Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
162*5113495bSYour Name 			Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
163*5113495bSYour Name 			Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
164*5113495bSYour Name 			Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
165*5113495bSYour Name 			Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
166*5113495bSYour Name 			Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
167*5113495bSYour Name 			Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
168*5113495bSYour Name 			Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
169*5113495bSYour Name 			Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
170*5113495bSYour Name 			Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
171*5113495bSYour Name 			Sw_buffer_cookie[19:18] = 2'b11: reserved
172*5113495bSYour Name 
173*5113495bSYour Name 			Note: a punctured transmission is indicated by the presence
174*5113495bSYour Name 			 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
175*5113495bSYour Name 
176*5113495bSYour Name 			<legal all>
177*5113495bSYour Name */
178*5113495bSYour Name 
179*5113495bSYour Name #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET           0x00000004
180*5113495bSYour Name #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB              12
181*5113495bSYour Name #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB              31
182*5113495bSYour Name #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK             0xfffff000
183*5113495bSYour Name 
184*5113495bSYour Name 
185*5113495bSYour Name 
186*5113495bSYour Name #endif   // RX_MPDU_LINK_PTR
187