1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_MSDU_DESC_INFO_H_ 27 #define _RX_MSDU_DESC_INFO_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1 32 33 34 struct rx_msdu_desc_info { 35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 36 uint32_t first_msdu_in_mpdu_flag : 1, // [0:0] 37 last_msdu_in_mpdu_flag : 1, // [1:1] 38 msdu_continuation : 1, // [2:2] 39 msdu_length : 14, // [16:3] 40 msdu_drop : 1, // [17:17] 41 sa_is_valid : 1, // [18:18] 42 da_is_valid : 1, // [19:19] 43 da_is_mcbc : 1, // [20:20] 44 l3_header_padding_msb : 1, // [21:21] 45 tcp_udp_chksum_fail : 1, // [22:22] 46 ip_chksum_fail : 1, // [23:23] 47 fr_ds : 1, // [24:24] 48 to_ds : 1, // [25:25] 49 intra_bss : 1, // [26:26] 50 dest_chip_id : 2, // [28:27] 51 decap_format : 2, // [30:29] 52 dest_chip_pmac_id : 1; // [31:31] 53 #else 54 uint32_t dest_chip_pmac_id : 1, // [31:31] 55 decap_format : 2, // [30:29] 56 dest_chip_id : 2, // [28:27] 57 intra_bss : 1, // [26:26] 58 to_ds : 1, // [25:25] 59 fr_ds : 1, // [24:24] 60 ip_chksum_fail : 1, // [23:23] 61 tcp_udp_chksum_fail : 1, // [22:22] 62 l3_header_padding_msb : 1, // [21:21] 63 da_is_mcbc : 1, // [20:20] 64 da_is_valid : 1, // [19:19] 65 sa_is_valid : 1, // [18:18] 66 msdu_drop : 1, // [17:17] 67 msdu_length : 14, // [16:3] 68 msdu_continuation : 1, // [2:2] 69 last_msdu_in_mpdu_flag : 1, // [1:1] 70 first_msdu_in_mpdu_flag : 1; // [0:0] 71 #endif 72 }; 73 74 75 /* Description FIRST_MSDU_IN_MPDU_FLAG 76 77 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 78 multiple buffers, this field will be valid in the Last 79 buffer used by the MSDU 80 81 <enum 0 Not_first_msdu> This is not the first MSDU in the 82 MPDU. 83 <enum 1 first_msdu> This MSDU is the first one in the MPDU. 84 85 86 <legal all> 87 */ 88 89 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 90 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 91 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 92 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 93 94 95 /* Description LAST_MSDU_IN_MPDU_FLAG 96 97 Consumer: WBM/REO/SW/FW 98 Producer: RXDMA 99 100 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 101 multiple buffers, this field will be valid in the Last 102 buffer used by the MSDU 103 104 <enum 0 Not_last_msdu> There are more MSDUs linked to this 105 MSDU that belongs to this MPDU 106 <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 107 This setting is only allowed in combination with 'Msdu_continuation' 108 set to 0. This implies that when an msdu is spread out over 109 multiple buffers and thus msdu_continuation is set, only 110 for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 111 be set. 112 113 When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 114 are set, the MPDU that this MSDU belongs to only contains 115 a single MSDU. 116 117 118 <legal all> 119 */ 120 121 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 122 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 123 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB 1 124 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 125 126 127 /* Description MSDU_CONTINUATION 128 129 When set, this MSDU buffer was not able to hold the entire 130 MSDU. The next buffer will therefor contain additional 131 information related to this MSDU. 132 133 <legal all> 134 */ 135 136 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET 0x00000000 137 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB 2 138 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB 2 139 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK 0x00000004 140 141 142 /* Description MSDU_LENGTH 143 144 Parsed from RX_MSDU_START TLV . In the case MSDU spans over 145 multiple buffers, this field will be valid in the First 146 buffer used by MSDU. 147 148 Full MSDU length in bytes after decapsulation. 149 150 This field is still valid for MPDU frames without A-MSDU. 151 It still represents MSDU length after decapsulation 152 153 Or in case of RAW MPDUs, it indicates the length of the 154 entire MPDU (without FCS field) 155 <legal all> 156 */ 157 158 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x00000000 159 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 160 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB 16 161 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 162 163 164 /* Description MSDU_DROP 165 166 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 167 multiple buffers, this field will be valid in the Last 168 buffer used by the MSDU 169 170 When set, REO shall drop this MSDU and not forward it to 171 any other ring... 172 <legal all> 173 */ 174 175 #define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET 0x00000000 176 #define RX_MSDU_DESC_INFO_MSDU_DROP_LSB 17 177 #define RX_MSDU_DESC_INFO_MSDU_DROP_MSB 17 178 #define RX_MSDU_DESC_INFO_MSDU_DROP_MASK 0x00020000 179 180 181 /* Description SA_IS_VALID 182 183 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 184 multiple buffers, this field will be valid in the Last 185 buffer used by the MSDU 186 187 Indicates that OLE found a valid SA entry for this MSDU 188 <legal all> 189 */ 190 191 #define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET 0x00000000 192 #define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB 18 193 #define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB 18 194 #define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK 0x00040000 195 196 197 /* Description DA_IS_VALID 198 199 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 200 multiple buffers, this field will be valid in the Last 201 buffer used by the MSDU 202 203 Indicates that OLE found a valid DA entry for this MSDU 204 <legal all> 205 */ 206 207 #define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET 0x00000000 208 #define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB 19 209 #define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB 19 210 #define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK 0x00080000 211 212 213 /* Description DA_IS_MCBC 214 215 Field Only valid if "da_is_valid" is set 216 217 Indicates the DA address was a Multicast of Broadcast address 218 for this MSDU 219 <legal all> 220 */ 221 222 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET 0x00000000 223 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB 20 224 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB 20 225 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK 0x00100000 226 227 228 /* Description L3_HEADER_PADDING_MSB 229 230 Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 231 as the LSB is always zero) 232 Number of bytes padded to make sure that the L3 header will 233 always start of a Dword boundary 234 <legal all> 235 */ 236 237 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 238 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB 21 239 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB 21 240 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK 0x00200000 241 242 243 /* Description TCP_UDP_CHKSUM_FAIL 244 245 Passed on from 'RX_ATTENTION' TLV 246 Indicates that the computed checksum did not match the checksum 247 in the TCP/UDP header. 248 <legal all> 249 */ 250 251 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 252 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB 22 253 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB 22 254 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 255 256 257 /* Description IP_CHKSUM_FAIL 258 259 Passed on from 'RX_ATTENTION' TLV 260 Indicates that the computed checksum did not match the checksum 261 in the IP header. 262 <legal all> 263 */ 264 265 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET 0x00000000 266 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB 23 267 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB 23 268 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK 0x00800000 269 270 271 /* Description FR_DS 272 273 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 274 TLV 275 Set if the 'from DS' bit is set in the frame control. 276 <legal all> 277 */ 278 279 #define RX_MSDU_DESC_INFO_FR_DS_OFFSET 0x00000000 280 #define RX_MSDU_DESC_INFO_FR_DS_LSB 24 281 #define RX_MSDU_DESC_INFO_FR_DS_MSB 24 282 #define RX_MSDU_DESC_INFO_FR_DS_MASK 0x01000000 283 284 285 /* Description TO_DS 286 287 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 288 TLV 289 Set if the 'to DS' bit is set in the frame control. 290 <legal all> 291 */ 292 293 #define RX_MSDU_DESC_INFO_TO_DS_OFFSET 0x00000000 294 #define RX_MSDU_DESC_INFO_TO_DS_LSB 25 295 #define RX_MSDU_DESC_INFO_TO_DS_MSB 25 296 #define RX_MSDU_DESC_INFO_TO_DS_MASK 0x02000000 297 298 299 /* Description INTRA_BSS 300 301 This packet needs intra-BSS routing by SW as the 'vdev_id' 302 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 303 that this MSDU was got in. 304 305 <legal all> 306 */ 307 308 #define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET 0x00000000 309 #define RX_MSDU_DESC_INFO_INTRA_BSS_LSB 26 310 #define RX_MSDU_DESC_INFO_INTRA_BSS_MSB 26 311 #define RX_MSDU_DESC_INFO_INTRA_BSS_MASK 0x04000000 312 313 314 /* Description DEST_CHIP_ID 315 316 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 317 to support intra-BSS routing with multi-chip multi-link 318 operation. 319 320 This indicates into which chip's TCL the packet should be 321 queued. 322 323 <legal all> 324 */ 325 326 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET 0x00000000 327 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB 27 328 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB 28 329 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK 0x18000000 330 331 332 /* Description DECAP_FORMAT 333 334 Indicates the format after decapsulation: 335 336 <enum 0 RAW> No encapsulation 337 <enum 1 Native_WiFi> 338 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 339 340 <enum 3 802_3> Indicate Ethernet 341 342 <legal all> 343 */ 344 345 #define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET 0x00000000 346 #define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB 29 347 #define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB 30 348 #define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK 0x60000000 349 350 351 /* Description DEST_CHIP_PMAC_ID 352 353 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 354 to support intra-BSS routing with multi-chip multi-link 355 operation. 356 357 This indicates into which link/'vdev' the packet should 358 be queued in TCL. 359 360 <legal all> 361 */ 362 363 #define RX_MSDU_DESC_INFO_DEST_CHIP_PMAC_ID_OFFSET 0x00000000 364 #define RX_MSDU_DESC_INFO_DEST_CHIP_PMAC_ID_LSB 31 365 #define RX_MSDU_DESC_INFO_DEST_CHIP_PMAC_ID_MSB 31 366 #define RX_MSDU_DESC_INFO_DEST_CHIP_PMAC_ID_MASK 0x80000000 367 368 369 370 #endif // RX_MSDU_DESC_INFO 371