1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_MSDU_DETAILS_H_ 27 #define _RX_MSDU_DETAILS_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "rx_msdu_desc_info.h" 32 #include "rx_msdu_ext_desc_info.h" 33 #include "buffer_addr_info.h" 34 #define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 35 36 37 struct rx_msdu_details { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct buffer_addr_info buffer_addr_info_details; 40 struct rx_msdu_desc_info rx_msdu_desc_info_details; 41 struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; 42 #else 43 struct buffer_addr_info buffer_addr_info_details; 44 struct rx_msdu_desc_info rx_msdu_desc_info_details; 45 struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; 46 #endif 47 }; 48 49 50 /* Description BUFFER_ADDR_INFO_DETAILS 51 52 Consumer: REO/SW 53 Producer: RXDMA 54 55 Details of the physical address of the buffer containing 56 an MSDU (or entire MPDU) 57 */ 58 59 60 /* Description BUFFER_ADDR_31_0 61 62 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 63 descriptor OR Link Descriptor 64 65 In case of 'NULL' pointer, this field is set to 0 66 <legal all> 67 */ 68 69 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 70 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 71 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 72 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 73 74 75 /* Description BUFFER_ADDR_39_32 76 77 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 78 descriptor OR Link Descriptor 79 80 In case of 'NULL' pointer, this field is set to 0 81 <legal all> 82 */ 83 84 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 85 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 86 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 87 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 88 89 90 /* Description RETURN_BUFFER_MANAGER 91 92 Consumer: WBM 93 Producer: SW/FW 94 95 In case of 'NULL' pointer, this field is set to 0 96 97 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 98 descriptor OR link descriptor that is being pointed to 99 shall be returned after the frame has been processed. It 100 is used by WBM for routing purposes. 101 102 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 103 to the WMB buffer idle list 104 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 105 to the WBM idle link descriptor idle list, where the chip 106 0 WBM is chosen in case of a multi-chip config 107 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 108 to the chip 1 WBM idle link descriptor idle list 109 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 110 to the chip 2 WBM idle link descriptor idle list 111 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 112 returned to chip 3 WBM idle link descriptor idle list 113 <enum 4 FW_BM> This buffer shall be returned to the FW 114 <enum 5 SW0_BM> This buffer shall be returned to the SW, 115 ring 0 116 <enum 6 SW1_BM> This buffer shall be returned to the SW, 117 ring 1 118 <enum 7 SW2_BM> This buffer shall be returned to the SW, 119 ring 2 120 <enum 8 SW3_BM> This buffer shall be returned to the SW, 121 ring 3 122 <enum 9 SW4_BM> This buffer shall be returned to the SW, 123 ring 4 124 <enum 10 SW5_BM> This buffer shall be returned to the SW, 125 ring 5 126 <enum 11 SW6_BM> This buffer shall be returned to the SW, 127 ring 6 128 129 <legal 0-12> 130 */ 131 132 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 133 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 134 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 135 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 136 137 138 /* Description SW_BUFFER_COOKIE 139 140 Cookie field exclusively used by SW. 141 142 In case of 'NULL' pointer, this field is set to 0 143 144 HW ignores the contents, accept that it passes the programmed 145 value on to other descriptors together with the physical 146 address 147 148 Field can be used by SW to for example associate the buffers 149 physical address with the virtual address 150 The bit definitions as used by SW are within SW HLD specification 151 152 153 NOTE1: 154 The three most significant bits can have a special meaning 155 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 156 and field transmit_bw_restriction is set 157 158 In case of NON punctured transmission: 159 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 160 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 161 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 162 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 163 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 164 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 165 Sw_buffer_cookie[19:18] = 2'b11: reserved 166 167 In case of punctured transmission: 168 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 169 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 170 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 171 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 172 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 173 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 174 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 175 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 176 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 177 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 178 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 179 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 180 Sw_buffer_cookie[19:18] = 2'b11: reserved 181 182 Note: a punctured transmission is indicated by the presence 183 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 184 185 <legal all> 186 */ 187 188 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 189 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 190 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 191 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 192 193 194 /* Description RX_MSDU_DESC_INFO_DETAILS 195 196 Consumer: REO/SW 197 Producer: RXDMA 198 199 General information related to the MSDU that should be passed 200 on from RXDMA all the way to to the REO destination ring. 201 202 */ 203 204 205 /* Description FIRST_MSDU_IN_MPDU_FLAG 206 207 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 208 multiple buffers, this field will be valid in the Last 209 buffer used by the MSDU 210 211 <enum 0 Not_first_msdu> This is not the first MSDU in the 212 MPDU. 213 <enum 1 first_msdu> This MSDU is the first one in the MPDU. 214 215 216 <legal all> 217 */ 218 219 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 220 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 221 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 222 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 223 224 225 /* Description LAST_MSDU_IN_MPDU_FLAG 226 227 Consumer: WBM/REO/SW/FW 228 Producer: RXDMA 229 230 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 231 multiple buffers, this field will be valid in the Last 232 buffer used by the MSDU 233 234 <enum 0 Not_last_msdu> There are more MSDUs linked to this 235 MSDU that belongs to this MPDU 236 <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 237 This setting is only allowed in combination with 'Msdu_continuation' 238 set to 0. This implies that when an msdu is spread out over 239 multiple buffers and thus msdu_continuation is set, only 240 for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 241 be set. 242 243 When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 244 are set, the MPDU that this MSDU belongs to only contains 245 a single MSDU. 246 247 248 <legal all> 249 */ 250 251 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 252 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 253 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 254 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 255 256 257 /* Description MSDU_CONTINUATION 258 259 When set, this MSDU buffer was not able to hold the entire 260 MSDU. The next buffer will therefor contain additional 261 information related to this MSDU. 262 263 <legal all> 264 */ 265 266 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 267 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 268 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 269 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 270 271 272 /* Description MSDU_LENGTH 273 274 Parsed from RX_MSDU_START TLV . In the case MSDU spans over 275 multiple buffers, this field will be valid in the First 276 buffer used by MSDU. 277 278 Full MSDU length in bytes after decapsulation. 279 280 This field is still valid for MPDU frames without A-MSDU. 281 It still represents MSDU length after decapsulation 282 283 Or in case of RAW MPDUs, it indicates the length of the 284 entire MPDU (without FCS field) 285 <legal all> 286 */ 287 288 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 289 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 290 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 291 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 292 293 294 /* Description MSDU_DROP 295 296 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 297 multiple buffers, this field will be valid in the Last 298 buffer used by the MSDU 299 300 When set, REO shall drop this MSDU and not forward it to 301 any other ring... 302 <legal all> 303 */ 304 305 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 306 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 307 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 308 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 309 310 311 /* Description SA_IS_VALID 312 313 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 314 multiple buffers, this field will be valid in the Last 315 buffer used by the MSDU 316 317 Indicates that OLE found a valid SA entry for this MSDU 318 <legal all> 319 */ 320 321 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 322 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 323 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 324 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 325 326 327 /* Description DA_IS_VALID 328 329 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 330 multiple buffers, this field will be valid in the Last 331 buffer used by the MSDU 332 333 Indicates that OLE found a valid DA entry for this MSDU 334 <legal all> 335 */ 336 337 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 338 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 339 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 340 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 341 342 343 /* Description DA_IS_MCBC 344 345 Field Only valid if "da_is_valid" is set 346 347 Indicates the DA address was a Multicast of Broadcast address 348 for this MSDU 349 <legal all> 350 */ 351 352 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 353 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 354 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 355 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 356 357 358 /* Description L3_HEADER_PADDING_MSB 359 360 Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 361 as the LSB is always zero) 362 Number of bytes padded to make sure that the L3 header will 363 always start of a Dword boundary 364 <legal all> 365 */ 366 367 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008 368 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 369 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 370 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 371 372 373 /* Description TCP_UDP_CHKSUM_FAIL 374 375 Passed on from 'RX_ATTENTION' TLV 376 Indicates that the computed checksum did not match the checksum 377 in the TCP/UDP header. 378 <legal all> 379 */ 380 381 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008 382 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 383 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 384 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 385 386 387 /* Description IP_CHKSUM_FAIL 388 389 Passed on from 'RX_ATTENTION' TLV 390 Indicates that the computed checksum did not match the checksum 391 in the IP header. 392 <legal all> 393 */ 394 395 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008 396 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 397 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 398 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 399 400 401 /* Description FR_DS 402 403 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 404 TLV 405 Set if the 'from DS' bit is set in the frame control. 406 <legal all> 407 */ 408 409 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000008 410 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 411 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 412 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 413 414 415 /* Description TO_DS 416 417 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 418 TLV 419 Set if the 'to DS' bit is set in the frame control. 420 <legal all> 421 */ 422 423 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000008 424 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 425 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 426 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 427 428 429 /* Description INTRA_BSS 430 431 This packet needs intra-BSS routing by SW as the 'vdev_id' 432 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 433 that this MSDU was got in. 434 435 <legal all> 436 */ 437 438 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000008 439 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 440 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 441 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 442 443 444 /* Description DEST_CHIP_ID 445 446 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 447 to support intra-BSS routing with multi-chip multi-link 448 operation. 449 450 This indicates into which chip's TCL the packet should be 451 queued. 452 453 <legal all> 454 */ 455 456 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000008 457 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 458 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 459 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 460 461 462 /* Description DECAP_FORMAT 463 464 Indicates the format after decapsulation: 465 466 <enum 0 RAW> No encapsulation 467 <enum 1 Native_WiFi> 468 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 469 470 <enum 3 802_3> Indicate Ethernet 471 472 <legal all> 473 */ 474 475 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000008 476 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 477 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 478 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 479 480 481 /* Description DEST_CHIP_PMAC_ID 482 483 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 484 to support intra-BSS routing with multi-chip multi-link 485 operation. 486 487 This indicates into which link/'vdev' the packet should 488 be queued in TCL. 489 490 <legal all> 491 */ 492 493 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000008 494 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 495 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 496 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 497 498 499 /* Description RX_MSDU_EXT_DESC_INFO_DETAILS 500 501 Consumer: REO/SW 502 Producer: RXDMA 503 504 Extended information related to the MSDU that is passed 505 on from RXDMA to REO but not part of the REO destination 506 ring. Some fields are passed on to PPE. 507 */ 508 509 510 /* Description REO_DESTINATION_INDICATION 511 512 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 513 multiple buffers, this field will be valid in the Last 514 buffer used by the MSDU 515 516 The ID of the REO exit ring where the MSDU frame shall push 517 after (MPDU level) reordering has finished. 518 519 <enum 0 reo_destination_sw0> Reo will push the frame into 520 the REO2SW0 ring 521 <enum 1 reo_destination_sw1> Reo will push the frame into 522 the REO2SW1 ring 523 <enum 2 reo_destination_sw2> Reo will push the frame into 524 the REO2SW2 ring 525 <enum 3 reo_destination_sw3> Reo will push the frame into 526 the REO2SW3 ring 527 <enum 4 reo_destination_sw4> Reo will push the frame into 528 the REO2SW4 ring 529 <enum 5 reo_destination_release> Reo will push the frame 530 into the REO_release ring 531 <enum 6 reo_destination_fw> Reo will push the frame into 532 the REO2FW ring 533 <enum 7 reo_destination_sw5> Reo will push the frame into 534 the REO2SW5 ring (REO remaps this in chips without REO2SW5 535 ring, e.g. Pine) 536 <enum 8 reo_destination_sw6> Reo will push the frame into 537 the REO2SW6 ring (REO remaps this in chips without REO2SW6 538 ring, e.g. Pine) 539 <enum 9 reo_destination_sw7> Reo will push the frame into 540 the REO2SW7 ring (REO remaps this in chips without REO2SW7 541 ring) 542 <enum 10 reo_destination_sw8> Reo will push the frame into 543 the REO2SW8 ring (REO remaps this in chips without REO2SW8 544 ring) 545 <enum 11 reo_destination_11> REO remaps this 546 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 547 REO remaps this 548 <enum 14 reo_destination_14> REO remaps this 549 <enum 15 reo_destination_15> REO remaps this 550 <enum 16 reo_destination_16> REO remaps this 551 <enum 17 reo_destination_17> REO remaps this 552 <enum 18 reo_destination_18> REO remaps this 553 <enum 19 reo_destination_19> REO remaps this 554 <enum 20 reo_destination_20> REO remaps this 555 <enum 21 reo_destination_21> REO remaps this 556 <enum 22 reo_destination_22> REO remaps this 557 <enum 23 reo_destination_23> REO remaps this 558 <enum 24 reo_destination_24> REO remaps this 559 <enum 25 reo_destination_25> REO remaps this 560 <enum 26 reo_destination_26> REO remaps this 561 <enum 27 reo_destination_27> REO remaps this 562 <enum 28 reo_destination_28> REO remaps this 563 <enum 29 reo_destination_29> REO remaps this 564 <enum 30 reo_destination_30> REO remaps this 565 <enum 31 reo_destination_31> REO remaps this 566 567 <legal all> 568 */ 569 570 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c 571 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 572 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 573 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 574 575 576 /* Description SERVICE_CODE 577 578 Opaque service code between PPE and Wi-Fi 579 580 This field gets passed on by REO to PPE in the EDMA descriptor 581 ('REO_TO_PPE_RING'). 582 583 <legal all> 584 */ 585 586 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000c 587 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 588 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 589 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 590 591 592 /* Description PRIORITY_VALID 593 594 This field gets passed on by REO to PPE in the EDMA descriptor 595 ('REO_TO_PPE_RING'). 596 597 <legal all> 598 */ 599 600 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000c 601 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 602 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 603 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 604 605 606 /* Description DATA_OFFSET 607 608 The offset to Rx packet data within the buffer (including 609 Rx DMA offset programming and L3 header padding inserted 610 by Rx OLE). 611 612 This field gets passed on by REO to PPE in the EDMA descriptor 613 ('REO_TO_PPE_RING'). 614 615 <legal all> 616 */ 617 618 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000000c 619 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 620 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 621 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 622 623 624 /* Description SRC_LINK_ID 625 626 Consumer: SW 627 Producer: RXDMA 628 629 Set to the link ID of the PMAC that received the frame 630 <legal all> 631 */ 632 633 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000000c 634 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 635 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 636 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 637 638 639 /* Description RESERVED_0A 640 641 <legal 0> 642 */ 643 644 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000c 645 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 646 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 647 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 648 649 650 651 #endif // RX_MSDU_DETAILS 652