1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_MSDU_END_H_ 27 #define _RX_MSDU_END_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_RX_MSDU_END 32 32 33 #define NUM_OF_QWORDS_RX_MSDU_END 16 34 35 36 struct rx_msdu_end { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] 39 sw_frame_group_id : 7, // [8:2] 40 reserved_0 : 7, // [15:9] 41 phy_ppdu_id : 16; // [31:16] 42 uint32_t ip_hdr_chksum : 16, // [15:0] 43 reported_mpdu_length : 14, // [29:16] 44 reserved_1a : 2; // [31:30] 45 uint32_t reserved_2a : 8, // [7:0] 46 cce_super_rule : 6, // [13:8] 47 cce_classify_not_done_truncate : 1, // [14:14] 48 cce_classify_not_done_cce_dis : 1, // [15:15] 49 cumulative_l3_checksum : 16; // [31:16] 50 uint32_t rule_indication_31_0 : 32; // [31:0] 51 uint32_t ipv6_options_crc : 32; // [31:0] 52 uint32_t da_offset : 6, // [5:0] 53 sa_offset : 6, // [11:6] 54 da_offset_valid : 1, // [12:12] 55 sa_offset_valid : 1, // [13:13] 56 reserved_5a : 2, // [15:14] 57 l3_type : 16; // [31:16] 58 uint32_t rule_indication_63_32 : 32; // [31:0] 59 uint32_t tcp_seq_number : 32; // [31:0] 60 uint32_t tcp_ack_number : 32; // [31:0] 61 uint32_t tcp_flag : 9, // [8:0] 62 lro_eligible : 1, // [9:9] 63 reserved_9a : 6, // [15:10] 64 window_size : 16; // [31:16] 65 uint32_t sa_sw_peer_id : 16, // [15:0] 66 sa_idx_timeout : 1, // [16:16] 67 da_idx_timeout : 1, // [17:17] 68 to_ds : 1, // [18:18] 69 tid : 4, // [22:19] 70 sa_is_valid : 1, // [23:23] 71 da_is_valid : 1, // [24:24] 72 da_is_mcbc : 1, // [25:25] 73 l3_header_padding : 2, // [27:26] 74 first_msdu : 1, // [28:28] 75 last_msdu : 1, // [29:29] 76 fr_ds : 1, // [30:30] 77 ip_chksum_fail_copy : 1; // [31:31] 78 uint32_t sa_idx : 16, // [15:0] 79 da_idx_or_sw_peer_id : 16; // [31:16] 80 uint32_t msdu_drop : 1, // [0:0] 81 reo_destination_indication : 5, // [5:1] 82 flow_idx : 20, // [25:6] 83 use_ppe : 1, // [26:26] 84 mesh_sta : 2, // [28:27] 85 vlan_ctag_stripped : 1, // [29:29] 86 vlan_stag_stripped : 1, // [30:30] 87 fragment_flag : 1; // [31:31] 88 uint32_t fse_metadata : 32; // [31:0] 89 uint32_t cce_metadata : 16, // [15:0] 90 tcp_udp_chksum : 16; // [31:16] 91 uint32_t aggregation_count : 8, // [7:0] 92 flow_aggregation_continuation : 1, // [8:8] 93 fisa_timeout : 1, // [9:9] 94 tcp_udp_chksum_fail_copy : 1, // [10:10] 95 msdu_limit_error : 1, // [11:11] 96 flow_idx_timeout : 1, // [12:12] 97 flow_idx_invalid : 1, // [13:13] 98 cce_match : 1, // [14:14] 99 amsdu_parser_error : 1, // [15:15] 100 cumulative_ip_length : 16; // [31:16] 101 uint32_t key_id_octet : 8, // [7:0] 102 reserved_16a : 24; // [31:8] 103 uint32_t reserved_17a : 6, // [5:0] 104 service_code : 9, // [14:6] 105 priority_valid : 1, // [15:15] 106 intra_bss : 1, // [16:16] 107 dest_chip_id : 2, // [18:17] 108 multicast_echo : 1, // [19:19] 109 wds_learning_event : 1, // [20:20] 110 wds_roaming_event : 1, // [21:21] 111 wds_keep_alive_event : 1, // [22:22] 112 dest_chip_pmac_id : 1, // [23:23] 113 reserved_17b : 8; // [31:24] 114 uint32_t msdu_length : 14, // [13:0] 115 stbc : 1, // [14:14] 116 ipsec_esp : 1, // [15:15] 117 l3_offset : 7, // [22:16] 118 ipsec_ah : 1, // [23:23] 119 l4_offset : 8; // [31:24] 120 uint32_t msdu_number : 8, // [7:0] 121 decap_format : 2, // [9:8] 122 ipv4_proto : 1, // [10:10] 123 ipv6_proto : 1, // [11:11] 124 tcp_proto : 1, // [12:12] 125 udp_proto : 1, // [13:13] 126 ip_frag : 1, // [14:14] 127 tcp_only_ack : 1, // [15:15] 128 da_is_bcast_mcast : 1, // [16:16] 129 toeplitz_hash_sel : 2, // [18:17] 130 ip_fixed_header_valid : 1, // [19:19] 131 ip_extn_header_valid : 1, // [20:20] 132 tcp_udp_header_valid : 1, // [21:21] 133 mesh_control_present : 1, // [22:22] 134 ldpc : 1, // [23:23] 135 ip4_protocol_ip6_next_header : 8; // [31:24] 136 uint32_t vlan_ctag_ci : 16, // [15:0] 137 vlan_stag_ci : 16; // [31:16] 138 uint32_t peer_meta_data : 32; // [31:0] 139 uint32_t user_rssi : 8, // [7:0] 140 pkt_type : 4, // [11:8] 141 sgi : 2, // [13:12] 142 rate_mcs : 4, // [17:14] 143 receive_bandwidth : 3, // [20:18] 144 reception_type : 3, // [23:21] 145 mimo_ss_bitmap : 7, // [30:24] 146 msdu_done_copy : 1; // [31:31] 147 uint32_t flow_id_toeplitz : 32; // [31:0] 148 uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] 149 uint32_t sw_phy_meta_data : 32; // [31:0] 150 uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] 151 uint32_t toeplitz_hash_2_or_4 : 32; // [31:0] 152 uint32_t reserved_28a : 16, // [15:0] 153 sa_15_0 : 16; // [31:16] 154 uint32_t sa_47_16 : 32; // [31:0] 155 uint32_t first_mpdu : 1, // [0:0] 156 reserved_30a : 1, // [1:1] 157 mcast_bcast : 1, // [2:2] 158 ast_index_not_found : 1, // [3:3] 159 ast_index_timeout : 1, // [4:4] 160 power_mgmt : 1, // [5:5] 161 non_qos : 1, // [6:6] 162 null_data : 1, // [7:7] 163 mgmt_type : 1, // [8:8] 164 ctrl_type : 1, // [9:9] 165 more_data : 1, // [10:10] 166 eosp : 1, // [11:11] 167 a_msdu_error : 1, // [12:12] 168 reserved_30b : 1, // [13:13] 169 order : 1, // [14:14] 170 wifi_parser_error : 1, // [15:15] 171 overflow_err : 1, // [16:16] 172 msdu_length_err : 1, // [17:17] 173 tcp_udp_chksum_fail : 1, // [18:18] 174 ip_chksum_fail : 1, // [19:19] 175 sa_idx_invalid : 1, // [20:20] 176 da_idx_invalid : 1, // [21:21] 177 amsdu_addr_mismatch : 1, // [22:22] 178 rx_in_tx_decrypt_byp : 1, // [23:23] 179 encrypt_required : 1, // [24:24] 180 directed : 1, // [25:25] 181 buffer_fragment : 1, // [26:26] 182 mpdu_length_err : 1, // [27:27] 183 tkip_mic_err : 1, // [28:28] 184 decrypt_err : 1, // [29:29] 185 unencrypted_frame_err : 1, // [30:30] 186 fcs_err : 1; // [31:31] 187 uint32_t reserved_31a : 10, // [9:0] 188 decrypt_status_code : 3, // [12:10] 189 rx_bitmap_not_updated : 1, // [13:13] 190 reserved_31b : 17, // [30:14] 191 msdu_done : 1; // [31:31] 192 #else 193 uint32_t phy_ppdu_id : 16, // [31:16] 194 reserved_0 : 7, // [15:9] 195 sw_frame_group_id : 7, // [8:2] 196 rxpcu_mpdu_filter_in_category : 2; // [1:0] 197 uint32_t reserved_1a : 2, // [31:30] 198 reported_mpdu_length : 14, // [29:16] 199 ip_hdr_chksum : 16; // [15:0] 200 uint32_t cumulative_l3_checksum : 16, // [31:16] 201 cce_classify_not_done_cce_dis : 1, // [15:15] 202 cce_classify_not_done_truncate : 1, // [14:14] 203 cce_super_rule : 6, // [13:8] 204 reserved_2a : 8; // [7:0] 205 uint32_t rule_indication_31_0 : 32; // [31:0] 206 uint32_t ipv6_options_crc : 32; // [31:0] 207 uint32_t l3_type : 16, // [31:16] 208 reserved_5a : 2, // [15:14] 209 sa_offset_valid : 1, // [13:13] 210 da_offset_valid : 1, // [12:12] 211 sa_offset : 6, // [11:6] 212 da_offset : 6; // [5:0] 213 uint32_t rule_indication_63_32 : 32; // [31:0] 214 uint32_t tcp_seq_number : 32; // [31:0] 215 uint32_t tcp_ack_number : 32; // [31:0] 216 uint32_t window_size : 16, // [31:16] 217 reserved_9a : 6, // [15:10] 218 lro_eligible : 1, // [9:9] 219 tcp_flag : 9; // [8:0] 220 uint32_t ip_chksum_fail_copy : 1, // [31:31] 221 fr_ds : 1, // [30:30] 222 last_msdu : 1, // [29:29] 223 first_msdu : 1, // [28:28] 224 l3_header_padding : 2, // [27:26] 225 da_is_mcbc : 1, // [25:25] 226 da_is_valid : 1, // [24:24] 227 sa_is_valid : 1, // [23:23] 228 tid : 4, // [22:19] 229 to_ds : 1, // [18:18] 230 da_idx_timeout : 1, // [17:17] 231 sa_idx_timeout : 1, // [16:16] 232 sa_sw_peer_id : 16; // [15:0] 233 uint32_t da_idx_or_sw_peer_id : 16, // [31:16] 234 sa_idx : 16; // [15:0] 235 uint32_t fragment_flag : 1, // [31:31] 236 vlan_stag_stripped : 1, // [30:30] 237 vlan_ctag_stripped : 1, // [29:29] 238 mesh_sta : 2, // [28:27] 239 use_ppe : 1, // [26:26] 240 flow_idx : 20, // [25:6] 241 reo_destination_indication : 5, // [5:1] 242 msdu_drop : 1; // [0:0] 243 uint32_t fse_metadata : 32; // [31:0] 244 uint32_t tcp_udp_chksum : 16, // [31:16] 245 cce_metadata : 16; // [15:0] 246 uint32_t cumulative_ip_length : 16, // [31:16] 247 amsdu_parser_error : 1, // [15:15] 248 cce_match : 1, // [14:14] 249 flow_idx_invalid : 1, // [13:13] 250 flow_idx_timeout : 1, // [12:12] 251 msdu_limit_error : 1, // [11:11] 252 tcp_udp_chksum_fail_copy : 1, // [10:10] 253 fisa_timeout : 1, // [9:9] 254 flow_aggregation_continuation : 1, // [8:8] 255 aggregation_count : 8; // [7:0] 256 uint32_t reserved_16a : 24, // [31:8] 257 key_id_octet : 8; // [7:0] 258 uint32_t reserved_17b : 8, // [31:24] 259 dest_chip_pmac_id : 1, // [23:23] 260 wds_keep_alive_event : 1, // [22:22] 261 wds_roaming_event : 1, // [21:21] 262 wds_learning_event : 1, // [20:20] 263 multicast_echo : 1, // [19:19] 264 dest_chip_id : 2, // [18:17] 265 intra_bss : 1, // [16:16] 266 priority_valid : 1, // [15:15] 267 service_code : 9, // [14:6] 268 reserved_17a : 6; // [5:0] 269 uint32_t l4_offset : 8, // [31:24] 270 ipsec_ah : 1, // [23:23] 271 l3_offset : 7, // [22:16] 272 ipsec_esp : 1, // [15:15] 273 stbc : 1, // [14:14] 274 msdu_length : 14; // [13:0] 275 uint32_t ip4_protocol_ip6_next_header : 8, // [31:24] 276 ldpc : 1, // [23:23] 277 mesh_control_present : 1, // [22:22] 278 tcp_udp_header_valid : 1, // [21:21] 279 ip_extn_header_valid : 1, // [20:20] 280 ip_fixed_header_valid : 1, // [19:19] 281 toeplitz_hash_sel : 2, // [18:17] 282 da_is_bcast_mcast : 1, // [16:16] 283 tcp_only_ack : 1, // [15:15] 284 ip_frag : 1, // [14:14] 285 udp_proto : 1, // [13:13] 286 tcp_proto : 1, // [12:12] 287 ipv6_proto : 1, // [11:11] 288 ipv4_proto : 1, // [10:10] 289 decap_format : 2, // [9:8] 290 msdu_number : 8; // [7:0] 291 uint32_t vlan_stag_ci : 16, // [31:16] 292 vlan_ctag_ci : 16; // [15:0] 293 uint32_t peer_meta_data : 32; // [31:0] 294 uint32_t msdu_done_copy : 1, // [31:31] 295 mimo_ss_bitmap : 7, // [30:24] 296 reception_type : 3, // [23:21] 297 receive_bandwidth : 3, // [20:18] 298 rate_mcs : 4, // [17:14] 299 sgi : 2, // [13:12] 300 pkt_type : 4, // [11:8] 301 user_rssi : 8; // [7:0] 302 uint32_t flow_id_toeplitz : 32; // [31:0] 303 uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] 304 uint32_t sw_phy_meta_data : 32; // [31:0] 305 uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] 306 uint32_t toeplitz_hash_2_or_4 : 32; // [31:0] 307 uint32_t sa_15_0 : 16, // [31:16] 308 reserved_28a : 16; // [15:0] 309 uint32_t sa_47_16 : 32; // [31:0] 310 uint32_t fcs_err : 1, // [31:31] 311 unencrypted_frame_err : 1, // [30:30] 312 decrypt_err : 1, // [29:29] 313 tkip_mic_err : 1, // [28:28] 314 mpdu_length_err : 1, // [27:27] 315 buffer_fragment : 1, // [26:26] 316 directed : 1, // [25:25] 317 encrypt_required : 1, // [24:24] 318 rx_in_tx_decrypt_byp : 1, // [23:23] 319 amsdu_addr_mismatch : 1, // [22:22] 320 da_idx_invalid : 1, // [21:21] 321 sa_idx_invalid : 1, // [20:20] 322 ip_chksum_fail : 1, // [19:19] 323 tcp_udp_chksum_fail : 1, // [18:18] 324 msdu_length_err : 1, // [17:17] 325 overflow_err : 1, // [16:16] 326 wifi_parser_error : 1, // [15:15] 327 order : 1, // [14:14] 328 reserved_30b : 1, // [13:13] 329 a_msdu_error : 1, // [12:12] 330 eosp : 1, // [11:11] 331 more_data : 1, // [10:10] 332 ctrl_type : 1, // [9:9] 333 mgmt_type : 1, // [8:8] 334 null_data : 1, // [7:7] 335 non_qos : 1, // [6:6] 336 power_mgmt : 1, // [5:5] 337 ast_index_timeout : 1, // [4:4] 338 ast_index_not_found : 1, // [3:3] 339 mcast_bcast : 1, // [2:2] 340 reserved_30a : 1, // [1:1] 341 first_mpdu : 1; // [0:0] 342 uint32_t msdu_done : 1, // [31:31] 343 reserved_31b : 17, // [30:14] 344 rx_bitmap_not_updated : 1, // [13:13] 345 decrypt_status_code : 3, // [12:10] 346 reserved_31a : 10; // [9:0] 347 #endif 348 }; 349 350 351 /* Description RXPCU_MPDU_FILTER_IN_CATEGORY 352 353 Field indicates what the reason was that this MPDU frame 354 was allowed to come into the receive path by RXPCU 355 <enum 0 rxpcu_filter_pass> This MPDU passed the normal frame 356 filter programming of rxpcu 357 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 358 regular frame filter and would have been dropped, were 359 it not for the frame fitting into the 'monitor_client' category. 360 361 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 362 regular frame filter and also did not pass the rxpcu_monitor_client 363 filter. It would have been dropped accept that it did pass 364 the 'monitor_other' category. 365 <enum 3 rxpcu_filter_pass_monitor_ovrd> This MPDU passed 366 the normal frame filter programming of RXPCU but additionally 367 fit into the 'monitor_override_client' category. 368 <legal 0-3> 369 */ 370 371 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 372 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 373 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 374 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 375 376 377 /* Description SW_FRAME_GROUP_ID 378 379 SW processes frames based on certain classifications. This 380 field indicates to what sw classification this MPDU is 381 mapped. 382 The classification is given in priority order 383 384 <enum 0 sw_frame_group_NDP_frame> 385 386 <enum 1 sw_frame_group_Multicast_data> 387 <enum 2 sw_frame_group_Unicast_data> 388 <enum 3 sw_frame_group_Null_data > This includes mpdus of 389 type Data Null. 390 Hamilton v1 included QoS Data Null as well here. 391 <enum 38 sw_frame_group_QoS_Null_data> This includes QoS 392 Null frames except in UL MU or TB PPDUs. 393 <enum 39 sw_frame_group_QoS_Null_data_TB> This includes 394 QoS Null frames in UL MU or TB PPDUs. 395 396 <enum 4 sw_frame_group_mgmt_0000 > 397 <enum 5 sw_frame_group_mgmt_0001 > 398 <enum 6 sw_frame_group_mgmt_0010 > 399 <enum 7 sw_frame_group_mgmt_0011 > 400 <enum 8 sw_frame_group_mgmt_0100 > 401 <enum 9 sw_frame_group_mgmt_0101 > 402 <enum 10 sw_frame_group_mgmt_0110 > 403 <enum 11 sw_frame_group_mgmt_0111 > 404 <enum 12 sw_frame_group_mgmt_1000 > 405 <enum 13 sw_frame_group_mgmt_1001 > 406 <enum 14 sw_frame_group_mgmt_1010 > 407 <enum 15 sw_frame_group_mgmt_1011 > 408 <enum 16 sw_frame_group_mgmt_1100 > 409 <enum 17 sw_frame_group_mgmt_1101 > 410 <enum 18 sw_frame_group_mgmt_1110 > 411 <enum 19 sw_frame_group_mgmt_1111 > 412 413 <enum 20 sw_frame_group_ctrl_0000 > 414 <enum 21 sw_frame_group_ctrl_0001 > 415 <enum 22 sw_frame_group_ctrl_0010 > 416 <enum 23 sw_frame_group_ctrl_0011 > 417 <enum 24 sw_frame_group_ctrl_0100 > 418 <enum 25 sw_frame_group_ctrl_0101 > 419 <enum 26 sw_frame_group_ctrl_0110 > 420 <enum 27 sw_frame_group_ctrl_0111 > 421 <enum 28 sw_frame_group_ctrl_1000 > 422 <enum 29 sw_frame_group_ctrl_1001 > 423 <enum 30 sw_frame_group_ctrl_1010 > 424 <enum 31 sw_frame_group_ctrl_1011 > 425 <enum 32 sw_frame_group_ctrl_1100 > 426 <enum 33 sw_frame_group_ctrl_1101 > 427 <enum 34 sw_frame_group_ctrl_1110 > 428 <enum 35 sw_frame_group_ctrl_1111 > 429 430 <enum 36 sw_frame_group_unsupported> This covers type 3 431 and protocol version != 0 432 433 <enum 37 sw_frame_group_phy_error> PHY reported an error 434 435 436 <legal 0-39> 437 */ 438 439 #define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 440 #define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2 441 #define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8 442 #define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc 443 444 445 /* Description RESERVED_0 446 447 <legal 0> 448 */ 449 450 #define RX_MSDU_END_RESERVED_0_OFFSET 0x0000000000000000 451 #define RX_MSDU_END_RESERVED_0_LSB 9 452 #define RX_MSDU_END_RESERVED_0_MSB 15 453 #define RX_MSDU_END_RESERVED_0_MASK 0x000000000000fe00 454 455 456 /* Description PHY_PPDU_ID 457 458 A ppdu counter value that PHY increments for every PPDU 459 received. The counter value wraps around 460 <legal all> 461 */ 462 463 #define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 464 #define RX_MSDU_END_PHY_PPDU_ID_LSB 16 465 #define RX_MSDU_END_PHY_PPDU_ID_MSB 31 466 #define RX_MSDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 467 468 469 /* Description IP_HDR_CHKSUM 470 471 This can include the IP header checksum or the pseudo header 472 checksum used by TCP/UDP checksum. 473 (with the first byte in the MSB and the second byte in the 474 LSB, i.e. requiring a byte-swap for little-endian FW/SW 475 w.r.t. the byte order in a packet) 476 */ 477 478 #define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x0000000000000000 479 #define RX_MSDU_END_IP_HDR_CHKSUM_LSB 32 480 #define RX_MSDU_END_IP_HDR_CHKSUM_MSB 47 481 #define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff00000000 482 483 484 /* Description REPORTED_MPDU_LENGTH 485 486 MPDU length before decapsulation. Only valid when first_msdu 487 is set. This field is taken directly from the length field 488 of the A-MPDU delimiter or the preamble length field for 489 non-A-MPDU frames. 490 */ 491 492 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x0000000000000000 493 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 48 494 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 61 495 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff000000000000 496 497 498 /* Description RESERVED_1A 499 500 <legal 0> 501 */ 502 503 #define RX_MSDU_END_RESERVED_1A_OFFSET 0x0000000000000000 504 #define RX_MSDU_END_RESERVED_1A_LSB 62 505 #define RX_MSDU_END_RESERVED_1A_MSB 63 506 #define RX_MSDU_END_RESERVED_1A_MASK 0xc000000000000000 507 508 509 /* Description RESERVED_2A 510 511 Hamilton v1 used this for 'key_id_octet.' 512 <legal 0> 513 */ 514 515 #define RX_MSDU_END_RESERVED_2A_OFFSET 0x0000000000000008 516 #define RX_MSDU_END_RESERVED_2A_LSB 0 517 #define RX_MSDU_END_RESERVED_2A_MSB 7 518 #define RX_MSDU_END_RESERVED_2A_MASK 0x00000000000000ff 519 520 521 /* Description CCE_SUPER_RULE 522 523 Indicates the super filter rule 524 */ 525 526 #define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x0000000000000008 527 #define RX_MSDU_END_CCE_SUPER_RULE_LSB 8 528 #define RX_MSDU_END_CCE_SUPER_RULE_MSB 13 529 #define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x0000000000003f00 530 531 532 /* Description CCE_CLASSIFY_NOT_DONE_TRUNCATE 533 534 Classification failed due to truncated frame 535 */ 536 537 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x0000000000000008 538 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 539 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14 540 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x0000000000004000 541 542 543 /* Description CCE_CLASSIFY_NOT_DONE_CCE_DIS 544 545 Classification failed due to CCE global disable 546 */ 547 548 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x0000000000000008 549 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 550 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15 551 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x0000000000008000 552 553 554 /* Description CUMULATIVE_L3_CHECKSUM 555 556 FISA: IP header checksum including the total MSDU length 557 that is part of this flow aggregated so far, reported if 558 'RXOLE_R0_FISA_CTRL. CHKSUM_CUM_IP_LEN_EN' is set 559 560 Set to zero in chips not supporting FISA, e.g. Pine 561 <legal all> 562 */ 563 564 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x0000000000000008 565 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16 566 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31 567 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0x00000000ffff0000 568 569 570 /* Description RULE_INDICATION_31_0 571 572 Bitmap indicating which of rules 31-0 have matched 573 574 In chips with more than 64 CCE rules, e.g. Waikiki, RXOLE 575 shall have a configuration to report any two rule_indication_* 576 in 'RX_MSDU_END.' 577 */ 578 579 #define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000000000008 580 #define RX_MSDU_END_RULE_INDICATION_31_0_LSB 32 581 #define RX_MSDU_END_RULE_INDICATION_31_0_MSB 63 582 #define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff00000000 583 584 585 /* Description IPV6_OPTIONS_CRC 586 587 32 bit CRC computed out of IP v6 extension headers 588 Hamilton v1 used this for 'rule_indication_63_32.' 589 */ 590 591 #define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x0000000000000010 592 #define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0 593 #define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31 594 #define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0x00000000ffffffff 595 596 597 /* Description DA_OFFSET 598 599 Offset into MSDU buffer for DA 600 */ 601 602 #define RX_MSDU_END_DA_OFFSET_OFFSET 0x0000000000000010 603 #define RX_MSDU_END_DA_OFFSET_LSB 32 604 #define RX_MSDU_END_DA_OFFSET_MSB 37 605 #define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f00000000 606 607 608 /* Description SA_OFFSET 609 610 Offset into MSDU buffer for SA 611 */ 612 613 #define RX_MSDU_END_SA_OFFSET_OFFSET 0x0000000000000010 614 #define RX_MSDU_END_SA_OFFSET_LSB 38 615 #define RX_MSDU_END_SA_OFFSET_MSB 43 616 #define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc000000000 617 618 619 /* Description DA_OFFSET_VALID 620 621 da_offset field is valid. This will be set to 0 in case 622 of a dynamic A-MSDU when DA is compressed 623 */ 624 625 #define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x0000000000000010 626 #define RX_MSDU_END_DA_OFFSET_VALID_LSB 44 627 #define RX_MSDU_END_DA_OFFSET_VALID_MSB 44 628 #define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x0000100000000000 629 630 631 /* Description SA_OFFSET_VALID 632 633 sa_offset field is valid. This will be set to 0 in case 634 of a dynamic A-MSDU when SA is compressed 635 */ 636 637 #define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x0000000000000010 638 #define RX_MSDU_END_SA_OFFSET_VALID_LSB 45 639 #define RX_MSDU_END_SA_OFFSET_VALID_MSB 45 640 #define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x0000200000000000 641 642 643 /* Description RESERVED_5A 644 645 <legal 0> 646 */ 647 648 #define RX_MSDU_END_RESERVED_5A_OFFSET 0x0000000000000010 649 #define RX_MSDU_END_RESERVED_5A_LSB 46 650 #define RX_MSDU_END_RESERVED_5A_MSB 47 651 #define RX_MSDU_END_RESERVED_5A_MASK 0x0000c00000000000 652 653 654 /* Description L3_TYPE 655 656 The 16-bit type value indicating the type of L3 later extracted 657 from LLC/SNAP, set to zero if SNAP is not available 658 */ 659 660 #define RX_MSDU_END_L3_TYPE_OFFSET 0x0000000000000010 661 #define RX_MSDU_END_L3_TYPE_LSB 48 662 #define RX_MSDU_END_L3_TYPE_MSB 63 663 #define RX_MSDU_END_L3_TYPE_MASK 0xffff000000000000 664 665 666 /* Description RULE_INDICATION_63_32 667 668 Bitmap indicating which of rules 63-32 have matched 669 670 In chips with more than 64 CCE rules, e.g. Waikiki, RXOLE 671 shall have a configuration to report any two rule_indication_* 672 in 'RX_MSDU_END.' 673 674 Hamilton v1 used this for 'IPv6_options_crc.' 675 */ 676 677 #define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x0000000000000018 678 #define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0 679 #define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31 680 #define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0x00000000ffffffff 681 682 683 /* Description TCP_SEQ_NUMBER 684 685 TCP sequence number (as a number assembled from a TCP packet 686 in big-endian order, i.e. requiring a byte-swap for little-endian 687 FW/SW w.r.t. the byte order in a packet) 688 689 In Pine, if 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' 690 is set, toeplitz_hash_2_or_4 from 'RX_MSDU_START' will be 691 reported here: 692 Controlled by multiple RxOLE registers for TCP/UDP over 693 IPv4/IPv6 - Either Toeplitz hash computed over 2-tuple IPv4 694 or IPv6 src/dest addresses is reported; or, Toeplitz hash 695 computed over 4-tuple IPv4 or IPv6 src/dest addresses and 696 src/dest ports is reported. The Flow_id_toeplitz hash can 697 also be reported here. Usually the hash reported here is 698 the one used for hash-based REO routing (see use_flow_id_toeplitz_clfy 699 in 'RXPT_CLASSIFY_INFO'). Optionally the 3-tuple Toeplitz 700 hash over IPv4 or IPv6 src/dest addresses and L4 protocol 701 can be reported here. 702 (Unsupported in HastingsPrime) 703 */ 704 705 #define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000000000000018 706 #define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 32 707 #define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 63 708 #define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 709 710 711 /* Description TCP_ACK_NUMBER 712 713 TCP acknowledge number (as a number assembled from a TCP 714 packet in big-endian order, i.e. requiring a byte-swap 715 for little-endian FW/SW w.r.t. the byte order in a packet) 716 717 718 In Pine, if 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' 719 is set, flow_id_toeplitz from 'RX_MSDU_START' will be reported 720 here: 721 Toeplitz hash of 5-tuple {IP source address, IP destination 722 address, IP source port, IP destination port, L4 protocol} 723 in case of non-IPSec. In case of IPSec - Toeplitz hash 724 of 4-tuple {IP source address, IP destination address, SPI, 725 L4 protocol}. Optionally the 3-tuple Toeplitz hash over 726 IPv4 or IPv6 src/dest addresses and L4 protocol can be reported 727 here. 728 The relevant Toeplitz key registers are provided in RxOLE's 729 instance of common parser module. These registers are separate 730 from the Toeplitz keys used by ASE/FSE modules inside RxOLE. 731 The actual value will be passed on from common parser module 732 to RxOLE in one of the WHO_* TLVs. 733 (Unsupported in HastingsPrime) 734 */ 735 736 #define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x0000000000000020 737 #define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0 738 #define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31 739 #define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0x00000000ffffffff 740 741 742 /* Description TCP_FLAG 743 744 TCP flags 745 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}(with the NS bit in 746 bit 8 and the FIN bit in bit 0, i.e. in big-endian order, 747 i.e. requiring a byte-swap for little-endian FW/SW w.r.t. 748 the byte order in a packet) 749 */ 750 751 #define RX_MSDU_END_TCP_FLAG_OFFSET 0x0000000000000020 752 #define RX_MSDU_END_TCP_FLAG_LSB 32 753 #define RX_MSDU_END_TCP_FLAG_MSB 40 754 #define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff00000000 755 756 757 /* Description LRO_ELIGIBLE 758 759 Computed out of TCP and IP fields to indicate that this 760 MSDU is eligible for LRO 761 */ 762 763 #define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x0000000000000020 764 #define RX_MSDU_END_LRO_ELIGIBLE_LSB 41 765 #define RX_MSDU_END_LRO_ELIGIBLE_MSB 41 766 #define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x0000020000000000 767 768 769 /* Description RESERVED_9A 770 771 NOTE: DO not assign a field... Internally used in RXOLE.. 772 773 <legal 0> 774 */ 775 776 #define RX_MSDU_END_RESERVED_9A_OFFSET 0x0000000000000020 777 #define RX_MSDU_END_RESERVED_9A_LSB 42 778 #define RX_MSDU_END_RESERVED_9A_MSB 47 779 #define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc0000000000 780 781 782 /* Description WINDOW_SIZE 783 784 TCP receive window size (as a number assembled from a TCP 785 packet in big-endian order, i.e. requiring a byte-swap 786 for little-endian FW/SW w.r.t. the byte order in a packet) 787 788 789 In Pine, if 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' 790 is set, msdu_length from 'RX_MSDU_START' will be reported 791 in the 14 LSBs here: 792 MSDU length in bytes after decapsulation. This field is 793 still valid for MPDU frames without A-MSDU. It still represents 794 MSDU length after decapsulation. 795 (Unsupported in HastingsPrime) 796 */ 797 798 #define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x0000000000000020 799 #define RX_MSDU_END_WINDOW_SIZE_LSB 48 800 #define RX_MSDU_END_WINDOW_SIZE_MSB 63 801 #define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff000000000000 802 803 804 /* Description SA_SW_PEER_ID 805 806 sw_peer_id from the address search entry corresponding to 807 the source address of the MSDU 808 809 Hamilton v1 used this for 'tcp_udp_chksum.' 810 <legal all> 811 */ 812 813 #define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x0000000000000028 814 #define RX_MSDU_END_SA_SW_PEER_ID_LSB 0 815 #define RX_MSDU_END_SA_SW_PEER_ID_MSB 15 816 #define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x000000000000ffff 817 818 819 /* Description SA_IDX_TIMEOUT 820 821 Indicates an unsuccessful MAC source address search due 822 to the expiring of the search timer. 823 */ 824 825 #define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x0000000000000028 826 #define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16 827 #define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16 828 #define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x0000000000010000 829 830 831 /* Description DA_IDX_TIMEOUT 832 833 Indicates an unsuccessful MAC destination address search 834 due to the expiring of the search timer. 835 */ 836 837 #define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x0000000000000028 838 #define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17 839 #define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17 840 #define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x0000000000020000 841 842 843 /* Description TO_DS 844 845 Set if the to DS bit is set in the frame control. 846 847 RXOLE copies this from the 'Struct RX_MPDU_INFO' in 'RX_MPDU_PCU_START.' 848 849 850 Hamilton v1 used this for 'msdu_limit_error.' 851 <legal all> 852 */ 853 854 #define RX_MSDU_END_TO_DS_OFFSET 0x0000000000000028 855 #define RX_MSDU_END_TO_DS_LSB 18 856 #define RX_MSDU_END_TO_DS_MSB 18 857 #define RX_MSDU_END_TO_DS_MASK 0x0000000000040000 858 859 860 /* Description TID 861 862 The TID field in the QoS control field 863 864 Hamilton v1 used bit [19] for 'flow_idx_timeout,' bit [20] 865 for 'flow_idx_invalid,' bit [21] for 'wifi_parser_error' 866 and bit [22] for 'amsdu_parser_error.' 867 <legal all> 868 */ 869 870 #define RX_MSDU_END_TID_OFFSET 0x0000000000000028 871 #define RX_MSDU_END_TID_LSB 19 872 #define RX_MSDU_END_TID_MSB 22 873 #define RX_MSDU_END_TID_MASK 0x0000000000780000 874 875 876 /* Description SA_IS_VALID 877 878 Indicates that OLE found a valid SA entry 879 */ 880 881 #define RX_MSDU_END_SA_IS_VALID_OFFSET 0x0000000000000028 882 #define RX_MSDU_END_SA_IS_VALID_LSB 23 883 #define RX_MSDU_END_SA_IS_VALID_MSB 23 884 #define RX_MSDU_END_SA_IS_VALID_MASK 0x0000000000800000 885 886 887 /* Description DA_IS_VALID 888 889 Indicates that OLE found a valid DA entry 890 */ 891 892 #define RX_MSDU_END_DA_IS_VALID_OFFSET 0x0000000000000028 893 #define RX_MSDU_END_DA_IS_VALID_LSB 24 894 #define RX_MSDU_END_DA_IS_VALID_MSB 24 895 #define RX_MSDU_END_DA_IS_VALID_MASK 0x0000000001000000 896 897 898 /* Description DA_IS_MCBC 899 900 Field Only valid if "da_is_valid" is set 901 902 Indicates the DA address was a Multicast of Broadcast address. 903 904 */ 905 906 #define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x0000000000000028 907 #define RX_MSDU_END_DA_IS_MCBC_LSB 25 908 #define RX_MSDU_END_DA_IS_MCBC_MSB 25 909 #define RX_MSDU_END_DA_IS_MCBC_MASK 0x0000000002000000 910 911 912 /* Description L3_HEADER_PADDING 913 914 Number of bytes padded to make sure that the L3 header 915 will always start of a Dword boundary 916 */ 917 918 #define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x0000000000000028 919 #define RX_MSDU_END_L3_HEADER_PADDING_LSB 26 920 #define RX_MSDU_END_L3_HEADER_PADDING_MSB 27 921 #define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x000000000c000000 922 923 924 /* Description FIRST_MSDU 925 926 Indicates the first MSDU of A-MSDU. If both first_msdu 927 and last_msdu are set in the MSDU then this is a non-aggregated 928 MSDU frame: normal MPDU. Interior MSDU in an A-MSDU shall 929 have both first_mpdu and last_mpdu bits set to 0. 930 */ 931 932 #define RX_MSDU_END_FIRST_MSDU_OFFSET 0x0000000000000028 933 #define RX_MSDU_END_FIRST_MSDU_LSB 28 934 #define RX_MSDU_END_FIRST_MSDU_MSB 28 935 #define RX_MSDU_END_FIRST_MSDU_MASK 0x0000000010000000 936 937 938 /* Description LAST_MSDU 939 940 Indicates the last MSDU of the A-MSDU. MPDU end status 941 is only valid when last_msdu is set. 942 */ 943 944 #define RX_MSDU_END_LAST_MSDU_OFFSET 0x0000000000000028 945 #define RX_MSDU_END_LAST_MSDU_LSB 29 946 #define RX_MSDU_END_LAST_MSDU_MSB 29 947 #define RX_MSDU_END_LAST_MSDU_MASK 0x0000000020000000 948 949 950 /* Description FR_DS 951 952 Set if the from DS bit is set in the frame control. 953 954 RXOLE copies this from the 'Struct RX_MPDU_INFO' in 'RX_MPDU_PCU_START.' 955 956 957 Hamilton v1 used this for 'tcp_udp_chksum_fail_copy.' 958 <legal all> 959 */ 960 961 #define RX_MSDU_END_FR_DS_OFFSET 0x0000000000000028 962 #define RX_MSDU_END_FR_DS_LSB 30 963 #define RX_MSDU_END_FR_DS_MSB 30 964 #define RX_MSDU_END_FR_DS_MASK 0x0000000040000000 965 966 967 /* Description IP_CHKSUM_FAIL_COPY 968 969 If 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is set, 970 ip_chksum_fail from 'RX_ATTENTION' will be reported in the 971 MSB here: 972 Indicates that the computed checksum (ip_hdr_chksum) did 973 not match the checksum in the IP header. 974 (unsupported in HastingsPrime) 975 */ 976 977 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000028 978 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31 979 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31 980 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x0000000080000000 981 982 983 /* Description SA_IDX 984 985 The offset in the address table which matches the MAC source 986 address. 987 */ 988 989 #define RX_MSDU_END_SA_IDX_OFFSET 0x0000000000000028 990 #define RX_MSDU_END_SA_IDX_LSB 32 991 #define RX_MSDU_END_SA_IDX_MSB 47 992 #define RX_MSDU_END_SA_IDX_MASK 0x0000ffff00000000 993 994 995 /* Description DA_IDX_OR_SW_PEER_ID 996 997 Based on a register configuration in RXOLE, this field will 998 contain: 999 The offset in the address table which matches the MAC destination 1000 address 1001 OR: 1002 sw_peer_id from the address search entry corresponding to 1003 the destination address of the MSDU 1004 */ 1005 1006 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000000000000028 1007 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 48 1008 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 63 1009 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff000000000000 1010 1011 1012 /* Description MSDU_DROP 1013 1014 When set, REO shall drop this MSDU and not forward it to 1015 any other ring... 1016 <legal all> 1017 */ 1018 1019 #define RX_MSDU_END_MSDU_DROP_OFFSET 0x0000000000000030 1020 #define RX_MSDU_END_MSDU_DROP_LSB 0 1021 #define RX_MSDU_END_MSDU_DROP_MSB 0 1022 #define RX_MSDU_END_MSDU_DROP_MASK 0x0000000000000001 1023 1024 1025 /* Description REO_DESTINATION_INDICATION 1026 1027 The ID of the REO exit ring where the MSDU frame shall push 1028 after (MPDU level) reordering has finished. 1029 1030 <enum 0 reo_destination_sw0> Reo will push the frame into 1031 the REO2SW0 ring 1032 <enum 1 reo_destination_sw1> Reo will push the frame into 1033 the REO2SW1 ring 1034 <enum 2 reo_destination_sw2> Reo will push the frame into 1035 the REO2SW2 ring 1036 <enum 3 reo_destination_sw3> Reo will push the frame into 1037 the REO2SW3 ring 1038 <enum 4 reo_destination_sw4> Reo will push the frame into 1039 the REO2SW4 ring 1040 <enum 5 reo_destination_release> Reo will push the frame 1041 into the REO_release ring 1042 <enum 6 reo_destination_fw> Reo will push the frame into 1043 the REO2FW ring 1044 <enum 7 reo_destination_sw5> Reo will push the frame into 1045 the REO2SW5 ring (REO remaps this in chips without REO2SW5 1046 ring, e.g. Pine) 1047 <enum 8 reo_destination_sw6> Reo will push the frame into 1048 the REO2SW6 ring (REO remaps this in chips without REO2SW6 1049 ring, e.g. Pine) 1050 <enum 9 reo_destination_sw7> Reo will push the frame into 1051 the REO2SW7 ring (REO remaps this in chips without REO2SW7 1052 ring) 1053 <enum 10 reo_destination_sw8> Reo will push the frame into 1054 the REO2SW8 ring (REO remaps this in chips without REO2SW8 1055 ring) 1056 <enum 11 reo_destination_11> REO remaps this 1057 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 1058 REO remaps this 1059 <enum 14 reo_destination_14> REO remaps this 1060 <enum 15 reo_destination_15> REO remaps this 1061 <enum 16 reo_destination_16> REO remaps this 1062 <enum 17 reo_destination_17> REO remaps this 1063 <enum 18 reo_destination_18> REO remaps this 1064 <enum 19 reo_destination_19> REO remaps this 1065 <enum 20 reo_destination_20> REO remaps this 1066 <enum 21 reo_destination_21> REO remaps this 1067 <enum 22 reo_destination_22> REO remaps this 1068 <enum 23 reo_destination_23> REO remaps this 1069 <enum 24 reo_destination_24> REO remaps this 1070 <enum 25 reo_destination_25> REO remaps this 1071 <enum 26 reo_destination_26> REO remaps this 1072 <enum 27 reo_destination_27> REO remaps this 1073 <enum 28 reo_destination_28> REO remaps this 1074 <enum 29 reo_destination_29> REO remaps this 1075 <enum 30 reo_destination_30> REO remaps this 1076 <enum 31 reo_destination_31> REO remaps this 1077 1078 <legal all> 1079 */ 1080 1081 #define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000030 1082 #define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1 1083 #define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5 1084 #define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x000000000000003e 1085 1086 1087 /* Description FLOW_IDX 1088 1089 Flow table index 1090 <legal all> 1091 */ 1092 1093 #define RX_MSDU_END_FLOW_IDX_OFFSET 0x0000000000000030 1094 #define RX_MSDU_END_FLOW_IDX_LSB 6 1095 #define RX_MSDU_END_FLOW_IDX_MSB 25 1096 #define RX_MSDU_END_FLOW_IDX_MASK 0x0000000003ffffc0 1097 1098 1099 /* Description USE_PPE 1100 1101 Indicates to RXDMA to ignore the REO_destination_indication 1102 and use a programmed value corresponding to the REO2PPE 1103 ring 1104 1105 This override to REO2PPE for packets requiring multiple 1106 buffers shall be disabled based on an RXDMA configuration, 1107 as PPE may not support such packets. 1108 <legal all> 1109 */ 1110 1111 #define RX_MSDU_END_USE_PPE_OFFSET 0x0000000000000030 1112 #define RX_MSDU_END_USE_PPE_LSB 26 1113 #define RX_MSDU_END_USE_PPE_MSB 26 1114 #define RX_MSDU_END_USE_PPE_MASK 0x0000000004000000 1115 1116 1117 /* Description MESH_STA 1118 1119 When set, this is a Mesh (11s) STA. 1120 1121 The interpretation of the A-MSDU 'Length' field in the MPDU 1122 (if any) is decided by the e-numerations below. 1123 1124 <enum 0 MESH_DISABLE> 1125 <enum 1 MESH_Q2Q> A-MSDU 'Length' is big endian and includes 1126 the length of Mesh Control. 1127 <enum 2 MESH_11S_BE> A-MSDU 'Length' is big endian and excludes 1128 the length of Mesh Control. 1129 <enum 3 MESH_11S_LE> A-MSDU 'Length' is little endian and 1130 excludes the length of Mesh Control. This is 802.11s-compliant. 1131 1132 <legal all> 1133 */ 1134 1135 #define RX_MSDU_END_MESH_STA_OFFSET 0x0000000000000030 1136 #define RX_MSDU_END_MESH_STA_LSB 27 1137 #define RX_MSDU_END_MESH_STA_MSB 28 1138 #define RX_MSDU_END_MESH_STA_MASK 0x0000000018000000 1139 1140 1141 /* Description VLAN_CTAG_STRIPPED 1142 1143 Set by RXOLE if it stripped 4-bytes of C-VLAN Tag from the 1144 packet 1145 <legal all> 1146 */ 1147 1148 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x0000000000000030 1149 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29 1150 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29 1151 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x0000000020000000 1152 1153 1154 /* Description VLAN_STAG_STRIPPED 1155 1156 Set by RXOLE if it stripped 4-bytes of S-VLAN Tag from the 1157 packet 1158 <legal all> 1159 */ 1160 1161 #define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x0000000000000030 1162 #define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30 1163 #define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30 1164 #define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x0000000040000000 1165 1166 1167 /* Description FRAGMENT_FLAG 1168 1169 Indicates that this is an 802.11 fragment frame. This is 1170 set when either the more_frag bit is set in the frame control 1171 or the fragment number is not zero. Only set when first_msdu 1172 is set. 1173 */ 1174 1175 #define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x0000000000000030 1176 #define RX_MSDU_END_FRAGMENT_FLAG_LSB 31 1177 #define RX_MSDU_END_FRAGMENT_FLAG_MSB 31 1178 #define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x0000000080000000 1179 1180 1181 /* Description FSE_METADATA 1182 1183 FSE related meta data: 1184 <legal all> 1185 */ 1186 1187 #define RX_MSDU_END_FSE_METADATA_OFFSET 0x0000000000000030 1188 #define RX_MSDU_END_FSE_METADATA_LSB 32 1189 #define RX_MSDU_END_FSE_METADATA_MSB 63 1190 #define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff00000000 1191 1192 1193 /* Description CCE_METADATA 1194 1195 CCE related meta data: 1196 <legal all> 1197 */ 1198 1199 #define RX_MSDU_END_CCE_METADATA_OFFSET 0x0000000000000038 1200 #define RX_MSDU_END_CCE_METADATA_LSB 0 1201 #define RX_MSDU_END_CCE_METADATA_MSB 15 1202 #define RX_MSDU_END_CCE_METADATA_MASK 0x000000000000ffff 1203 1204 1205 /* Description TCP_UDP_CHKSUM 1206 1207 The value of the computed TCP/UDP checksum. A mode bit 1208 selects whether this checksum is the full checksum or the 1209 partial checksum which does not include the pseudo header. (with 1210 the first byte in the MSB and the second byte in the LSB, 1211 i.e. requiring a byte-swap for little-endian FW/SW w.r.t. 1212 the byte order in a packet) 1213 1214 Hamilton v1 used this for 'sa_sw_peer_id.' 1215 */ 1216 1217 #define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x0000000000000038 1218 #define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16 1219 #define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31 1220 #define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0x00000000ffff0000 1221 1222 1223 /* Description AGGREGATION_COUNT 1224 1225 FISA: Number of MSDU's aggregated so far 1226 1227 Set to zero in chips not supporting FISA, e.g. Pine 1228 <legal all> 1229 */ 1230 1231 #define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000000000000038 1232 #define RX_MSDU_END_AGGREGATION_COUNT_LSB 32 1233 #define RX_MSDU_END_AGGREGATION_COUNT_MSB 39 1234 #define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff00000000 1235 1236 1237 /* Description FLOW_AGGREGATION_CONTINUATION 1238 1239 FISA: To indicate that this MSDU can be aggregated with 1240 the previous packet with the same flow id 1241 1242 Set to zero in chips not supporting FISA, e.g. Pine 1243 <legal all> 1244 */ 1245 1246 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000000000000038 1247 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 40 1248 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 40 1249 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x0000010000000000 1250 1251 1252 /* Description FISA_TIMEOUT 1253 1254 FISA: To indicate that the aggregation has restarted for 1255 this flow due to timeout 1256 1257 Set to zero in chips not supporting FISA, e.g. Pine 1258 <legal all> 1259 */ 1260 1261 #define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000000000000038 1262 #define RX_MSDU_END_FISA_TIMEOUT_LSB 41 1263 #define RX_MSDU_END_FISA_TIMEOUT_MSB 41 1264 #define RX_MSDU_END_FISA_TIMEOUT_MASK 0x0000020000000000 1265 1266 1267 /* Description TCP_UDP_CHKSUM_FAIL_COPY 1268 1269 if 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is set, 1270 tcp_udp_chksum_fail from 'RX_ATTENTION' will be reported 1271 here: 1272 Indicates that the computed checksum (tcp_udp_chksum) did 1273 not match the checksum in the TCP/UDP header. 1274 (unsupported in HastingsPrime) 1275 */ 1276 1277 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000038 1278 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 42 1279 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 42 1280 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x0000040000000000 1281 1282 1283 /* Description MSDU_LIMIT_ERROR 1284 1285 Indicates that the MSDU threshold was exceeded and thus 1286 all the rest of the MSDUs will not be scattered and will 1287 not be decapsulated but will be DMA'ed in RAW format as 1288 a single MSDU buffer 1289 */ 1290 1291 #define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000038 1292 #define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 43 1293 #define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 43 1294 #define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x0000080000000000 1295 1296 1297 /* Description FLOW_IDX_TIMEOUT 1298 1299 Indicates an unsuccessful flow search due to the expiring 1300 of the search timer. 1301 <legal all> 1302 */ 1303 1304 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000038 1305 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 44 1306 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 44 1307 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x0000100000000000 1308 1309 1310 /* Description FLOW_IDX_INVALID 1311 1312 flow id is not valid 1313 <legal all> 1314 */ 1315 1316 #define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000000000000038 1317 #define RX_MSDU_END_FLOW_IDX_INVALID_LSB 45 1318 #define RX_MSDU_END_FLOW_IDX_INVALID_MSB 45 1319 #define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x0000200000000000 1320 1321 1322 /* Description CCE_MATCH 1323 1324 Indicates that this status has a corresponding MSDU that 1325 requires FW processing. The OLE will have classification 1326 ring mask registers which will indicate the ring(s) for 1327 packets and descriptors which need FW attention. 1328 */ 1329 1330 #define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000000000000038 1331 #define RX_MSDU_END_CCE_MATCH_LSB 46 1332 #define RX_MSDU_END_CCE_MATCH_MSB 46 1333 #define RX_MSDU_END_CCE_MATCH_MASK 0x0000400000000000 1334 1335 1336 /* Description AMSDU_PARSER_ERROR 1337 1338 A-MSDU could not be properly de-agregated. 1339 <legal all> 1340 */ 1341 1342 #define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000038 1343 #define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 47 1344 #define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 47 1345 #define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x0000800000000000 1346 1347 1348 /* Description CUMULATIVE_IP_LENGTH 1349 1350 FISA: Total MSDU length that is part of this flow aggregated 1351 so far 1352 1353 Set to zero in chips not supporting FISA, e.g. Pine 1354 <legal all> 1355 */ 1356 1357 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000000000000038 1358 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 48 1359 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 63 1360 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff000000000000 1361 1362 1363 /* Description KEY_ID_OCTET 1364 1365 The key ID octet from the IV. Only valid when first_msdu 1366 is set. 1367 */ 1368 1369 #define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x0000000000000040 1370 #define RX_MSDU_END_KEY_ID_OCTET_LSB 0 1371 #define RX_MSDU_END_KEY_ID_OCTET_MSB 7 1372 #define RX_MSDU_END_KEY_ID_OCTET_MASK 0x00000000000000ff 1373 1374 1375 /* Description RESERVED_16A 1376 1377 Hamilton v1 used bits [31:16] for 'cumulative_IP_length.' 1378 1379 <legal 0> 1380 */ 1381 1382 #define RX_MSDU_END_RESERVED_16A_OFFSET 0x0000000000000040 1383 #define RX_MSDU_END_RESERVED_16A_LSB 8 1384 #define RX_MSDU_END_RESERVED_16A_MSB 31 1385 #define RX_MSDU_END_RESERVED_16A_MASK 0x00000000ffffff00 1386 1387 1388 /* Description RESERVED_17A 1389 1390 <legal 0> 1391 */ 1392 1393 #define RX_MSDU_END_RESERVED_17A_OFFSET 0x0000000000000040 1394 #define RX_MSDU_END_RESERVED_17A_LSB 32 1395 #define RX_MSDU_END_RESERVED_17A_MSB 37 1396 #define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f00000000 1397 1398 1399 /* Description SERVICE_CODE 1400 1401 Opaque service code between PPE and Wi-Fi 1402 1403 This field gets passed on by REO to PPE in the EDMA descriptor 1404 ('REO_TO_PPE_RING'). 1405 1406 <legal all> 1407 */ 1408 1409 #define RX_MSDU_END_SERVICE_CODE_OFFSET 0x0000000000000040 1410 #define RX_MSDU_END_SERVICE_CODE_LSB 38 1411 #define RX_MSDU_END_SERVICE_CODE_MSB 46 1412 #define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc000000000 1413 1414 1415 /* Description PRIORITY_VALID 1416 1417 This field gets passed on by REO to PPE in the EDMA descriptor 1418 ('REO_TO_PPE_RING'). 1419 1420 <legal all> 1421 */ 1422 1423 #define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x0000000000000040 1424 #define RX_MSDU_END_PRIORITY_VALID_LSB 47 1425 #define RX_MSDU_END_PRIORITY_VALID_MSB 47 1426 #define RX_MSDU_END_PRIORITY_VALID_MASK 0x0000800000000000 1427 1428 1429 /* Description INTRA_BSS 1430 1431 This packet needs intra-BSS routing by SW as the 'vdev_id' 1432 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 1433 that this MSDU was got in. 1434 1435 <legal all> 1436 */ 1437 1438 #define RX_MSDU_END_INTRA_BSS_OFFSET 0x0000000000000040 1439 #define RX_MSDU_END_INTRA_BSS_LSB 48 1440 #define RX_MSDU_END_INTRA_BSS_MSB 48 1441 #define RX_MSDU_END_INTRA_BSS_MASK 0x0001000000000000 1442 1443 1444 /* Description DEST_CHIP_ID 1445 1446 If intra_bss is set, copied by RXOLE from 'ADDR_SEARCH_ENTRY' 1447 to support intra-BSS routing with multi-chip multi-link 1448 operation. 1449 1450 This indicates into which chip's TCL the packet should be 1451 queued. 1452 1453 <legal all> 1454 */ 1455 1456 #define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x0000000000000040 1457 #define RX_MSDU_END_DEST_CHIP_ID_LSB 49 1458 #define RX_MSDU_END_DEST_CHIP_ID_MSB 50 1459 #define RX_MSDU_END_DEST_CHIP_ID_MASK 0x0006000000000000 1460 1461 1462 /* Description MULTICAST_ECHO 1463 1464 If set, this packet is a multicast echo, i.e. the DA is 1465 multicast and Rx OLE SA search with mcast_echo_check = 1 1466 passed. RXDMA should release such packets to WBM. 1467 1468 <legal all> 1469 */ 1470 1471 #define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x0000000000000040 1472 #define RX_MSDU_END_MULTICAST_ECHO_LSB 51 1473 #define RX_MSDU_END_MULTICAST_ECHO_MSB 51 1474 #define RX_MSDU_END_MULTICAST_ECHO_MASK 0x0008000000000000 1475 1476 1477 /* Description WDS_LEARNING_EVENT 1478 1479 If set, this packet has an SA search failure with WDS learning 1480 enabled for the peer. RXOLE should route this TLV to the 1481 RXDMA0 status ring to notify FW. 1482 1483 <legal all> 1484 */ 1485 1486 #define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x0000000000000040 1487 #define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 52 1488 #define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 52 1489 #define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x0010000000000000 1490 1491 1492 /* Description WDS_ROAMING_EVENT 1493 1494 If set, this packet's SA 'Sw_peer_id' mismatches the 'Sw_peer_id' 1495 of the peer through which the packet was got, indicating 1496 the SA node has roamed. RXOLE should route this TLV to 1497 the RXDMA0 status ring to notify FW. 1498 1499 <legal all> 1500 */ 1501 1502 #define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x0000000000000040 1503 #define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 53 1504 #define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 53 1505 #define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x0020000000000000 1506 1507 1508 /* Description WDS_KEEP_ALIVE_EVENT 1509 1510 If set, the AST timestamp for this packet's SA is older 1511 than the current timestamp by more than a threshold programmed 1512 in RXOLE. RXOLE should route this TLV to the RXDMA0 status 1513 ring to notify FW to keep the AST entry for the SA alive. 1514 1515 1516 <legal all> 1517 */ 1518 1519 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x0000000000000040 1520 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 54 1521 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 54 1522 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x0040000000000000 1523 1524 1525 /* Description DEST_CHIP_PMAC_ID 1526 1527 If intra_bss is set, copied by RXOLE from 'ADDR_SEARCH_ENTRY' 1528 to support intra-BSS routing with multi-chip multi-link 1529 operation. 1530 1531 This indicates into which link/'vdev' the packet should 1532 be queued in TCL. 1533 1534 <legal all> 1535 */ 1536 1537 #define RX_MSDU_END_DEST_CHIP_PMAC_ID_OFFSET 0x0000000000000040 1538 #define RX_MSDU_END_DEST_CHIP_PMAC_ID_LSB 55 1539 #define RX_MSDU_END_DEST_CHIP_PMAC_ID_MSB 55 1540 #define RX_MSDU_END_DEST_CHIP_PMAC_ID_MASK 0x0080000000000000 1541 1542 1543 /* Description RESERVED_17B 1544 1545 <legal 0> 1546 */ 1547 1548 #define RX_MSDU_END_RESERVED_17B_OFFSET 0x0000000000000040 1549 #define RX_MSDU_END_RESERVED_17B_LSB 56 1550 #define RX_MSDU_END_RESERVED_17B_MSB 63 1551 #define RX_MSDU_END_RESERVED_17B_MASK 0xff00000000000000 1552 1553 1554 /* Description MSDU_LENGTH 1555 1556 Words 18 - 26 are from Lithium 'RX_MSDU_START.' 1557 1558 MSDU length in bytes after decapsulation. 1559 1560 This field is still valid for MPDU frames without A-MSDU. 1561 It still represents MSDU length after decapsulation 1562 */ 1563 1564 #define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x0000000000000048 1565 #define RX_MSDU_END_MSDU_LENGTH_LSB 0 1566 #define RX_MSDU_END_MSDU_LENGTH_MSB 13 1567 #define RX_MSDU_END_MSDU_LENGTH_MASK 0x0000000000003fff 1568 1569 1570 /* Description STBC 1571 1572 When set, use STBC transmission rates 1573 */ 1574 1575 #define RX_MSDU_END_STBC_OFFSET 0x0000000000000048 1576 #define RX_MSDU_END_STBC_LSB 14 1577 #define RX_MSDU_END_STBC_MSB 14 1578 #define RX_MSDU_END_STBC_MASK 0x0000000000004000 1579 1580 1581 /* Description IPSEC_ESP 1582 1583 Set if IPv4/v6 packet is using IPsec ESP 1584 */ 1585 1586 #define RX_MSDU_END_IPSEC_ESP_OFFSET 0x0000000000000048 1587 #define RX_MSDU_END_IPSEC_ESP_LSB 15 1588 #define RX_MSDU_END_IPSEC_ESP_MSB 15 1589 #define RX_MSDU_END_IPSEC_ESP_MASK 0x0000000000008000 1590 1591 1592 /* Description L3_OFFSET 1593 1594 Depending upon mode bit, this field either indicates the 1595 L3 offset in bytes from the start of the RX_HEADER or the 1596 IP offset in bytes from the start of the packet after decapsulation. 1597 The latter is only valid if ipv4_proto or ipv6_proto is 1598 set. 1599 */ 1600 1601 #define RX_MSDU_END_L3_OFFSET_OFFSET 0x0000000000000048 1602 #define RX_MSDU_END_L3_OFFSET_LSB 16 1603 #define RX_MSDU_END_L3_OFFSET_MSB 22 1604 #define RX_MSDU_END_L3_OFFSET_MASK 0x00000000007f0000 1605 1606 1607 /* Description IPSEC_AH 1608 1609 Set if IPv4/v6 packet is using IPsec AH 1610 */ 1611 1612 #define RX_MSDU_END_IPSEC_AH_OFFSET 0x0000000000000048 1613 #define RX_MSDU_END_IPSEC_AH_LSB 23 1614 #define RX_MSDU_END_IPSEC_AH_MSB 23 1615 #define RX_MSDU_END_IPSEC_AH_MASK 0x0000000000800000 1616 1617 1618 /* Description L4_OFFSET 1619 1620 Depending upon mode bit, this field either indicates the 1621 L4 offset nin bytes from the start of RX_HEADER(only valid 1622 if either ipv4_proto or ipv6_proto is set to 1) or indicates 1623 the offset in bytes to the start of TCP or UDP header from 1624 the start of the IP header after decapsulation(Only valid 1625 if tcp_proto or udp_proto is set). The value 0 indicates 1626 that the offset is longer than 127 bytes. 1627 */ 1628 1629 #define RX_MSDU_END_L4_OFFSET_OFFSET 0x0000000000000048 1630 #define RX_MSDU_END_L4_OFFSET_LSB 24 1631 #define RX_MSDU_END_L4_OFFSET_MSB 31 1632 #define RX_MSDU_END_L4_OFFSET_MASK 0x00000000ff000000 1633 1634 1635 /* Description MSDU_NUMBER 1636 1637 Indicates the MSDU number within a MPDU. This value is 1638 reset to zero at the start of each MPDU. If the number 1639 of MSDU exceeds 255 this number will wrap using modulo 256. 1640 1641 */ 1642 1643 #define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000000000000048 1644 #define RX_MSDU_END_MSDU_NUMBER_LSB 32 1645 #define RX_MSDU_END_MSDU_NUMBER_MSB 39 1646 #define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff00000000 1647 1648 1649 /* Description DECAP_FORMAT 1650 1651 Indicates the format after decapsulation: 1652 1653 <enum 0 RAW> No encapsulation 1654 <enum 1 Native_WiFi> 1655 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 1656 1657 <enum 3 802_3> Indicate Ethernet 1658 1659 <legal all> 1660 */ 1661 1662 #define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000000000000048 1663 #define RX_MSDU_END_DECAP_FORMAT_LSB 40 1664 #define RX_MSDU_END_DECAP_FORMAT_MSB 41 1665 #define RX_MSDU_END_DECAP_FORMAT_MASK 0x0000030000000000 1666 1667 1668 /* Description IPV4_PROTO 1669 1670 Set if L2 layer indicates IPv4 protocol. 1671 */ 1672 1673 #define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000000000000048 1674 #define RX_MSDU_END_IPV4_PROTO_LSB 42 1675 #define RX_MSDU_END_IPV4_PROTO_MSB 42 1676 #define RX_MSDU_END_IPV4_PROTO_MASK 0x0000040000000000 1677 1678 1679 /* Description IPV6_PROTO 1680 1681 Set if L2 layer indicates IPv6 protocol. 1682 */ 1683 1684 #define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000000000000048 1685 #define RX_MSDU_END_IPV6_PROTO_LSB 43 1686 #define RX_MSDU_END_IPV6_PROTO_MSB 43 1687 #define RX_MSDU_END_IPV6_PROTO_MASK 0x0000080000000000 1688 1689 1690 /* Description TCP_PROTO 1691 1692 Set if the ipv4_proto or ipv6_proto are set and the IP protocol 1693 indicates TCP. 1694 */ 1695 1696 #define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000000000000048 1697 #define RX_MSDU_END_TCP_PROTO_LSB 44 1698 #define RX_MSDU_END_TCP_PROTO_MSB 44 1699 #define RX_MSDU_END_TCP_PROTO_MASK 0x0000100000000000 1700 1701 1702 /* Description UDP_PROTO 1703 1704 Set if the ipv4_proto or ipv6_proto are set and the IP protocol 1705 indicates UDP. 1706 */ 1707 1708 #define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000000000000048 1709 #define RX_MSDU_END_UDP_PROTO_LSB 45 1710 #define RX_MSDU_END_UDP_PROTO_MSB 45 1711 #define RX_MSDU_END_UDP_PROTO_MASK 0x0000200000000000 1712 1713 1714 /* Description IP_FRAG 1715 1716 Indicates that either the IP More frag bit is set or IP 1717 frag number is non-zero. If set indicates that this is 1718 a fragmented IP packet. 1719 */ 1720 1721 #define RX_MSDU_END_IP_FRAG_OFFSET 0x0000000000000048 1722 #define RX_MSDU_END_IP_FRAG_LSB 46 1723 #define RX_MSDU_END_IP_FRAG_MSB 46 1724 #define RX_MSDU_END_IP_FRAG_MASK 0x0000400000000000 1725 1726 1727 /* Description TCP_ONLY_ACK 1728 1729 Set if only the TCP Ack bit is set in the TCP flags and 1730 if the TCP payload is 0. 1731 */ 1732 1733 #define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000000000000048 1734 #define RX_MSDU_END_TCP_ONLY_ACK_LSB 47 1735 #define RX_MSDU_END_TCP_ONLY_ACK_MSB 47 1736 #define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x0000800000000000 1737 1738 1739 /* Description DA_IS_BCAST_MCAST 1740 1741 The destination address is broadcast or multicast. 1742 */ 1743 1744 #define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000048 1745 #define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 48 1746 #define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 48 1747 #define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x0001000000000000 1748 1749 1750 /* Description TOEPLITZ_HASH_SEL 1751 1752 Actual choosen Hash. 1753 1754 0 -> Toeplitz hash of 2-tuple (IP source address, IP destination 1755 address)1 -> Toeplitz hash of 4-tuple (IP source address, 1756 IP destination address, L4 (TCP/UDP) source port, L4 (TCP/UDP) 1757 destination port) 1758 2 -> Toeplitz of flow_id 1759 3 -> "Zero" is used 1760 <legal all> 1761 */ 1762 1763 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000048 1764 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 49 1765 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 50 1766 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x0006000000000000 1767 1768 1769 /* Description IP_FIXED_HEADER_VALID 1770 1771 Fixed 20-byte IPv4 header or 40-byte IPv6 header parsed 1772 fully within first 256 bytes of the packet 1773 */ 1774 1775 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000048 1776 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 51 1777 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 51 1778 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x0008000000000000 1779 1780 1781 /* Description IP_EXTN_HEADER_VALID 1782 1783 IPv6/IPv6 header, including IPv4 options and recognizable 1784 extension headers parsed fully within first 256 bytes of 1785 the packet 1786 */ 1787 1788 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000048 1789 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 52 1790 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 52 1791 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x0010000000000000 1792 1793 1794 /* Description TCP_UDP_HEADER_VALID 1795 1796 Fixed 20-byte TCP (excluding TCP options) or 8-byte UDP 1797 header parsed fully within first 256 bytes of the packet 1798 1799 */ 1800 1801 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000048 1802 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 53 1803 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 53 1804 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x0020000000000000 1805 1806 1807 /* Description MESH_CONTROL_PRESENT 1808 1809 When set, this MSDU includes the 'Mesh Control' field 1810 <legal all> 1811 */ 1812 1813 #define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000048 1814 #define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 54 1815 #define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 54 1816 #define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x0040000000000000 1817 1818 1819 /* Description LDPC 1820 1821 When set, indicates that LDPC coding was used. 1822 <legal all> 1823 */ 1824 1825 #define RX_MSDU_END_LDPC_OFFSET 0x0000000000000048 1826 #define RX_MSDU_END_LDPC_LSB 55 1827 #define RX_MSDU_END_LDPC_MSB 55 1828 #define RX_MSDU_END_LDPC_MASK 0x0080000000000000 1829 1830 1831 /* Description IP4_PROTOCOL_IP6_NEXT_HEADER 1832 1833 For IPv4 this is the 8 bit protocol field (when ipv4_proto 1834 is set). For IPv6 this is the 8 bit next_header field (when 1835 ipv6_proto is set). 1836 */ 1837 1838 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000048 1839 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 56 1840 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 63 1841 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff00000000000000 1842 1843 1844 /* Description VLAN_CTAG_CI 1845 1846 2 bytes of C-VLAN Tag Control Information from WHO_L2_LLC 1847 1848 1849 Hamilton v1 used this for 'toeplitz_hash_2_or_4.' 1850 */ 1851 1852 #define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x0000000000000050 1853 #define RX_MSDU_END_VLAN_CTAG_CI_LSB 0 1854 #define RX_MSDU_END_VLAN_CTAG_CI_MSB 15 1855 #define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x000000000000ffff 1856 1857 1858 /* Description VLAN_STAG_CI 1859 1860 Words 18 - 26 are from Lithium 'RX_MSDU_START.' 1861 1862 2 bytes of S-VLAN Tag Control Information from WHO_L2_LLC 1863 in case of double VLAN 1864 1865 Hamilton v1 used this for 'toeplitz_hash_2_or_4.' 1866 */ 1867 1868 #define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x0000000000000050 1869 #define RX_MSDU_END_VLAN_STAG_CI_LSB 16 1870 #define RX_MSDU_END_VLAN_STAG_CI_MSB 31 1871 #define RX_MSDU_END_VLAN_STAG_CI_MASK 0x00000000ffff0000 1872 1873 1874 /* Description PEER_META_DATA 1875 1876 Meta data that SW has programmed in the Peer table entry 1877 of the transmitting STA. 1878 1879 RXOLE copies this from the 'Struct RX_MPDU_INFO' in 'RX_MPDU_PCU_START.' 1880 1881 1882 Hamilton v1 used this for 'Flow_id_toeplitz.' 1883 <legal all> 1884 */ 1885 1886 #define RX_MSDU_END_PEER_META_DATA_OFFSET 0x0000000000000050 1887 #define RX_MSDU_END_PEER_META_DATA_LSB 32 1888 #define RX_MSDU_END_PEER_META_DATA_MSB 63 1889 #define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff00000000 1890 1891 1892 /* Description USER_RSSI 1893 1894 RSSI for this user 1895 <legal all> 1896 */ 1897 1898 #define RX_MSDU_END_USER_RSSI_OFFSET 0x0000000000000058 1899 #define RX_MSDU_END_USER_RSSI_LSB 0 1900 #define RX_MSDU_END_USER_RSSI_MSB 7 1901 #define RX_MSDU_END_USER_RSSI_MASK 0x00000000000000ff 1902 1903 1904 /* Description PKT_TYPE 1905 1906 Packet type: 1907 <enum 0 dot11a>802.11a PPDU type 1908 <enum 1 dot11b>802.11b PPDU type 1909 <enum 2 dot11n_mm>802.11n Mixed Mode PPDU type 1910 <enum 3 dot11ac>802.11ac PPDU type 1911 <enum 4 dot11ax>802.11ax PPDU type 1912 <enum 5 dot11ba>802.11ba (WUR) PPDU type 1913 <enum 6 dot11be>802.11be PPDU type 1914 <enum 7 dot11az>802.11az (ranging) PPDU type 1915 <enum 8 dot11n_gf>802.11n Green Field PPDU type (unsupported 1916 & aborted) 1917 */ 1918 1919 #define RX_MSDU_END_PKT_TYPE_OFFSET 0x0000000000000058 1920 #define RX_MSDU_END_PKT_TYPE_LSB 8 1921 #define RX_MSDU_END_PKT_TYPE_MSB 11 1922 #define RX_MSDU_END_PKT_TYPE_MASK 0x0000000000000f00 1923 1924 1925 /* Description SGI 1926 1927 Field only valid when pkt type is HT, VHT or HE. 1928 1929 <enum 0 0_8_us_sgi > Legacy normal GI. Can also be used 1930 for HE 1931 <enum 1 0_4_us_sgi > Legacy short GI. Can also be used 1932 for HE 1933 <enum 2 1_6_us_sgi > HE related GI 1934 <enum 3 3_2_us_sgi > HE related GI 1935 <legal 0 - 3> 1936 */ 1937 1938 #define RX_MSDU_END_SGI_OFFSET 0x0000000000000058 1939 #define RX_MSDU_END_SGI_LSB 12 1940 #define RX_MSDU_END_SGI_MSB 13 1941 #define RX_MSDU_END_SGI_MASK 0x0000000000003000 1942 1943 1944 /* Description RATE_MCS 1945 1946 For details, refer to MCS_TYPE description 1947 Note: This is "rate" in case of 11a/11b 1948 1949 <legal all> 1950 */ 1951 1952 #define RX_MSDU_END_RATE_MCS_OFFSET 0x0000000000000058 1953 #define RX_MSDU_END_RATE_MCS_LSB 14 1954 #define RX_MSDU_END_RATE_MCS_MSB 17 1955 #define RX_MSDU_END_RATE_MCS_MASK 0x000000000003c000 1956 1957 1958 /* Description RECEIVE_BANDWIDTH 1959 1960 Full receive Bandwidth 1961 1962 <enum 0 20_mhz>20 Mhz BW 1963 <enum 1 40_mhz>40 Mhz BW 1964 <enum 2 80_mhz>80 Mhz BW 1965 <enum 3 160_mhz>160 Mhz BW 1966 <enum 4 320_mhz>320 Mhz BW 1967 <enum 5 240_mhz>240 Mhz BW 1968 */ 1969 1970 #define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000058 1971 #define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 18 1972 #define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 20 1973 #define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x00000000001c0000 1974 1975 1976 /* Description RECEPTION_TYPE 1977 1978 Indicates what type of reception this is. 1979 <enum 0 reception_type_SU > Basic SU reception (not 1980 part of OFDMA or MIMO) 1981 <enum 1 reception_type_MU_MIMO > This is related to 1982 DL type of reception 1983 <enum 2 reception_type_MU_OFDMA > This is related to 1984 DL type of reception 1985 <enum 3 reception_type_MU_OFDMA_MIMO > This is related 1986 to DL type of reception 1987 <enum 4 reception_type_UL_MU_MIMO > This is related 1988 to UL type of reception 1989 <enum 5 reception_type_UL_MU_OFDMA > This is related 1990 to UL type of reception 1991 <enum 6 reception_type_UL_MU_OFDMA_MIMO > This is related 1992 to UL type of reception 1993 1994 <legal 0-6> 1995 */ 1996 1997 #define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x0000000000000058 1998 #define RX_MSDU_END_RECEPTION_TYPE_LSB 21 1999 #define RX_MSDU_END_RECEPTION_TYPE_MSB 23 2000 #define RX_MSDU_END_RECEPTION_TYPE_MASK 0x0000000000e00000 2001 2002 2003 /* Description MIMO_SS_BITMAP 2004 2005 Field only valid when Reception_type for the MPDU from this 2006 STA is some form of MIMO reception 2007 2008 Bitmap, with each bit indicating if the related spatial 2009 stream is used for this STA 2010 LSB related to SS 0 2011 2012 0: spatial stream not used for this reception 2013 1: spatial stream used for this reception 2014 2015 Note: Only 7 bits are reported here to accommodate field 2016 'msdu_done_copy.' 2017 <legal all> 2018 */ 2019 2020 #define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x0000000000000058 2021 #define RX_MSDU_END_MIMO_SS_BITMAP_LSB 24 2022 #define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30 2023 #define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x000000007f000000 2024 2025 2026 /* Description MSDU_DONE_COPY 2027 2028 If set indicates that the RX packet data, RX header data, 2029 RX PPDU start descriptor, RX MPDU start/end descriptor, 2030 RX MSDU start/end descriptors and RX Attention descriptor 2031 are all valid. This bit is in the last 64-bit of the descriptor 2032 expected to be subscribed to in Waikiki and Hamilton v2. 2033 2034 <legal 1> 2035 */ 2036 2037 #define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x0000000000000058 2038 #define RX_MSDU_END_MSDU_DONE_COPY_LSB 31 2039 #define RX_MSDU_END_MSDU_DONE_COPY_MSB 31 2040 #define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x0000000080000000 2041 2042 2043 /* Description FLOW_ID_TOEPLITZ 2044 2045 Toeplitz hash of 5-tuple 2046 {IP source address, IP destination address, IP source port, 2047 IP destination port, L4 protocol} in case of non-IPSec. 2048 2049 In case of IPSec - Toeplitz hash of 4-tuple 2050 {IP source address, IP destination address, SPI, L4 protocol} 2051 2052 2053 In Pine, optionally the 3-tuple Toeplitz hash over IPv4 2054 or IPv6 src/dest addresses and L4 protocol can be reported 2055 here. (Unsupported in HastingsPrime) 2056 2057 The relevant Toeplitz key registers are provided in RxOLE's 2058 instance of common parser module. These registers are separate 2059 from the Toeplitz keys used by ASE/FSE modules inside RxOLE.The 2060 actual value will be passed on from common parser module 2061 to RxOLE in one of the WHO_* TLVs. 2062 2063 Hamilton v1 used this for 'ppdu_start_timestamp_31_0.' 2064 <legal all> 2065 */ 2066 2067 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000058 2068 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 32 2069 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 63 2070 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff00000000 2071 2072 2073 /* Description PPDU_START_TIMESTAMP_63_32 2074 2075 Timestamp that indicates when the PPDU that contained this 2076 MPDU started on the medium, upper 32 bits 2077 <legal all> 2078 */ 2079 2080 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000060 2081 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0 2082 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31 2083 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff 2084 2085 2086 /* Description SW_PHY_META_DATA 2087 2088 SW programmed Meta data provided by the PHY. 2089 2090 Can be used for SW to indicate the channel the device is 2091 on. 2092 <legal all> 2093 */ 2094 2095 #define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x0000000000000060 2096 #define RX_MSDU_END_SW_PHY_META_DATA_LSB 32 2097 #define RX_MSDU_END_SW_PHY_META_DATA_MSB 63 2098 #define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff00000000 2099 2100 2101 /* Description PPDU_START_TIMESTAMP_31_0 2102 2103 Words 18 - 26 are from Lithium 'RX_MSDU_START.' 2104 2105 Timestamp that indicates when the PPDU that contained this 2106 MPDU started on the medium, lower 32 bits 2107 2108 Hamilton v1 used bits [15:0] for 'vlan_ctag_ci and bits [31:16] 2109 for 'vlan_stag_ci.' 2110 <legal all> 2111 */ 2112 2113 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000068 2114 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0 2115 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31 2116 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff 2117 2118 2119 /* Description TOEPLITZ_HASH_2_OR_4 2120 2121 Controlled by multiple RxOLE registers for TCP/UDP over 2122 IPv4/IPv6 - Either, Toeplitz hash computed over 2-tuple 2123 IPv4 or IPv6 src/dest addresses is reported; or, Toeplitz 2124 hash computed over 4-tuple IPv4 or IPv6 src/dest addresses 2125 and src/dest ports is reported. The Flow_id_toeplitz hash 2126 can also be reported here. Usually the hash reported here 2127 is the one used for hash-based REO routing (see use_flow_id_toeplitz_clfy 2128 in 'RXPT_CLASSIFY_INFO'). 2129 2130 In Pine, optionally the 3-tuple Toeplitz hash over IPv4 2131 or IPv6 src/dest addresses and L4 protocol can be reported 2132 here. (Unsupported in HastingsPrime) 2133 */ 2134 2135 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000068 2136 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 32 2137 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 63 2138 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 2139 2140 2141 /* Description RESERVED_28A 2142 2143 <legal 0> 2144 */ 2145 2146 #define RX_MSDU_END_RESERVED_28A_OFFSET 0x0000000000000070 2147 #define RX_MSDU_END_RESERVED_28A_LSB 0 2148 #define RX_MSDU_END_RESERVED_28A_MSB 15 2149 #define RX_MSDU_END_RESERVED_28A_MASK 0x000000000000ffff 2150 2151 2152 /* Description SA_15_0 2153 2154 Source MAC address bits [15:0] (with the fifth byte in the 2155 MSB and the last byte in the LSB, i.e. requiring a byte-swap 2156 for little-endian FW) 2157 */ 2158 2159 #define RX_MSDU_END_SA_15_0_OFFSET 0x0000000000000070 2160 #define RX_MSDU_END_SA_15_0_LSB 16 2161 #define RX_MSDU_END_SA_15_0_MSB 31 2162 #define RX_MSDU_END_SA_15_0_MASK 0x00000000ffff0000 2163 2164 2165 /* Description SA_47_16 2166 2167 Source MAC address bits [47:16] (with the first byte in 2168 the MSB and the fourth byte in the LSB, i.e. requiring a 2169 byte-swap for little-endian FW) 2170 */ 2171 2172 #define RX_MSDU_END_SA_47_16_OFFSET 0x0000000000000070 2173 #define RX_MSDU_END_SA_47_16_LSB 32 2174 #define RX_MSDU_END_SA_47_16_MSB 63 2175 #define RX_MSDU_END_SA_47_16_MASK 0xffffffff00000000 2176 2177 2178 /* Description FIRST_MPDU 2179 2180 Words 30 - 31 are from Lithium 'RX_ATTENTION.' 2181 2182 Indicates the first MSDU of the PPDU. If both first_mpdu 2183 and last_mpdu are set in the MSDU then this is a not an 2184 A-MPDU frame but a stand alone MPDU. Interior MPDU in 2185 an A-MPDU shall have both first_mpdu and last_mpdu bits 2186 set to 0. The PPDU start status will only be valid when 2187 this bit is set. 2188 */ 2189 2190 #define RX_MSDU_END_FIRST_MPDU_OFFSET 0x0000000000000078 2191 #define RX_MSDU_END_FIRST_MPDU_LSB 0 2192 #define RX_MSDU_END_FIRST_MPDU_MSB 0 2193 #define RX_MSDU_END_FIRST_MPDU_MASK 0x0000000000000001 2194 2195 2196 /* Description RESERVED_30A 2197 2198 <legal 0> 2199 */ 2200 2201 #define RX_MSDU_END_RESERVED_30A_OFFSET 0x0000000000000078 2202 #define RX_MSDU_END_RESERVED_30A_LSB 1 2203 #define RX_MSDU_END_RESERVED_30A_MSB 1 2204 #define RX_MSDU_END_RESERVED_30A_MASK 0x0000000000000002 2205 2206 2207 /* Description MCAST_BCAST 2208 2209 Multicast / broadcast indicator. Only set when the MAC 2210 address 1 bit 0 is set indicating mcast/bcast and the BSSID 2211 matches one of the 4 BSSID registers. Only set when first_msdu 2212 is set. 2213 */ 2214 2215 #define RX_MSDU_END_MCAST_BCAST_OFFSET 0x0000000000000078 2216 #define RX_MSDU_END_MCAST_BCAST_LSB 2 2217 #define RX_MSDU_END_MCAST_BCAST_MSB 2 2218 #define RX_MSDU_END_MCAST_BCAST_MASK 0x0000000000000004 2219 2220 2221 /* Description AST_INDEX_NOT_FOUND 2222 2223 Only valid when first_msdu is set. 2224 2225 Indicates no AST matching entries within the the max search 2226 count. 2227 */ 2228 2229 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000078 2230 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3 2231 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3 2232 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x0000000000000008 2233 2234 2235 /* Description AST_INDEX_TIMEOUT 2236 2237 Only valid when first_msdu is set. 2238 2239 Indicates an unsuccessful search in the address seach table 2240 due to timeout. 2241 */ 2242 2243 #define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000078 2244 #define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4 2245 #define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4 2246 #define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x0000000000000010 2247 2248 2249 /* Description POWER_MGMT 2250 2251 Power management bit set in the 802.11 header. Only set 2252 when first_msdu is set. 2253 */ 2254 2255 #define RX_MSDU_END_POWER_MGMT_OFFSET 0x0000000000000078 2256 #define RX_MSDU_END_POWER_MGMT_LSB 5 2257 #define RX_MSDU_END_POWER_MGMT_MSB 5 2258 #define RX_MSDU_END_POWER_MGMT_MASK 0x0000000000000020 2259 2260 2261 /* Description NON_QOS 2262 2263 Set if packet is not a non-QoS data frame. Only set when 2264 first_msdu is set. 2265 */ 2266 2267 #define RX_MSDU_END_NON_QOS_OFFSET 0x0000000000000078 2268 #define RX_MSDU_END_NON_QOS_LSB 6 2269 #define RX_MSDU_END_NON_QOS_MSB 6 2270 #define RX_MSDU_END_NON_QOS_MASK 0x0000000000000040 2271 2272 2273 /* Description NULL_DATA 2274 2275 Set if frame type indicates either null data or QoS null 2276 data format. Only set when first_msdu is set. 2277 */ 2278 2279 #define RX_MSDU_END_NULL_DATA_OFFSET 0x0000000000000078 2280 #define RX_MSDU_END_NULL_DATA_LSB 7 2281 #define RX_MSDU_END_NULL_DATA_MSB 7 2282 #define RX_MSDU_END_NULL_DATA_MASK 0x0000000000000080 2283 2284 2285 /* Description MGMT_TYPE 2286 2287 Set if packet is a management packet. Only set when first_msdu 2288 is set. 2289 */ 2290 2291 #define RX_MSDU_END_MGMT_TYPE_OFFSET 0x0000000000000078 2292 #define RX_MSDU_END_MGMT_TYPE_LSB 8 2293 #define RX_MSDU_END_MGMT_TYPE_MSB 8 2294 #define RX_MSDU_END_MGMT_TYPE_MASK 0x0000000000000100 2295 2296 2297 /* Description CTRL_TYPE 2298 2299 Set if packet is a control packet. Only set when first_msdu 2300 is set. 2301 */ 2302 2303 #define RX_MSDU_END_CTRL_TYPE_OFFSET 0x0000000000000078 2304 #define RX_MSDU_END_CTRL_TYPE_LSB 9 2305 #define RX_MSDU_END_CTRL_TYPE_MSB 9 2306 #define RX_MSDU_END_CTRL_TYPE_MASK 0x0000000000000200 2307 2308 2309 /* Description MORE_DATA 2310 2311 Set if more bit in frame control is set. Only set when 2312 first_msdu is set. 2313 */ 2314 2315 #define RX_MSDU_END_MORE_DATA_OFFSET 0x0000000000000078 2316 #define RX_MSDU_END_MORE_DATA_LSB 10 2317 #define RX_MSDU_END_MORE_DATA_MSB 10 2318 #define RX_MSDU_END_MORE_DATA_MASK 0x0000000000000400 2319 2320 2321 /* Description EOSP 2322 2323 Set if the EOSP (end of service period) bit in the QoS control 2324 field is set. Only set when first_msdu is set. 2325 */ 2326 2327 #define RX_MSDU_END_EOSP_OFFSET 0x0000000000000078 2328 #define RX_MSDU_END_EOSP_LSB 11 2329 #define RX_MSDU_END_EOSP_MSB 11 2330 #define RX_MSDU_END_EOSP_MASK 0x0000000000000800 2331 2332 2333 /* Description A_MSDU_ERROR 2334 2335 Set if number of MSDUs in A-MSDU is above a threshold or 2336 if the size of the MSDU is invalid. This receive buffer 2337 will contain all of the remainder of the MSDUs in this 2338 MPDU without decapsulation. 2339 */ 2340 2341 #define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x0000000000000078 2342 #define RX_MSDU_END_A_MSDU_ERROR_LSB 12 2343 #define RX_MSDU_END_A_MSDU_ERROR_MSB 12 2344 #define RX_MSDU_END_A_MSDU_ERROR_MASK 0x0000000000001000 2345 2346 2347 /* Description RESERVED_30B 2348 2349 Hamilton v1 used this for 'Fragment_flag.' 2350 <legal 0> 2351 */ 2352 2353 #define RX_MSDU_END_RESERVED_30B_OFFSET 0x0000000000000078 2354 #define RX_MSDU_END_RESERVED_30B_LSB 13 2355 #define RX_MSDU_END_RESERVED_30B_MSB 13 2356 #define RX_MSDU_END_RESERVED_30B_MASK 0x0000000000002000 2357 2358 2359 /* Description ORDER 2360 2361 Set if the order bit in the frame control is set. Only 2362 set when first_msdu is set. 2363 */ 2364 2365 #define RX_MSDU_END_ORDER_OFFSET 0x0000000000000078 2366 #define RX_MSDU_END_ORDER_LSB 14 2367 #define RX_MSDU_END_ORDER_MSB 14 2368 #define RX_MSDU_END_ORDER_MASK 0x0000000000004000 2369 2370 2371 /* Description WIFI_PARSER_ERROR 2372 2373 Indicates that the WiFi frame has one of the following errors 2374 2375 o has less than minimum allowed bytes as per standard 2376 o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) 2377 <legal all> 2378 */ 2379 2380 #define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x0000000000000078 2381 #define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15 2382 #define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15 2383 #define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x0000000000008000 2384 2385 2386 /* Description OVERFLOW_ERR 2387 2388 RXPCU Receive FIFO ran out of space to receive the full 2389 MPDU. Therefor this MPDU is terminated early and is thus 2390 corrupted. 2391 2392 This MPDU will not be ACKed. 2393 RXPCU might still be able to correctly receive the following 2394 MPDUs in the PPDU if enough fifo space became available 2395 in time 2396 */ 2397 2398 #define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000078 2399 #define RX_MSDU_END_OVERFLOW_ERR_LSB 16 2400 #define RX_MSDU_END_OVERFLOW_ERR_MSB 16 2401 #define RX_MSDU_END_OVERFLOW_ERR_MASK 0x0000000000010000 2402 2403 2404 /* Description MSDU_LENGTH_ERR 2405 2406 Indicates that the MSDU length from the 802.3 encapsulated 2407 length field extends beyond the MPDU boundary or if the 2408 length is less than 14 bytes. 2409 Merged with original "other_msdu_err": Indicates that the 2410 MSDU threshold was exceeded and thus all the rest of the 2411 MSDUs will not be scattered and will not be decasulated 2412 but will be DMA'ed in RAW format as a single MSDU buffer 2413 2414 */ 2415 2416 #define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000078 2417 #define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17 2418 #define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17 2419 #define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x0000000000020000 2420 2421 2422 /* Description TCP_UDP_CHKSUM_FAIL 2423 2424 Indicates that the computed checksum (tcp_udp_chksum in 'RX_MSDU_END') 2425 did not match the checksum in the TCP/UDP header. 2426 */ 2427 2428 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000078 2429 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18 2430 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18 2431 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x0000000000040000 2432 2433 2434 /* Description IP_CHKSUM_FAIL 2435 2436 Indicates that the computed checksum (ip_hdr_chksum in 'RX_MSDU_END') 2437 did not match the checksum in the IP header. 2438 */ 2439 2440 #define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x0000000000000078 2441 #define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19 2442 #define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19 2443 #define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x0000000000080000 2444 2445 2446 /* Description SA_IDX_INVALID 2447 2448 Indicates no matching entry was found in the address search 2449 table for the source MAC address. 2450 */ 2451 2452 #define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x0000000000000078 2453 #define RX_MSDU_END_SA_IDX_INVALID_LSB 20 2454 #define RX_MSDU_END_SA_IDX_INVALID_MSB 20 2455 #define RX_MSDU_END_SA_IDX_INVALID_MASK 0x0000000000100000 2456 2457 2458 /* Description DA_IDX_INVALID 2459 2460 Indicates no matching entry was found in the address search 2461 table for the destination MAC address. 2462 */ 2463 2464 #define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x0000000000000078 2465 #define RX_MSDU_END_DA_IDX_INVALID_LSB 21 2466 #define RX_MSDU_END_DA_IDX_INVALID_MSB 21 2467 #define RX_MSDU_END_DA_IDX_INVALID_MASK 0x0000000000200000 2468 2469 2470 /* Description AMSDU_ADDR_MISMATCH 2471 2472 Indicates that an A-MSDU with 'from DS = 0' had an SA mismatching 2473 TA or an A-MDU with 'to DS = 0' had a DA mismatching RA 2474 2475 */ 2476 2477 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x0000000000000078 2478 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22 2479 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22 2480 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x0000000000400000 2481 2482 2483 /* Description RX_IN_TX_DECRYPT_BYP 2484 2485 Indicates that RX packet is not decrypted as Crypto is busy 2486 with TX packet processing. 2487 */ 2488 2489 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000078 2490 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23 2491 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23 2492 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000000000800000 2493 2494 2495 /* Description ENCRYPT_REQUIRED 2496 2497 Indicates that this data type frame is not encrypted even 2498 if the policy for this MPDU requires encryption as indicated 2499 in the peer entry key type. 2500 */ 2501 2502 #define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x0000000000000078 2503 #define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24 2504 #define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24 2505 #define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x0000000001000000 2506 2507 2508 /* Description DIRECTED 2509 2510 MPDU is a directed packet which means that the RA matched 2511 our STA addresses. In proxySTA it means that the TA matched 2512 an entry in our address search table with the corresponding 2513 "no_ack" bit is the address search entry cleared. 2514 */ 2515 2516 #define RX_MSDU_END_DIRECTED_OFFSET 0x0000000000000078 2517 #define RX_MSDU_END_DIRECTED_LSB 25 2518 #define RX_MSDU_END_DIRECTED_MSB 25 2519 #define RX_MSDU_END_DIRECTED_MASK 0x0000000002000000 2520 2521 2522 /* Description BUFFER_FRAGMENT 2523 2524 Indicates that at least one of the rx buffers has been fragmented. 2525 If set the FW should look at the rx_frag_info descriptor 2526 described below. 2527 */ 2528 2529 #define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x0000000000000078 2530 #define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26 2531 #define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26 2532 #define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x0000000004000000 2533 2534 2535 /* Description MPDU_LENGTH_ERR 2536 2537 Indicates that the MPDU was pre-maturely terminated resulting 2538 in a truncated MPDU. Don't trust the MPDU length field. 2539 2540 */ 2541 2542 #define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000078 2543 #define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27 2544 #define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27 2545 #define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x0000000008000000 2546 2547 2548 /* Description TKIP_MIC_ERR 2549 2550 Indicates that the MPDU Michael integrity check failed 2551 */ 2552 2553 #define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000078 2554 #define RX_MSDU_END_TKIP_MIC_ERR_LSB 28 2555 #define RX_MSDU_END_TKIP_MIC_ERR_MSB 28 2556 #define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x0000000010000000 2557 2558 2559 /* Description DECRYPT_ERR 2560 2561 Indicates that the MPDU decrypt integrity check failed or 2562 CRYPTO received an encrypted frame, but did not get a valid 2563 corresponding key id in the peer entry. 2564 */ 2565 2566 #define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x0000000000000078 2567 #define RX_MSDU_END_DECRYPT_ERR_LSB 29 2568 #define RX_MSDU_END_DECRYPT_ERR_MSB 29 2569 #define RX_MSDU_END_DECRYPT_ERR_MASK 0x0000000020000000 2570 2571 2572 /* Description UNENCRYPTED_FRAME_ERR 2573 2574 Copied here by RX OLE from the RX_MPDU_END TLV 2575 */ 2576 2577 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000078 2578 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30 2579 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30 2580 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0000000040000000 2581 2582 2583 /* Description FCS_ERR 2584 2585 Indicates that the MPDU FCS check failed 2586 */ 2587 2588 #define RX_MSDU_END_FCS_ERR_OFFSET 0x0000000000000078 2589 #define RX_MSDU_END_FCS_ERR_LSB 31 2590 #define RX_MSDU_END_FCS_ERR_MSB 31 2591 #define RX_MSDU_END_FCS_ERR_MASK 0x0000000080000000 2592 2593 2594 /* Description RESERVED_31A 2595 2596 <legal 0> 2597 */ 2598 2599 #define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000000000000078 2600 #define RX_MSDU_END_RESERVED_31A_LSB 32 2601 #define RX_MSDU_END_RESERVED_31A_MSB 41 2602 #define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff00000000 2603 2604 2605 /* Description DECRYPT_STATUS_CODE 2606 2607 Field provides insight into the decryption performed 2608 2609 <enum 0 decrypt_ok> Frame had protection enabled and decrypted 2610 properly 2611 <enum 1 decrypt_unprotected_frame > Frame is unprotected 2612 and hence bypassed 2613 <enum 2 decrypt_data_err > Frame has protection enabled 2614 and could not be properly d ecrypted due to MIC/ICV mismatch 2615 etc. 2616 <enum 3 decrypt_key_invalid > Frame has protection enabled 2617 but the key that was required to decrypt this frame was 2618 not valid 2619 <enum 4 decrypt_peer_entry_invalid > Frame has protection 2620 enabled but the key that was required to decrypt this frame 2621 was not valid 2622 <enum 5 decrypt_other > Reserved for other indications 2623 2624 <legal 0 - 5> 2625 */ 2626 2627 #define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000078 2628 #define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 42 2629 #define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 44 2630 #define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c0000000000 2631 2632 2633 /* Description RX_BITMAP_NOT_UPDATED 2634 2635 Frame is received, but RXPCU could not update the receive 2636 bitmap due to (temporary) fifo contraints. 2637 <legal all> 2638 */ 2639 2640 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000078 2641 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 45 2642 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 45 2643 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x0000200000000000 2644 2645 2646 /* Description RESERVED_31B 2647 2648 <legal 0> 2649 */ 2650 2651 #define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000000000000078 2652 #define RX_MSDU_END_RESERVED_31B_LSB 46 2653 #define RX_MSDU_END_RESERVED_31B_MSB 62 2654 #define RX_MSDU_END_RESERVED_31B_MASK 0x7fffc00000000000 2655 2656 2657 /* Description MSDU_DONE 2658 2659 Words 27 - 28 are from Lithium 'RX_ATTENTION.' 2660 2661 If set indicates that the RX packet data, RX header data, 2662 RX PPDU start descriptor, RX MPDU start/end descriptor, 2663 RX MSDU start/end descriptors and RX Attention descriptor 2664 are all valid. This bit must be in the last octet of the 2665 descriptor. 2666 */ 2667 2668 #define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000000000000078 2669 #define RX_MSDU_END_MSDU_DONE_LSB 63 2670 #define RX_MSDU_END_MSDU_DONE_MSB 63 2671 #define RX_MSDU_END_MSDU_DONE_MASK 0x8000000000000000 2672 2673 2674 2675 #endif // RX_MSDU_END 2676