1*5113495bSYour Name 2*5113495bSYour Name /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name 18*5113495bSYour Name 19*5113495bSYour Name 20*5113495bSYour Name 21*5113495bSYour Name 22*5113495bSYour Name 23*5113495bSYour Name 24*5113495bSYour Name 25*5113495bSYour Name 26*5113495bSYour Name #ifndef _RX_MSDU_EXT_DESC_INFO_H_ 27*5113495bSYour Name #define _RX_MSDU_EXT_DESC_INFO_H_ 28*5113495bSYour Name #if !defined(__ASSEMBLER__) 29*5113495bSYour Name #endif 30*5113495bSYour Name 31*5113495bSYour Name #define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1 32*5113495bSYour Name 33*5113495bSYour Name 34*5113495bSYour Name struct rx_msdu_ext_desc_info { 35*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 36*5113495bSYour Name uint32_t reo_destination_indication : 5, // [4:0] 37*5113495bSYour Name service_code : 9, // [13:5] 38*5113495bSYour Name priority_valid : 1, // [14:14] 39*5113495bSYour Name data_offset : 12, // [26:15] 40*5113495bSYour Name src_link_id : 3, // [29:27] 41*5113495bSYour Name reserved_0a : 2; // [31:30] 42*5113495bSYour Name #else 43*5113495bSYour Name uint32_t reserved_0a : 2, // [31:30] 44*5113495bSYour Name src_link_id : 3, // [29:27] 45*5113495bSYour Name data_offset : 12, // [26:15] 46*5113495bSYour Name priority_valid : 1, // [14:14] 47*5113495bSYour Name service_code : 9, // [13:5] 48*5113495bSYour Name reo_destination_indication : 5; // [4:0] 49*5113495bSYour Name #endif 50*5113495bSYour Name }; 51*5113495bSYour Name 52*5113495bSYour Name 53*5113495bSYour Name /* Description REO_DESTINATION_INDICATION 54*5113495bSYour Name 55*5113495bSYour Name Parsed from RX_MSDU_END TLV . In the case MSDU spans over 56*5113495bSYour Name multiple buffers, this field will be valid in the Last 57*5113495bSYour Name buffer used by the MSDU 58*5113495bSYour Name 59*5113495bSYour Name The ID of the REO exit ring where the MSDU frame shall push 60*5113495bSYour Name after (MPDU level) reordering has finished. 61*5113495bSYour Name 62*5113495bSYour Name <enum 0 reo_destination_sw0> Reo will push the frame into 63*5113495bSYour Name the REO2SW0 ring 64*5113495bSYour Name <enum 1 reo_destination_sw1> Reo will push the frame into 65*5113495bSYour Name the REO2SW1 ring 66*5113495bSYour Name <enum 2 reo_destination_sw2> Reo will push the frame into 67*5113495bSYour Name the REO2SW2 ring 68*5113495bSYour Name <enum 3 reo_destination_sw3> Reo will push the frame into 69*5113495bSYour Name the REO2SW3 ring 70*5113495bSYour Name <enum 4 reo_destination_sw4> Reo will push the frame into 71*5113495bSYour Name the REO2SW4 ring 72*5113495bSYour Name <enum 5 reo_destination_release> Reo will push the frame 73*5113495bSYour Name into the REO_release ring 74*5113495bSYour Name <enum 6 reo_destination_fw> Reo will push the frame into 75*5113495bSYour Name the REO2FW ring 76*5113495bSYour Name <enum 7 reo_destination_sw5> Reo will push the frame into 77*5113495bSYour Name the REO2SW5 ring (REO remaps this in chips without REO2SW5 78*5113495bSYour Name ring, e.g. Pine) 79*5113495bSYour Name <enum 8 reo_destination_sw6> Reo will push the frame into 80*5113495bSYour Name the REO2SW6 ring (REO remaps this in chips without REO2SW6 81*5113495bSYour Name ring, e.g. Pine) 82*5113495bSYour Name <enum 9 reo_destination_sw7> Reo will push the frame into 83*5113495bSYour Name the REO2SW7 ring (REO remaps this in chips without REO2SW7 84*5113495bSYour Name ring) 85*5113495bSYour Name <enum 10 reo_destination_sw8> Reo will push the frame into 86*5113495bSYour Name the REO2SW8 ring (REO remaps this in chips without REO2SW8 87*5113495bSYour Name ring) 88*5113495bSYour Name <enum 11 reo_destination_11> REO remaps this 89*5113495bSYour Name <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 90*5113495bSYour Name REO remaps this 91*5113495bSYour Name <enum 14 reo_destination_14> REO remaps this 92*5113495bSYour Name <enum 15 reo_destination_15> REO remaps this 93*5113495bSYour Name <enum 16 reo_destination_16> REO remaps this 94*5113495bSYour Name <enum 17 reo_destination_17> REO remaps this 95*5113495bSYour Name <enum 18 reo_destination_18> REO remaps this 96*5113495bSYour Name <enum 19 reo_destination_19> REO remaps this 97*5113495bSYour Name <enum 20 reo_destination_20> REO remaps this 98*5113495bSYour Name <enum 21 reo_destination_21> REO remaps this 99*5113495bSYour Name <enum 22 reo_destination_22> REO remaps this 100*5113495bSYour Name <enum 23 reo_destination_23> REO remaps this 101*5113495bSYour Name <enum 24 reo_destination_24> REO remaps this 102*5113495bSYour Name <enum 25 reo_destination_25> REO remaps this 103*5113495bSYour Name <enum 26 reo_destination_26> REO remaps this 104*5113495bSYour Name <enum 27 reo_destination_27> REO remaps this 105*5113495bSYour Name <enum 28 reo_destination_28> REO remaps this 106*5113495bSYour Name <enum 29 reo_destination_29> REO remaps this 107*5113495bSYour Name <enum 30 reo_destination_30> REO remaps this 108*5113495bSYour Name <enum 31 reo_destination_31> REO remaps this 109*5113495bSYour Name 110*5113495bSYour Name <legal all> 111*5113495bSYour Name */ 112*5113495bSYour Name 113*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 114*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB 0 115*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB 4 116*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f 117*5113495bSYour Name 118*5113495bSYour Name 119*5113495bSYour Name /* Description SERVICE_CODE 120*5113495bSYour Name 121*5113495bSYour Name Opaque service code between PPE and Wi-Fi 122*5113495bSYour Name 123*5113495bSYour Name This field gets passed on by REO to PPE in the EDMA descriptor 124*5113495bSYour Name ('REO_TO_PPE_RING'). 125*5113495bSYour Name 126*5113495bSYour Name <legal all> 127*5113495bSYour Name */ 128*5113495bSYour Name 129*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET 0x00000000 130*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB 5 131*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB 13 132*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK 0x00003fe0 133*5113495bSYour Name 134*5113495bSYour Name 135*5113495bSYour Name /* Description PRIORITY_VALID 136*5113495bSYour Name 137*5113495bSYour Name This field gets passed on by REO to PPE in the EDMA descriptor 138*5113495bSYour Name ('REO_TO_PPE_RING'). 139*5113495bSYour Name 140*5113495bSYour Name <legal all> 141*5113495bSYour Name */ 142*5113495bSYour Name 143*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET 0x00000000 144*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB 14 145*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB 14 146*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK 0x00004000 147*5113495bSYour Name 148*5113495bSYour Name 149*5113495bSYour Name /* Description DATA_OFFSET 150*5113495bSYour Name 151*5113495bSYour Name The offset to Rx packet data within the buffer (including 152*5113495bSYour Name Rx DMA offset programming and L3 header padding inserted 153*5113495bSYour Name by Rx OLE). 154*5113495bSYour Name 155*5113495bSYour Name This field gets passed on by REO to PPE in the EDMA descriptor 156*5113495bSYour Name ('REO_TO_PPE_RING'). 157*5113495bSYour Name 158*5113495bSYour Name <legal all> 159*5113495bSYour Name */ 160*5113495bSYour Name 161*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET 0x00000000 162*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB 15 163*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB 26 164*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK 0x07ff8000 165*5113495bSYour Name 166*5113495bSYour Name 167*5113495bSYour Name /* Description SRC_LINK_ID 168*5113495bSYour Name 169*5113495bSYour Name Consumer: SW 170*5113495bSYour Name Producer: RXDMA 171*5113495bSYour Name 172*5113495bSYour Name Set to the link ID of the PMAC that received the frame 173*5113495bSYour Name <legal all> 174*5113495bSYour Name */ 175*5113495bSYour Name 176*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_OFFSET 0x00000000 177*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_LSB 27 178*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MSB 29 179*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MASK 0x38000000 180*5113495bSYour Name 181*5113495bSYour Name 182*5113495bSYour Name /* Description RESERVED_0A 183*5113495bSYour Name 184*5113495bSYour Name <legal 0> 185*5113495bSYour Name */ 186*5113495bSYour Name 187*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET 0x00000000 188*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB 30 189*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB 31 190*5113495bSYour Name #define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK 0xc0000000 191*5113495bSYour Name 192*5113495bSYour Name 193*5113495bSYour Name 194*5113495bSYour Name #endif // RX_MSDU_EXT_DESC_INFO 195