1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_MSDU_EXT_DESC_INFO_H_ 27 #define _RX_MSDU_EXT_DESC_INFO_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1 32 33 34 struct rx_msdu_ext_desc_info { 35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 36 uint32_t reo_destination_indication : 5, // [4:0] 37 service_code : 9, // [13:5] 38 priority_valid : 1, // [14:14] 39 data_offset : 12, // [26:15] 40 src_link_id : 3, // [29:27] 41 reserved_0a : 2; // [31:30] 42 #else 43 uint32_t reserved_0a : 2, // [31:30] 44 src_link_id : 3, // [29:27] 45 data_offset : 12, // [26:15] 46 priority_valid : 1, // [14:14] 47 service_code : 9, // [13:5] 48 reo_destination_indication : 5; // [4:0] 49 #endif 50 }; 51 52 53 /* Description REO_DESTINATION_INDICATION 54 55 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 56 multiple buffers, this field will be valid in the Last 57 buffer used by the MSDU 58 59 The ID of the REO exit ring where the MSDU frame shall push 60 after (MPDU level) reordering has finished. 61 62 <enum 0 reo_destination_sw0> Reo will push the frame into 63 the REO2SW0 ring 64 <enum 1 reo_destination_sw1> Reo will push the frame into 65 the REO2SW1 ring 66 <enum 2 reo_destination_sw2> Reo will push the frame into 67 the REO2SW2 ring 68 <enum 3 reo_destination_sw3> Reo will push the frame into 69 the REO2SW3 ring 70 <enum 4 reo_destination_sw4> Reo will push the frame into 71 the REO2SW4 ring 72 <enum 5 reo_destination_release> Reo will push the frame 73 into the REO_release ring 74 <enum 6 reo_destination_fw> Reo will push the frame into 75 the REO2FW ring 76 <enum 7 reo_destination_sw5> Reo will push the frame into 77 the REO2SW5 ring (REO remaps this in chips without REO2SW5 78 ring, e.g. Pine) 79 <enum 8 reo_destination_sw6> Reo will push the frame into 80 the REO2SW6 ring (REO remaps this in chips without REO2SW6 81 ring, e.g. Pine) 82 <enum 9 reo_destination_sw7> Reo will push the frame into 83 the REO2SW7 ring (REO remaps this in chips without REO2SW7 84 ring) 85 <enum 10 reo_destination_sw8> Reo will push the frame into 86 the REO2SW8 ring (REO remaps this in chips without REO2SW8 87 ring) 88 <enum 11 reo_destination_11> REO remaps this 89 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 90 REO remaps this 91 <enum 14 reo_destination_14> REO remaps this 92 <enum 15 reo_destination_15> REO remaps this 93 <enum 16 reo_destination_16> REO remaps this 94 <enum 17 reo_destination_17> REO remaps this 95 <enum 18 reo_destination_18> REO remaps this 96 <enum 19 reo_destination_19> REO remaps this 97 <enum 20 reo_destination_20> REO remaps this 98 <enum 21 reo_destination_21> REO remaps this 99 <enum 22 reo_destination_22> REO remaps this 100 <enum 23 reo_destination_23> REO remaps this 101 <enum 24 reo_destination_24> REO remaps this 102 <enum 25 reo_destination_25> REO remaps this 103 <enum 26 reo_destination_26> REO remaps this 104 <enum 27 reo_destination_27> REO remaps this 105 <enum 28 reo_destination_28> REO remaps this 106 <enum 29 reo_destination_29> REO remaps this 107 <enum 30 reo_destination_30> REO remaps this 108 <enum 31 reo_destination_31> REO remaps this 109 110 <legal all> 111 */ 112 113 #define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 114 #define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB 0 115 #define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB 4 116 #define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f 117 118 119 /* Description SERVICE_CODE 120 121 Opaque service code between PPE and Wi-Fi 122 123 This field gets passed on by REO to PPE in the EDMA descriptor 124 ('REO_TO_PPE_RING'). 125 126 <legal all> 127 */ 128 129 #define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET 0x00000000 130 #define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB 5 131 #define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB 13 132 #define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK 0x00003fe0 133 134 135 /* Description PRIORITY_VALID 136 137 This field gets passed on by REO to PPE in the EDMA descriptor 138 ('REO_TO_PPE_RING'). 139 140 <legal all> 141 */ 142 143 #define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET 0x00000000 144 #define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB 14 145 #define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB 14 146 #define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK 0x00004000 147 148 149 /* Description DATA_OFFSET 150 151 The offset to Rx packet data within the buffer (including 152 Rx DMA offset programming and L3 header padding inserted 153 by Rx OLE). 154 155 This field gets passed on by REO to PPE in the EDMA descriptor 156 ('REO_TO_PPE_RING'). 157 158 <legal all> 159 */ 160 161 #define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET 0x00000000 162 #define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB 15 163 #define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB 26 164 #define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK 0x07ff8000 165 166 167 /* Description SRC_LINK_ID 168 169 Consumer: SW 170 Producer: RXDMA 171 172 Set to the link ID of the PMAC that received the frame 173 <legal all> 174 */ 175 176 #define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_OFFSET 0x00000000 177 #define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_LSB 27 178 #define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MSB 29 179 #define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MASK 0x38000000 180 181 182 /* Description RESERVED_0A 183 184 <legal 0> 185 */ 186 187 #define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET 0x00000000 188 #define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB 30 189 #define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB 31 190 #define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK 0xc0000000 191 192 193 194 #endif // RX_MSDU_EXT_DESC_INFO 195