1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_PPDU_END_USER_STATS_EXT_H_ 27 #define _RX_PPDU_END_USER_STATS_EXT_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "rx_rxpcu_classification_overview.h" 32 #define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 8 33 34 #define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS_EXT 4 35 36 37 struct rx_ppdu_end_user_stats_ext { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct rx_rxpcu_classification_overview rxpcu_classification_details; 40 uint32_t fcs_ok_bitmap_95_64 : 32; // [31:0] 41 uint32_t fcs_ok_bitmap_127_96 : 32; // [31:0] 42 uint32_t fcs_ok_bitmap_159_128 : 32; // [31:0] 43 uint32_t fcs_ok_bitmap_191_160 : 32; // [31:0] 44 uint32_t fcs_ok_bitmap_223_192 : 32; // [31:0] 45 uint32_t fcs_ok_bitmap_255_224 : 32; // [31:0] 46 uint32_t corrupted_due_to_fifo_delay : 1, // [0:0] 47 reserved_7a : 31; // [31:1] 48 #else 49 struct rx_rxpcu_classification_overview rxpcu_classification_details; 50 uint32_t fcs_ok_bitmap_95_64 : 32; // [31:0] 51 uint32_t fcs_ok_bitmap_127_96 : 32; // [31:0] 52 uint32_t fcs_ok_bitmap_159_128 : 32; // [31:0] 53 uint32_t fcs_ok_bitmap_191_160 : 32; // [31:0] 54 uint32_t fcs_ok_bitmap_223_192 : 32; // [31:0] 55 uint32_t fcs_ok_bitmap_255_224 : 32; // [31:0] 56 uint32_t reserved_7a : 31, // [31:1] 57 corrupted_due_to_fifo_delay : 1; // [0:0] 58 #endif 59 }; 60 61 62 /* Description RXPCU_CLASSIFICATION_DETAILS 63 64 Details related to what RXPCU classification types of MPDUs 65 have been received 66 */ 67 68 69 /* Description FILTER_PASS_MPDUS 70 71 When set, at least one Filter Pass MPDU has been received. 72 FCS might or might not have been passing. 73 74 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 75 this field is the "OR of all the users. 76 <legal all> 77 */ 78 79 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 80 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 81 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 82 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 83 84 85 /* Description FILTER_PASS_MPDUS_FCS_OK 86 87 When set, at least one Filter Pass MPDU has been received 88 that has a correct FCS. 89 90 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 91 this field is the "OR of all the users. 92 93 <legal all> 94 */ 95 96 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 97 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 98 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 99 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 100 101 102 /* Description MONITOR_DIRECT_MPDUS 103 104 When set, at least one Monitor Direct MPDU has been received. 105 FCS might or might not have been passing 106 107 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 108 this field is the "OR of all the users. 109 <legal all> 110 */ 111 112 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 113 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 114 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 115 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 116 117 118 /* Description MONITOR_DIRECT_MPDUS_FCS_OK 119 120 When set, at least one Monitor Direct MPDU has been received 121 that has a correct FCS. 122 123 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 124 this field is the "OR of all the users. 125 126 <legal all> 127 */ 128 129 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 130 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 131 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 132 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 133 134 135 /* Description MONITOR_OTHER_MPDUS 136 137 When set, at least one Monitor Direct MPDU has been received. 138 FCS might or might not have been passing. 139 140 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 141 this field is the "OR of all the users. 142 <legal all> 143 */ 144 145 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 146 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 147 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 148 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 149 150 151 /* Description MONITOR_OTHER_MPDUS_FCS_OK 152 153 When set, at least one Monitor Direct MPDU has been received 154 that has a correct FCS. 155 156 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 157 this field is the "OR of all the users. 158 <legal all> 159 */ 160 161 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 162 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 163 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 164 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 165 166 167 /* Description PHYRX_ABORT_RECEIVED 168 169 When set, PPDU reception was aborted by the PHY 170 <legal all> 171 */ 172 173 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 174 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 175 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 176 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 177 178 179 /* Description FILTER_PASS_MONITOR_OVRD_MPDUS 180 181 When set, at least one 'Filter Pass Monitor Override' MPDU 182 has been received. FCS might or might not have been passing. 183 184 185 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 186 this field is the "OR of all the users. 187 <legal all> 188 */ 189 190 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 191 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 192 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 193 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 194 195 196 /* Description FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK 197 198 When set, at least one 'Filter Pass Monitor Override' MPDU 199 has been received that has a correct FCS. 200 201 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 202 this field is the "OR of all the users. 203 204 <legal all> 205 */ 206 207 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 208 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 209 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 210 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 211 212 213 /* Description RESERVED_0 214 215 <legal 0> 216 */ 217 218 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 219 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 220 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 221 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 222 223 224 /* Description PHY_PPDU_ID 225 226 A ppdu counter value that PHY increments for every PPDU 227 received. The counter value wraps around 228 <legal all> 229 */ 230 231 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 232 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 233 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 234 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 235 236 237 /* Description FCS_OK_BITMAP_95_64 238 239 Bitmap indicates in order of received MPDUs, which MPDUs 240 had an passing FCS or had an error. 241 1: FCS OK 242 0: FCS error 243 <legal all> 244 */ 245 246 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_OFFSET 0x0000000000000000 247 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_LSB 32 248 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MSB 63 249 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MASK 0xffffffff00000000 250 251 252 /* Description FCS_OK_BITMAP_127_96 253 254 Bitmap indicates in order of received MPDUs, which MPDUs 255 had an passing FCS or had an error. 256 1: FCS OK 257 0: FCS error 258 <legal all> 259 */ 260 261 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_OFFSET 0x0000000000000008 262 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_LSB 0 263 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MSB 31 264 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MASK 0x00000000ffffffff 265 266 267 /* Description FCS_OK_BITMAP_159_128 268 269 Bitmap indicates in order of received MPDUs, which MPDUs 270 had an passing FCS or had an error. 271 1: FCS OK 272 0: FCS error 273 <legal all> 274 */ 275 276 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_OFFSET 0x0000000000000008 277 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_LSB 32 278 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MSB 63 279 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MASK 0xffffffff00000000 280 281 282 /* Description FCS_OK_BITMAP_191_160 283 284 Bitmap indicates in order of received MPDUs, which MPDUs 285 had an passing FCS or had an error. 286 1: FCS OK 287 0: FCS error 288 <legal all> 289 */ 290 291 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_OFFSET 0x0000000000000010 292 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_LSB 0 293 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MSB 31 294 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MASK 0x00000000ffffffff 295 296 297 /* Description FCS_OK_BITMAP_223_192 298 299 Bitmap indicates in order of received MPDUs, which MPDUs 300 had an passing FCS or had an error. 301 1: FCS OK 302 0: FCS error 303 <legal all> 304 */ 305 306 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_OFFSET 0x0000000000000010 307 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_LSB 32 308 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MSB 63 309 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MASK 0xffffffff00000000 310 311 312 /* Description FCS_OK_BITMAP_255_224 313 314 Bitmap indicates in order of received MPDUs, which MPDUs 315 had an passing FCS or had an error. 316 1: FCS OK 317 0: FCS error 318 <legal all> 319 */ 320 321 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_OFFSET 0x0000000000000018 322 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_LSB 0 323 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MSB 31 324 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MASK 0x00000000ffffffff 325 326 327 /* Description CORRUPTED_DUE_TO_FIFO_DELAY 328 329 Set if Rx PCU avoided a hang due to SFM delays by writing 330 a corrupted 'RX_PPDU_END_USER_STATS*' and/or 'RX_PPDU_END.' 331 332 */ 333 334 #define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000018 335 #define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 336 #define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 337 #define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 338 339 340 /* Description RESERVED_7A 341 342 <legal 0> 343 */ 344 345 #define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_OFFSET 0x0000000000000018 346 #define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_LSB 33 347 #define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MSB 63 348 #define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MASK 0xfffffffe00000000 349 350 351 352 #endif // RX_PPDU_END_USER_STATS_EXT 353