1*5113495bSYour Name 2*5113495bSYour Name /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name 18*5113495bSYour Name 19*5113495bSYour Name 20*5113495bSYour Name 21*5113495bSYour Name 22*5113495bSYour Name 23*5113495bSYour Name 24*5113495bSYour Name 25*5113495bSYour Name 26*5113495bSYour Name #ifndef _RX_PPDU_START_H_ 27*5113495bSYour Name #define _RX_PPDU_START_H_ 28*5113495bSYour Name #if !defined(__ASSEMBLER__) 29*5113495bSYour Name #endif 30*5113495bSYour Name 31*5113495bSYour Name #define NUM_OF_DWORDS_RX_PPDU_START 6 32*5113495bSYour Name 33*5113495bSYour Name #define NUM_OF_QWORDS_RX_PPDU_START 3 34*5113495bSYour Name 35*5113495bSYour Name 36*5113495bSYour Name struct rx_ppdu_start { 37*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38*5113495bSYour Name uint32_t phy_ppdu_id : 16, // [15:0] 39*5113495bSYour Name preamble_time_to_rxframe : 8, // [23:16] 40*5113495bSYour Name reserved_0a : 8; // [31:24] 41*5113495bSYour Name uint32_t sw_phy_meta_data : 32; // [31:0] 42*5113495bSYour Name uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] 43*5113495bSYour Name uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] 44*5113495bSYour Name uint32_t rxframe_assert_timestamp : 32; // [31:0] 45*5113495bSYour Name uint32_t tlv64_padding : 32; // [31:0] 46*5113495bSYour Name #else 47*5113495bSYour Name uint32_t reserved_0a : 8, // [31:24] 48*5113495bSYour Name preamble_time_to_rxframe : 8, // [23:16] 49*5113495bSYour Name phy_ppdu_id : 16; // [15:0] 50*5113495bSYour Name uint32_t sw_phy_meta_data : 32; // [31:0] 51*5113495bSYour Name uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] 52*5113495bSYour Name uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] 53*5113495bSYour Name uint32_t rxframe_assert_timestamp : 32; // [31:0] 54*5113495bSYour Name uint32_t tlv64_padding : 32; // [31:0] 55*5113495bSYour Name #endif 56*5113495bSYour Name }; 57*5113495bSYour Name 58*5113495bSYour Name 59*5113495bSYour Name /* Description PHY_PPDU_ID 60*5113495bSYour Name 61*5113495bSYour Name A ppdu counter value that PHY increments for every PPDU 62*5113495bSYour Name received. The counter value wraps around 63*5113495bSYour Name <legal all> 64*5113495bSYour Name */ 65*5113495bSYour Name 66*5113495bSYour Name #define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 67*5113495bSYour Name #define RX_PPDU_START_PHY_PPDU_ID_LSB 0 68*5113495bSYour Name #define RX_PPDU_START_PHY_PPDU_ID_MSB 15 69*5113495bSYour Name #define RX_PPDU_START_PHY_PPDU_ID_MASK 0x000000000000ffff 70*5113495bSYour Name 71*5113495bSYour Name 72*5113495bSYour Name /* Description PREAMBLE_TIME_TO_RXFRAME 73*5113495bSYour Name 74*5113495bSYour Name The amount of time (in us) of the frame being put on the 75*5113495bSYour Name medium, and PHY raising rx_frame 76*5113495bSYour Name 77*5113495bSYour Name From 'PHYRX_RSSI_LEGACY. Preamble_time_to_rx_frame' 78*5113495bSYour Name 79*5113495bSYour Name <legal all> 80*5113495bSYour Name */ 81*5113495bSYour Name 82*5113495bSYour Name #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000000 83*5113495bSYour Name #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16 84*5113495bSYour Name #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23 85*5113495bSYour Name #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x0000000000ff0000 86*5113495bSYour Name 87*5113495bSYour Name 88*5113495bSYour Name /* Description RESERVED_0A 89*5113495bSYour Name 90*5113495bSYour Name Reserved 91*5113495bSYour Name <legal 0> 92*5113495bSYour Name */ 93*5113495bSYour Name 94*5113495bSYour Name #define RX_PPDU_START_RESERVED_0A_OFFSET 0x0000000000000000 95*5113495bSYour Name #define RX_PPDU_START_RESERVED_0A_LSB 24 96*5113495bSYour Name #define RX_PPDU_START_RESERVED_0A_MSB 31 97*5113495bSYour Name #define RX_PPDU_START_RESERVED_0A_MASK 0x00000000ff000000 98*5113495bSYour Name 99*5113495bSYour Name 100*5113495bSYour Name /* Description SW_PHY_META_DATA 101*5113495bSYour Name 102*5113495bSYour Name SW programmed Meta data provided by the PHY. 103*5113495bSYour Name 104*5113495bSYour Name Can be used for SW to indicate the channel the device is 105*5113495bSYour Name on. 106*5113495bSYour Name 107*5113495bSYour Name From 'PHYRX_RSSI_LEGACY.Sw_phy_meta_data' 108*5113495bSYour Name */ 109*5113495bSYour Name 110*5113495bSYour Name #define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000000 111*5113495bSYour Name #define RX_PPDU_START_SW_PHY_META_DATA_LSB 32 112*5113495bSYour Name #define RX_PPDU_START_SW_PHY_META_DATA_MSB 63 113*5113495bSYour Name #define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff00000000 114*5113495bSYour Name 115*5113495bSYour Name 116*5113495bSYour Name /* Description PPDU_START_TIMESTAMP_31_0 117*5113495bSYour Name 118*5113495bSYour Name Timestamp that indicates when the PPDU that contained this 119*5113495bSYour Name MPDU started on the medium, lower 32 bits. 120*5113495bSYour Name 121*5113495bSYour Name The timestamp is captured by the PHY and given to the MAC 122*5113495bSYour Name in 'PHYRX_RSSI_LEGACY.ppdu_start_timestamp_*.' 123*5113495bSYour Name <legal all> 124*5113495bSYour Name */ 125*5113495bSYour Name 126*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 127*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 128*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 129*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff 130*5113495bSYour Name 131*5113495bSYour Name 132*5113495bSYour Name /* Description PPDU_START_TIMESTAMP_63_32 133*5113495bSYour Name 134*5113495bSYour Name Timestamp that indicates when the PPDU that contained this 135*5113495bSYour Name MPDU started on the medium, upper 32 bits. 136*5113495bSYour Name 137*5113495bSYour Name The timestamp is captured by the PHY and given to the MAC 138*5113495bSYour Name in 'PHYRX_RSSI_LEGACY.ppdu_start_timestamp_*.' 139*5113495bSYour Name <legal all> 140*5113495bSYour Name */ 141*5113495bSYour Name 142*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 143*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 144*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 145*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 146*5113495bSYour Name 147*5113495bSYour Name 148*5113495bSYour Name /* Description RXFRAME_ASSERT_TIMESTAMP 149*5113495bSYour Name 150*5113495bSYour Name MAC timer Timestamp that indicates when PHY asserted the 151*5113495bSYour Name 'rx_frame' signal for the reception of this PPDU 152*5113495bSYour Name <legal all> 153*5113495bSYour Name */ 154*5113495bSYour Name 155*5113495bSYour Name #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x0000000000000010 156*5113495bSYour Name #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0 157*5113495bSYour Name #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31 158*5113495bSYour Name #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0x00000000ffffffff 159*5113495bSYour Name 160*5113495bSYour Name 161*5113495bSYour Name /* Description TLV64_PADDING 162*5113495bSYour Name 163*5113495bSYour Name Automatic DWORD padding inserted while converting TLV32 164*5113495bSYour Name to TLV64 for 64 bit ARCH 165*5113495bSYour Name <legal 0> 166*5113495bSYour Name */ 167*5113495bSYour Name 168*5113495bSYour Name #define RX_PPDU_START_TLV64_PADDING_OFFSET 0x0000000000000010 169*5113495bSYour Name #define RX_PPDU_START_TLV64_PADDING_LSB 32 170*5113495bSYour Name #define RX_PPDU_START_TLV64_PADDING_MSB 63 171*5113495bSYour Name #define RX_PPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 172*5113495bSYour Name 173*5113495bSYour Name 174*5113495bSYour Name 175*5113495bSYour Name #endif // RX_PPDU_START 176