1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_PPDU_START_H_ 27 #define _RX_PPDU_START_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_RX_PPDU_START 6 32 33 #define NUM_OF_QWORDS_RX_PPDU_START 3 34 35 36 struct rx_ppdu_start { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t phy_ppdu_id : 16, // [15:0] 39 preamble_time_to_rxframe : 8, // [23:16] 40 reserved_0a : 8; // [31:24] 41 uint32_t sw_phy_meta_data : 32; // [31:0] 42 uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] 43 uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] 44 uint32_t rxframe_assert_timestamp : 32; // [31:0] 45 uint32_t tlv64_padding : 32; // [31:0] 46 #else 47 uint32_t reserved_0a : 8, // [31:24] 48 preamble_time_to_rxframe : 8, // [23:16] 49 phy_ppdu_id : 16; // [15:0] 50 uint32_t sw_phy_meta_data : 32; // [31:0] 51 uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] 52 uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] 53 uint32_t rxframe_assert_timestamp : 32; // [31:0] 54 uint32_t tlv64_padding : 32; // [31:0] 55 #endif 56 }; 57 58 59 /* Description PHY_PPDU_ID 60 61 A ppdu counter value that PHY increments for every PPDU 62 received. The counter value wraps around 63 <legal all> 64 */ 65 66 #define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 67 #define RX_PPDU_START_PHY_PPDU_ID_LSB 0 68 #define RX_PPDU_START_PHY_PPDU_ID_MSB 15 69 #define RX_PPDU_START_PHY_PPDU_ID_MASK 0x000000000000ffff 70 71 72 /* Description PREAMBLE_TIME_TO_RXFRAME 73 74 The amount of time (in us) of the frame being put on the 75 medium, and PHY raising rx_frame 76 77 From 'PHYRX_RSSI_LEGACY. Preamble_time_to_rx_frame' 78 79 <legal all> 80 */ 81 82 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000000 83 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16 84 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23 85 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x0000000000ff0000 86 87 88 /* Description RESERVED_0A 89 90 Reserved 91 <legal 0> 92 */ 93 94 #define RX_PPDU_START_RESERVED_0A_OFFSET 0x0000000000000000 95 #define RX_PPDU_START_RESERVED_0A_LSB 24 96 #define RX_PPDU_START_RESERVED_0A_MSB 31 97 #define RX_PPDU_START_RESERVED_0A_MASK 0x00000000ff000000 98 99 100 /* Description SW_PHY_META_DATA 101 102 SW programmed Meta data provided by the PHY. 103 104 Can be used for SW to indicate the channel the device is 105 on. 106 107 From 'PHYRX_RSSI_LEGACY.Sw_phy_meta_data' 108 */ 109 110 #define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000000 111 #define RX_PPDU_START_SW_PHY_META_DATA_LSB 32 112 #define RX_PPDU_START_SW_PHY_META_DATA_MSB 63 113 #define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff00000000 114 115 116 /* Description PPDU_START_TIMESTAMP_31_0 117 118 Timestamp that indicates when the PPDU that contained this 119 MPDU started on the medium, lower 32 bits. 120 121 The timestamp is captured by the PHY and given to the MAC 122 in 'PHYRX_RSSI_LEGACY.ppdu_start_timestamp_*.' 123 <legal all> 124 */ 125 126 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 127 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 128 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 129 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff 130 131 132 /* Description PPDU_START_TIMESTAMP_63_32 133 134 Timestamp that indicates when the PPDU that contained this 135 MPDU started on the medium, upper 32 bits. 136 137 The timestamp is captured by the PHY and given to the MAC 138 in 'PHYRX_RSSI_LEGACY.ppdu_start_timestamp_*.' 139 <legal all> 140 */ 141 142 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 143 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 144 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 145 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 146 147 148 /* Description RXFRAME_ASSERT_TIMESTAMP 149 150 MAC timer Timestamp that indicates when PHY asserted the 151 'rx_frame' signal for the reception of this PPDU 152 <legal all> 153 */ 154 155 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x0000000000000010 156 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0 157 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31 158 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0x00000000ffffffff 159 160 161 /* Description TLV64_PADDING 162 163 Automatic DWORD padding inserted while converting TLV32 164 to TLV64 for 64 bit ARCH 165 <legal 0> 166 */ 167 168 #define RX_PPDU_START_TLV64_PADDING_OFFSET 0x0000000000000010 169 #define RX_PPDU_START_TLV64_PADDING_LSB 32 170 #define RX_PPDU_START_TLV64_PADDING_MSB 63 171 #define RX_PPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 172 173 174 175 #endif // RX_PPDU_START 176