1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _RX_REO_QUEUE_H_ 19 #define _RX_REO_QUEUE_H_ 20 #if !defined(__ASSEMBLER__) 21 #endif 22 23 #include "uniform_descriptor_header.h" 24 #define NUM_OF_DWORDS_RX_REO_QUEUE 32 25 26 27 struct rx_reo_queue { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 struct uniform_descriptor_header descriptor_header; 30 uint32_t receive_queue_number : 16, // [15:0] 31 reserved_1b : 16; // [31:16] 32 uint32_t vld : 1, // [0:0] 33 associated_link_descriptor_counter : 2, // [2:1] 34 disable_duplicate_detection : 1, // [3:3] 35 soft_reorder_enable : 1, // [4:4] 36 ac : 2, // [6:5] 37 bar : 1, // [7:7] 38 rty : 1, // [8:8] 39 chk_2k_mode : 1, // [9:9] 40 oor_mode : 1, // [10:10] 41 ba_window_size : 10, // [20:11] 42 pn_check_needed : 1, // [21:21] 43 pn_shall_be_even : 1, // [22:22] 44 pn_shall_be_uneven : 1, // [23:23] 45 pn_handling_enable : 1, // [24:24] 46 pn_size : 2, // [26:25] 47 ignore_ampdu_flag : 1, // [27:27] 48 reserved_2b : 4; // [31:28] 49 uint32_t svld : 1, // [0:0] 50 ssn : 12, // [12:1] 51 current_index : 10, // [22:13] 52 seq_2k_error_detected_flag : 1, // [23:23] 53 pn_error_detected_flag : 1, // [24:24] 54 reserved_3a : 6, // [30:25] 55 pn_valid : 1; // [31:31] 56 uint32_t pn_31_0 : 32; // [31:0] 57 uint32_t pn_63_32 : 32; // [31:0] 58 uint32_t pn_95_64 : 32; // [31:0] 59 uint32_t pn_127_96 : 32; // [31:0] 60 uint32_t last_rx_enqueue_timestamp : 32; // [31:0] 61 uint32_t last_rx_dequeue_timestamp : 32; // [31:0] 62 uint32_t ptr_to_next_aging_queue_31_0 : 32; // [31:0] 63 uint32_t ptr_to_next_aging_queue_39_32 : 8, // [7:0] 64 reserved_11a : 24; // [31:8] 65 uint32_t ptr_to_previous_aging_queue_31_0 : 32; // [31:0] 66 uint32_t ptr_to_previous_aging_queue_39_32 : 8, // [7:0] 67 statistics_counter_index : 6, // [13:8] 68 reserved_13a : 18; // [31:14] 69 uint32_t rx_bitmap_31_0 : 32; // [31:0] 70 uint32_t rx_bitmap_63_32 : 32; // [31:0] 71 uint32_t rx_bitmap_95_64 : 32; // [31:0] 72 uint32_t rx_bitmap_127_96 : 32; // [31:0] 73 uint32_t rx_bitmap_159_128 : 32; // [31:0] 74 uint32_t rx_bitmap_191_160 : 32; // [31:0] 75 uint32_t rx_bitmap_223_192 : 32; // [31:0] 76 uint32_t rx_bitmap_255_224 : 32; // [31:0] 77 uint32_t rx_bitmap_287_256 : 32; // [31:0] 78 uint32_t current_mpdu_count : 7, // [6:0] 79 current_msdu_count : 25; // [31:7] 80 uint32_t last_sn_reg_index : 4, // [3:0] 81 timeout_count : 6, // [9:4] 82 forward_due_to_bar_count : 6, // [15:10] 83 duplicate_count : 16; // [31:16] 84 uint32_t frames_in_order_count : 24, // [23:0] 85 bar_received_count : 8; // [31:24] 86 uint32_t mpdu_frames_processed_count : 32; // [31:0] 87 uint32_t msdu_frames_processed_count : 32; // [31:0] 88 uint32_t total_processed_byte_count : 32; // [31:0] 89 uint32_t late_receive_mpdu_count : 12, // [11:0] 90 window_jump_2k : 4, // [15:12] 91 hole_count : 16; // [31:16] 92 uint32_t aging_drop_mpdu_count : 16, // [15:0] 93 aging_drop_interval : 8, // [23:16] 94 reserved_30 : 8; // [31:24] 95 uint32_t reserved_31 : 32; // [31:0] 96 #else 97 struct uniform_descriptor_header descriptor_header; 98 uint32_t reserved_1b : 16, // [31:16] 99 receive_queue_number : 16; // [15:0] 100 uint32_t reserved_2b : 4, // [31:28] 101 ignore_ampdu_flag : 1, // [27:27] 102 pn_size : 2, // [26:25] 103 pn_handling_enable : 1, // [24:24] 104 pn_shall_be_uneven : 1, // [23:23] 105 pn_shall_be_even : 1, // [22:22] 106 pn_check_needed : 1, // [21:21] 107 ba_window_size : 10, // [20:11] 108 oor_mode : 1, // [10:10] 109 chk_2k_mode : 1, // [9:9] 110 rty : 1, // [8:8] 111 bar : 1, // [7:7] 112 ac : 2, // [6:5] 113 soft_reorder_enable : 1, // [4:4] 114 disable_duplicate_detection : 1, // [3:3] 115 associated_link_descriptor_counter : 2, // [2:1] 116 vld : 1; // [0:0] 117 uint32_t pn_valid : 1, // [31:31] 118 reserved_3a : 6, // [30:25] 119 pn_error_detected_flag : 1, // [24:24] 120 seq_2k_error_detected_flag : 1, // [23:23] 121 current_index : 10, // [22:13] 122 ssn : 12, // [12:1] 123 svld : 1; // [0:0] 124 uint32_t pn_31_0 : 32; // [31:0] 125 uint32_t pn_63_32 : 32; // [31:0] 126 uint32_t pn_95_64 : 32; // [31:0] 127 uint32_t pn_127_96 : 32; // [31:0] 128 uint32_t last_rx_enqueue_timestamp : 32; // [31:0] 129 uint32_t last_rx_dequeue_timestamp : 32; // [31:0] 130 uint32_t ptr_to_next_aging_queue_31_0 : 32; // [31:0] 131 uint32_t reserved_11a : 24, // [31:8] 132 ptr_to_next_aging_queue_39_32 : 8; // [7:0] 133 uint32_t ptr_to_previous_aging_queue_31_0 : 32; // [31:0] 134 uint32_t reserved_13a : 18, // [31:14] 135 statistics_counter_index : 6, // [13:8] 136 ptr_to_previous_aging_queue_39_32 : 8; // [7:0] 137 uint32_t rx_bitmap_31_0 : 32; // [31:0] 138 uint32_t rx_bitmap_63_32 : 32; // [31:0] 139 uint32_t rx_bitmap_95_64 : 32; // [31:0] 140 uint32_t rx_bitmap_127_96 : 32; // [31:0] 141 uint32_t rx_bitmap_159_128 : 32; // [31:0] 142 uint32_t rx_bitmap_191_160 : 32; // [31:0] 143 uint32_t rx_bitmap_223_192 : 32; // [31:0] 144 uint32_t rx_bitmap_255_224 : 32; // [31:0] 145 uint32_t rx_bitmap_287_256 : 32; // [31:0] 146 uint32_t current_msdu_count : 25, // [31:7] 147 current_mpdu_count : 7; // [6:0] 148 uint32_t duplicate_count : 16, // [31:16] 149 forward_due_to_bar_count : 6, // [15:10] 150 timeout_count : 6, // [9:4] 151 last_sn_reg_index : 4; // [3:0] 152 uint32_t bar_received_count : 8, // [31:24] 153 frames_in_order_count : 24; // [23:0] 154 uint32_t mpdu_frames_processed_count : 32; // [31:0] 155 uint32_t msdu_frames_processed_count : 32; // [31:0] 156 uint32_t total_processed_byte_count : 32; // [31:0] 157 uint32_t hole_count : 16, // [31:16] 158 window_jump_2k : 4, // [15:12] 159 late_receive_mpdu_count : 12; // [11:0] 160 uint32_t reserved_30 : 8, // [31:24] 161 aging_drop_interval : 8, // [23:16] 162 aging_drop_mpdu_count : 16; // [15:0] 163 uint32_t reserved_31 : 32; // [31:0] 164 #endif 165 }; 166 167 168 /* Description DESCRIPTOR_HEADER 169 170 Details about which module owns this struct. 171 Note that sub field "Buffer_type" shall be set to "Receive_REO_queue_descriptor" 172 173 */ 174 175 176 /* Description OWNER 177 178 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 179 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 180 181 The owner of this data structure: 182 <enum 0 WBM_owned> Buffer Manager currently owns this data 183 structure. 184 <enum 1 SW_OR_FW_owned> Software of FW currently owns this 185 data structure. 186 <enum 2 TQM_owned> Transmit Queue Manager currently owns 187 this data structure. 188 <enum 3 RXDMA_owned> Receive DMA currently owns this data 189 structure. 190 <enum 4 REO_owned> Reorder currently owns this data structure. 191 192 <enum 5 SWITCH_owned> SWITCH currently owns this data structure. 193 194 195 <legal 0-5> 196 */ 197 198 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 199 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_LSB 0 200 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MSB 3 201 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 202 203 204 /* Description BUFFER_TYPE 205 206 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 207 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 208 209 Field describing what contents format is of this descriptor 210 211 212 <enum 0 Transmit_MSDU_Link_descriptor> 213 <enum 1 Transmit_MPDU_Link_descriptor> 214 <enum 2 Transmit_MPDU_Queue_head_descriptor> 215 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 216 <enum 4 Transmit_flow_descriptor> 217 <enum 5 Transmit_buffer> NOT TO BE USED: 218 219 <enum 6 Receive_MSDU_Link_descriptor> 220 <enum 7 Receive_MPDU_Link_descriptor> 221 <enum 8 Receive_REO_queue_descriptor> 222 <enum 9 Receive_REO_queue_1k_descriptor> 223 <enum 10 Receive_REO_queue_ext_descriptor> 224 225 <enum 11 Receive_buffer> 226 227 <enum 12 Idle_link_list_entry> 228 229 <legal 0-12> 230 */ 231 232 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 233 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 234 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 235 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 236 237 238 /* Description TX_MPDU_QUEUE_NUMBER 239 240 Consumer: TQM/Debug 241 Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) 242 243 Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor 244 245 246 Indicates the MPDU queue ID to which this MPDU descriptor 247 belongs 248 Used for tracking and debugging 249 250 Hamilton and Waikiki used bits [19:0] of word 1 of 'TX_MPDU_LINK,' 251 word 16 of 'TX_MPDU_QUEUE_HEAD' and word 1 of 'TX_MPDU_QUEUE_EXT' 252 for this. 253 <legal all> 254 */ 255 256 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 257 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 258 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 259 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 260 261 262 /* Description RESERVED_0A 263 264 <legal 0> 265 */ 266 267 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 268 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 269 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 270 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 271 272 273 /* Description RECEIVE_QUEUE_NUMBER 274 275 Indicates the MPDU queue ID to which this MPDU link descriptor 276 belongs 277 Used for tracking and debugging 278 <legal all> 279 */ 280 281 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 282 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 0 283 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 15 284 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff 285 286 287 /* Description RESERVED_1B 288 289 <legal 0> 290 */ 291 292 #define RX_REO_QUEUE_RESERVED_1B_OFFSET 0x00000004 293 #define RX_REO_QUEUE_RESERVED_1B_LSB 16 294 #define RX_REO_QUEUE_RESERVED_1B_MSB 31 295 #define RX_REO_QUEUE_RESERVED_1B_MASK 0xffff0000 296 297 298 /* Description VLD 299 300 Valid bit indicating a session is established and the queue 301 descriptor is valid(Filled by SW) 302 <legal all> 303 */ 304 305 #define RX_REO_QUEUE_VLD_OFFSET 0x00000008 306 #define RX_REO_QUEUE_VLD_LSB 0 307 #define RX_REO_QUEUE_VLD_MSB 0 308 #define RX_REO_QUEUE_VLD_MASK 0x00000001 309 310 311 /* Description ASSOCIATED_LINK_DESCRIPTOR_COUNTER 312 313 Indicates which of the 3 link descriptor counters shall 314 be incremented or decremented when link descriptors are 315 added or removed from this flow queue. 316 MSDU link descriptors related with MPDUs stored in the re-order 317 buffer shall also be included in this count. 318 319 <legal 0-2> 320 */ 321 322 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 323 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 324 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 2 325 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 326 327 328 /* Description DISABLE_DUPLICATE_DETECTION 329 330 When set, do not perform any duplicate detection. 331 332 <legal all> 333 */ 334 335 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 336 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 3 337 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 3 338 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 339 340 341 /* Description SOFT_REORDER_ENABLE 342 343 When set, REO has been instructed to not perform the actual 344 re-ordering of frames for this queue, but just to insert 345 the reorder opcodes. 346 347 Note that this implies that REO is also not going to perform 348 any MSDU level operations, and the entire MPDU (and thus 349 pointer to the MSDU link descriptor) will be pushed to 350 a destination ring that SW has programmed in a SW programmable 351 configuration register in REO 352 353 <legal all> 354 */ 355 356 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 357 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 4 358 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 4 359 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x00000010 360 361 362 /* Description AC 363 364 Indicates which access category the queue descriptor belongs 365 to(filled by SW) 366 <legal all> 367 */ 368 369 #define RX_REO_QUEUE_AC_OFFSET 0x00000008 370 #define RX_REO_QUEUE_AC_LSB 5 371 #define RX_REO_QUEUE_AC_MSB 6 372 #define RX_REO_QUEUE_AC_MASK 0x00000060 373 374 375 /* Description BAR 376 377 Indicates if BAR has been received (mostly used for debug 378 purpose and this is filled by REO) 379 <legal all> 380 */ 381 382 #define RX_REO_QUEUE_BAR_OFFSET 0x00000008 383 #define RX_REO_QUEUE_BAR_LSB 7 384 #define RX_REO_QUEUE_BAR_MSB 7 385 #define RX_REO_QUEUE_BAR_MASK 0x00000080 386 387 388 /* Description RTY 389 390 Retry bit is checked if this bit is set. 391 <legal all> 392 */ 393 394 #define RX_REO_QUEUE_RTY_OFFSET 0x00000008 395 #define RX_REO_QUEUE_RTY_LSB 8 396 #define RX_REO_QUEUE_RTY_MSB 8 397 #define RX_REO_QUEUE_RTY_MASK 0x00000100 398 399 400 /* Description CHK_2K_MODE 401 402 Indicates what type of operation is expected from Reo when 403 the received frame SN falls within the 2K window 404 405 See REO MLD document for programming details. 406 <legal all> 407 */ 408 409 #define RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x00000008 410 #define RX_REO_QUEUE_CHK_2K_MODE_LSB 9 411 #define RX_REO_QUEUE_CHK_2K_MODE_MSB 9 412 #define RX_REO_QUEUE_CHK_2K_MODE_MASK 0x00000200 413 414 415 /* Description OOR_MODE 416 417 Out of Order mode: 418 Indicates what type of operation is expected when the received 419 frame falls within the OOR window. 420 421 See REO MLD document for programming details. 422 <legal all> 423 */ 424 425 #define RX_REO_QUEUE_OOR_MODE_OFFSET 0x00000008 426 #define RX_REO_QUEUE_OOR_MODE_LSB 10 427 #define RX_REO_QUEUE_OOR_MODE_MSB 10 428 #define RX_REO_QUEUE_OOR_MODE_MASK 0x00000400 429 430 431 /* Description BA_WINDOW_SIZE 432 433 Indicates the negotiated (window size + 1). 434 It can go up to Max of 256bits. 435 436 A value 255 means 256 bitmap, 63 means 64 bitmap, 0 (means 437 non-BA session, with window size of 0). The 3 values here 438 are the main values validated, but other values should 439 work as well. 440 441 A value 1023 means 1024 bitmap, 511 means 512 bitmap. The 442 2 values here are the main values validated for 1k-bitmap 443 support, but other values should work as well. 444 445 A BA window size of 0 (=> one frame entry bitmap), means 446 that there is NO RX_REO_QUEUE_EXT descriptor following 447 this RX_REO_QUEUE STRUCT in memory 448 449 A BA window size of 1 - 105 means that there is 1 RX_REO_QUEUE_EXT 450 descriptor directly following this RX_REO_QUEUE STRUCT 451 in memory. 452 453 A BA window size of 106 - 210 means that there are 2 RX_REO_QUEUE_EXT 454 descriptors directly following this RX_REO_QUEUE STRUCT 455 in memory 456 457 A BA window size of 211 - 256 means that there are 3 RX_REO_QUEUE_EXT 458 descriptors directly following this RX_REO_QUEUE STRUCT 459 in memory 460 461 A BA window size of 257 - 315 means that there is one RX_REO_QUEUE_1K 462 descriptor followed by 3 RX_REO_QUEUE_EXT descriptors directly 463 following this RX_REO_QUEUE STRUCT in memory 464 465 A BA window size of 316 - 420 means that there is one RX_REO_QUEUE_1K 466 descriptor followed by 4 RX_REO_QUEUE_EXT descriptors directly 467 following this RX_REO_QUEUE STRUCT in memory 468 ... 469 A BA window size of 946 - 1024 means that there is one RX_REO_QUEUE_1K 470 descriptor followed by 10 RX_REO_QUEUE_EXT descriptors 471 directly following this RX_REO_QUEUE STRUCT in memory 472 473 TODO: Should the above text use '255' and '1023' instead 474 of '256' and '1024'? 475 <legal 0 - 1023> 476 */ 477 478 #define RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x00000008 479 #define RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 11 480 #define RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 20 481 #define RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x001ff800 482 483 484 /* Description PN_CHECK_NEEDED 485 486 When set, REO shall perform the PN increment check 487 <legal all> 488 */ 489 490 #define RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x00000008 491 #define RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 21 492 #define RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 21 493 #define RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x00200000 494 495 496 /* Description PN_SHALL_BE_EVEN 497 498 Field only valid when 'pn_check_needed' is set. 499 500 When set, REO shall confirm that the received PN number 501 is not only incremented, but also always an even number 502 <legal all> 503 */ 504 505 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 506 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 22 507 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 22 508 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x00400000 509 510 511 /* Description PN_SHALL_BE_UNEVEN 512 513 Field only valid when 'pn_check_needed' is set. 514 515 When set, REO shall confirm that the received PN number 516 is not only incremented, but also always an uneven number 517 518 <legal all> 519 */ 520 521 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 522 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 23 523 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 23 524 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x00800000 525 526 527 /* Description PN_HANDLING_ENABLE 528 529 Field only valid when 'pn_check_needed' is set. 530 531 When set, and REO detected a PN error, HW shall set the 'pn_error_detected_flag'. 532 533 <legal all> 534 */ 535 536 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x00000008 537 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 24 538 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 24 539 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x01000000 540 541 542 /* Description PN_SIZE 543 544 Size of the PN field check. 545 Needed for wrap around handling... 546 547 <enum 0 pn_size_24> 548 <enum 1 pn_size_48> 549 <enum 2 pn_size_128> 550 551 <legal 0-2> 552 */ 553 554 #define RX_REO_QUEUE_PN_SIZE_OFFSET 0x00000008 555 #define RX_REO_QUEUE_PN_SIZE_LSB 25 556 #define RX_REO_QUEUE_PN_SIZE_MSB 26 557 #define RX_REO_QUEUE_PN_SIZE_MASK 0x06000000 558 559 560 /* Description IGNORE_AMPDU_FLAG 561 562 When set, REO shall ignore the ampdu_flag on the entrance 563 descriptor for this queue. 564 <legal all> 565 */ 566 567 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 568 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 27 569 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 27 570 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x08000000 571 572 573 /* Description RESERVED_2B 574 575 <legal 0> 576 */ 577 578 #define RX_REO_QUEUE_RESERVED_2B_OFFSET 0x00000008 579 #define RX_REO_QUEUE_RESERVED_2B_LSB 28 580 #define RX_REO_QUEUE_RESERVED_2B_MSB 31 581 #define RX_REO_QUEUE_RESERVED_2B_MASK 0xf0000000 582 583 584 /* Description SVLD 585 586 Sequence number in next field is valid one. It can be filled 587 by SW if the want to fill in the any negotiated SSN, otherwise 588 REO will fill the sequence number of first received packet 589 and set this bit to 1. 590 <legal all> 591 */ 592 593 #define RX_REO_QUEUE_SVLD_OFFSET 0x0000000c 594 #define RX_REO_QUEUE_SVLD_LSB 0 595 #define RX_REO_QUEUE_SVLD_MSB 0 596 #define RX_REO_QUEUE_SVLD_MASK 0x00000001 597 598 599 /* Description SSN 600 601 Starting Sequence number of the session, this changes whenever 602 window moves. (can be filled by SW then maintained by REO) 603 604 <legal all> 605 */ 606 607 #define RX_REO_QUEUE_SSN_OFFSET 0x0000000c 608 #define RX_REO_QUEUE_SSN_LSB 1 609 #define RX_REO_QUEUE_SSN_MSB 12 610 #define RX_REO_QUEUE_SSN_MASK 0x00001ffe 611 612 613 /* Description CURRENT_INDEX 614 615 Points to last forwarded packet 616 <legal all> 617 */ 618 619 #define RX_REO_QUEUE_CURRENT_INDEX_OFFSET 0x0000000c 620 #define RX_REO_QUEUE_CURRENT_INDEX_LSB 13 621 #define RX_REO_QUEUE_CURRENT_INDEX_MSB 22 622 #define RX_REO_QUEUE_CURRENT_INDEX_MASK 0x007fe000 623 624 625 /* Description SEQ_2K_ERROR_DETECTED_FLAG 626 627 Set by REO, can only be cleared by SW 628 629 When set, REO has detected a 2k error jump in the sequence 630 number and from that moment forward, all new frames are 631 forwarded directly to FW, without duplicate detect, reordering, 632 etc. 633 <legal all> 634 */ 635 636 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 637 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23 638 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 23 639 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000 640 641 642 /* Description PN_ERROR_DETECTED_FLAG 643 644 Set by REO, can only be cleared by SW 645 646 When set, REO has detected a PN error and from that moment 647 forward, all new frames are forwarded directly to FW, without 648 duplicate detect, reordering, etc. 649 <legal all> 650 */ 651 652 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 653 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 24 654 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 24 655 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x01000000 656 657 658 /* Description RESERVED_3A 659 660 <legal 0> 661 */ 662 663 #define RX_REO_QUEUE_RESERVED_3A_OFFSET 0x0000000c 664 #define RX_REO_QUEUE_RESERVED_3A_LSB 25 665 #define RX_REO_QUEUE_RESERVED_3A_MSB 30 666 #define RX_REO_QUEUE_RESERVED_3A_MASK 0x7e000000 667 668 669 /* Description PN_VALID 670 671 PN number in next fields are valid. It can be filled by 672 SW if it wants to fill in the any negotiated SSN, otherwise 673 REO will fill the pn based on the first received packet 674 and set this bit to 1. 675 <legal all> 676 */ 677 678 #define RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000c 679 #define RX_REO_QUEUE_PN_VALID_LSB 31 680 #define RX_REO_QUEUE_PN_VALID_MSB 31 681 #define RX_REO_QUEUE_PN_VALID_MASK 0x80000000 682 683 684 /* Description PN_31_0 685 686 Bits [31:0] of the PN number extracted from the IV field 687 688 <legal all> 689 */ 690 691 #define RX_REO_QUEUE_PN_31_0_OFFSET 0x00000010 692 #define RX_REO_QUEUE_PN_31_0_LSB 0 693 #define RX_REO_QUEUE_PN_31_0_MSB 31 694 #define RX_REO_QUEUE_PN_31_0_MASK 0xffffffff 695 696 697 /* Description PN_63_32 698 699 Bits [63:32] of the PN number. 700 <legal all> 701 */ 702 703 #define RX_REO_QUEUE_PN_63_32_OFFSET 0x00000014 704 #define RX_REO_QUEUE_PN_63_32_LSB 0 705 #define RX_REO_QUEUE_PN_63_32_MSB 31 706 #define RX_REO_QUEUE_PN_63_32_MASK 0xffffffff 707 708 709 /* Description PN_95_64 710 711 Bits [95:64] of the PN number. 712 <legal all> 713 */ 714 715 #define RX_REO_QUEUE_PN_95_64_OFFSET 0x00000018 716 #define RX_REO_QUEUE_PN_95_64_LSB 0 717 #define RX_REO_QUEUE_PN_95_64_MSB 31 718 #define RX_REO_QUEUE_PN_95_64_MASK 0xffffffff 719 720 721 /* Description PN_127_96 722 723 Bits [127:96] of the PN number. 724 <legal all> 725 */ 726 727 #define RX_REO_QUEUE_PN_127_96_OFFSET 0x0000001c 728 #define RX_REO_QUEUE_PN_127_96_LSB 0 729 #define RX_REO_QUEUE_PN_127_96_MSB 31 730 #define RX_REO_QUEUE_PN_127_96_MASK 0xffffffff 731 732 733 /* Description LAST_RX_ENQUEUE_TIMESTAMP 734 735 This timestamp is updated when an MPDU is received and accesses 736 this Queue Descriptor. It does not include the access due 737 to Command TLVs or Aging (which will be updated in Last_rx_dequeue_timestamp). 738 739 <legal all> 740 */ 741 742 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 743 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 744 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MSB 31 745 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff 746 747 748 /* Description LAST_RX_DEQUEUE_TIMESTAMP 749 750 This timestamp is used for Aging. When an MPDU or multiple 751 MPDUs are forwarded, either due to window movement, bar, 752 aging or command flush, this timestamp is updated. Also 753 when the bitmap is all zero and the first time an MPDU is 754 queued (opcode=QCUR), this timestamp is updated for aging. 755 756 <legal all> 757 */ 758 759 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 760 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 761 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31 762 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff 763 764 765 /* Description PTR_TO_NEXT_AGING_QUEUE_31_0 766 767 Address (address bits 31-0)of next RX_REO_QUEUE descriptor 768 in the 'receive timestamp' ordered list. 769 From it the Position of this queue descriptor in the per 770 AC aging waitlist can be derived. 771 Value 0x0 indicates the 'NULL' pointer which implies that 772 this is the last entry in the list. 773 <legal all> 774 */ 775 776 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 777 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 778 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MSB 31 779 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff 780 781 782 /* Description PTR_TO_NEXT_AGING_QUEUE_39_32 783 784 Address (address bits 39-32)of next RX_REO_QUEUE descriptor 785 in the 'receive timestamp' ordered list. 786 From it the Position of this queue descriptor in the per 787 AC aging waitlist can be derived. 788 Value 0x0 indicates the 'NULL' pointer which implies that 789 this is the last entry in the list. 790 <legal all> 791 */ 792 793 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c 794 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 795 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MSB 7 796 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff 797 798 799 /* Description RESERVED_11A 800 801 <legal 0> 802 */ 803 804 #define RX_REO_QUEUE_RESERVED_11A_OFFSET 0x0000002c 805 #define RX_REO_QUEUE_RESERVED_11A_LSB 8 806 #define RX_REO_QUEUE_RESERVED_11A_MSB 31 807 #define RX_REO_QUEUE_RESERVED_11A_MASK 0xffffff00 808 809 810 /* Description PTR_TO_PREVIOUS_AGING_QUEUE_31_0 811 812 Address (address bits 31-0)of next RX_REO_QUEUE descriptor 813 in the 'receive timestamp' ordered list. 814 From it the Position of this queue descriptor in the per 815 AC aging waitlist can be derived. 816 Value 0x0 indicates the 'NULL' pointer which implies that 817 this is the first entry in the list. 818 <legal all> 819 */ 820 821 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 822 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 823 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MSB 31 824 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff 825 826 827 /* Description PTR_TO_PREVIOUS_AGING_QUEUE_39_32 828 829 Address (address bits 39-32)of next RX_REO_QUEUE descriptor 830 in the 'receive timestamp' ordered list. 831 From it the Position of this queue descriptor in the per 832 AC aging waitlist can be derived. 833 Value 0x0 indicates the 'NULL' pointer which implies that 834 this is the first entry in the list. 835 <legal all> 836 */ 837 838 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 839 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 840 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MSB 7 841 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff 842 843 844 /* Description STATISTICS_COUNTER_INDEX 845 846 This is used to select one of the REO register sets for 847 tracking statistics—MSDU count and MSDU byte count in 848 Waikiki (Not supported in Hamilton). 849 850 Usually all the queues pertaining to one virtual device 851 use one statistics register set, and each virtual device 852 maps to a different set in case of not too many virtual 853 devices. 854 <legal 0-47> 855 */ 856 857 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_OFFSET 0x00000034 858 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_LSB 8 859 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MSB 13 860 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MASK 0x00003f00 861 862 863 /* Description RESERVED_13A 864 865 <legal 0> 866 */ 867 868 #define RX_REO_QUEUE_RESERVED_13A_OFFSET 0x00000034 869 #define RX_REO_QUEUE_RESERVED_13A_LSB 14 870 #define RX_REO_QUEUE_RESERVED_13A_MSB 31 871 #define RX_REO_QUEUE_RESERVED_13A_MASK 0xffffc000 872 873 874 /* Description RX_BITMAP_31_0 875 876 When a bit is set, the corresponding frame is currently 877 held in the re-order queue. 878 The bitmap is Fully managed by HW. 879 SW shall init this to 0, and then never ever change it 880 <legal all> 881 */ 882 883 #define RX_REO_QUEUE_RX_BITMAP_31_0_OFFSET 0x00000038 884 #define RX_REO_QUEUE_RX_BITMAP_31_0_LSB 0 885 #define RX_REO_QUEUE_RX_BITMAP_31_0_MSB 31 886 #define RX_REO_QUEUE_RX_BITMAP_31_0_MASK 0xffffffff 887 888 889 /* Description RX_BITMAP_63_32 890 891 See Rx_bitmap_31_0 description 892 <legal all> 893 */ 894 895 #define RX_REO_QUEUE_RX_BITMAP_63_32_OFFSET 0x0000003c 896 #define RX_REO_QUEUE_RX_BITMAP_63_32_LSB 0 897 #define RX_REO_QUEUE_RX_BITMAP_63_32_MSB 31 898 #define RX_REO_QUEUE_RX_BITMAP_63_32_MASK 0xffffffff 899 900 901 /* Description RX_BITMAP_95_64 902 903 See Rx_bitmap_31_0 description 904 <legal all> 905 */ 906 907 #define RX_REO_QUEUE_RX_BITMAP_95_64_OFFSET 0x00000040 908 #define RX_REO_QUEUE_RX_BITMAP_95_64_LSB 0 909 #define RX_REO_QUEUE_RX_BITMAP_95_64_MSB 31 910 #define RX_REO_QUEUE_RX_BITMAP_95_64_MASK 0xffffffff 911 912 913 /* Description RX_BITMAP_127_96 914 915 See Rx_bitmap_31_0 description 916 <legal all> 917 */ 918 919 #define RX_REO_QUEUE_RX_BITMAP_127_96_OFFSET 0x00000044 920 #define RX_REO_QUEUE_RX_BITMAP_127_96_LSB 0 921 #define RX_REO_QUEUE_RX_BITMAP_127_96_MSB 31 922 #define RX_REO_QUEUE_RX_BITMAP_127_96_MASK 0xffffffff 923 924 925 /* Description RX_BITMAP_159_128 926 927 See Rx_bitmap_31_0 description 928 <legal all> 929 */ 930 931 #define RX_REO_QUEUE_RX_BITMAP_159_128_OFFSET 0x00000048 932 #define RX_REO_QUEUE_RX_BITMAP_159_128_LSB 0 933 #define RX_REO_QUEUE_RX_BITMAP_159_128_MSB 31 934 #define RX_REO_QUEUE_RX_BITMAP_159_128_MASK 0xffffffff 935 936 937 /* Description RX_BITMAP_191_160 938 939 See Rx_bitmap_31_0 description 940 <legal all> 941 */ 942 943 #define RX_REO_QUEUE_RX_BITMAP_191_160_OFFSET 0x0000004c 944 #define RX_REO_QUEUE_RX_BITMAP_191_160_LSB 0 945 #define RX_REO_QUEUE_RX_BITMAP_191_160_MSB 31 946 #define RX_REO_QUEUE_RX_BITMAP_191_160_MASK 0xffffffff 947 948 949 /* Description RX_BITMAP_223_192 950 951 See Rx_bitmap_31_0 description 952 <legal all> 953 */ 954 955 #define RX_REO_QUEUE_RX_BITMAP_223_192_OFFSET 0x00000050 956 #define RX_REO_QUEUE_RX_BITMAP_223_192_LSB 0 957 #define RX_REO_QUEUE_RX_BITMAP_223_192_MSB 31 958 #define RX_REO_QUEUE_RX_BITMAP_223_192_MASK 0xffffffff 959 960 961 /* Description RX_BITMAP_255_224 962 963 See Rx_bitmap_31_0 description 964 <legal all> 965 */ 966 967 #define RX_REO_QUEUE_RX_BITMAP_255_224_OFFSET 0x00000054 968 #define RX_REO_QUEUE_RX_BITMAP_255_224_LSB 0 969 #define RX_REO_QUEUE_RX_BITMAP_255_224_MSB 31 970 #define RX_REO_QUEUE_RX_BITMAP_255_224_MASK 0xffffffff 971 972 973 /* Description RX_BITMAP_287_256 974 975 See Rx_bitmap_31_0 description 976 <legal all> 977 */ 978 979 #define RX_REO_QUEUE_RX_BITMAP_287_256_OFFSET 0x00000058 980 #define RX_REO_QUEUE_RX_BITMAP_287_256_LSB 0 981 #define RX_REO_QUEUE_RX_BITMAP_287_256_MSB 31 982 #define RX_REO_QUEUE_RX_BITMAP_287_256_MASK 0xffffffff 983 984 985 /* Description CURRENT_MPDU_COUNT 986 987 The number of MPDUs in the queue. 988 989 <legal all> 990 */ 991 992 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_OFFSET 0x0000005c 993 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_LSB 0 994 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MSB 6 995 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MASK 0x0000007f 996 997 998 /* Description CURRENT_MSDU_COUNT 999 1000 The number of MSDUs in the queue. 1001 <legal all> 1002 */ 1003 1004 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_OFFSET 0x0000005c 1005 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_LSB 7 1006 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MSB 31 1007 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MASK 0xffffff80 1008 1009 1010 /* Description LAST_SN_REG_INDEX 1011 1012 REO has registers to save the last SN seen in up to 9 REO 1013 queues, to support "leaky APs." 1014 1015 This field gives the register number to use for saving the 1016 last SN of this REO queue. 1017 <legal 0-8> 1018 */ 1019 1020 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_OFFSET 0x00000060 1021 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_LSB 0 1022 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_MSB 3 1023 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_MASK 0x0000000f 1024 1025 1026 /* Description TIMEOUT_COUNT 1027 1028 The number of times that REO started forwarding frames even 1029 though there is a hole in the bitmap. Forwarding reason 1030 is Timeout 1031 1032 The counter saturates and freezes at 0x3F 1033 1034 <legal all> 1035 */ 1036 1037 #define RX_REO_QUEUE_TIMEOUT_COUNT_OFFSET 0x00000060 1038 #define RX_REO_QUEUE_TIMEOUT_COUNT_LSB 4 1039 #define RX_REO_QUEUE_TIMEOUT_COUNT_MSB 9 1040 #define RX_REO_QUEUE_TIMEOUT_COUNT_MASK 0x000003f0 1041 1042 1043 /* Description FORWARD_DUE_TO_BAR_COUNT 1044 1045 The number of times that REO started forwarding frames even 1046 though there is a hole in the bitmap. Forwarding reason 1047 is reception of BAR frame. 1048 1049 The counter saturates and freezes at 0x3F 1050 1051 <legal all> 1052 */ 1053 1054 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000060 1055 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_LSB 10 1056 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MSB 15 1057 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 1058 1059 1060 /* Description DUPLICATE_COUNT 1061 1062 The number of duplicate frames that have been detected 1063 <legal all> 1064 */ 1065 1066 #define RX_REO_QUEUE_DUPLICATE_COUNT_OFFSET 0x00000060 1067 #define RX_REO_QUEUE_DUPLICATE_COUNT_LSB 16 1068 #define RX_REO_QUEUE_DUPLICATE_COUNT_MSB 31 1069 #define RX_REO_QUEUE_DUPLICATE_COUNT_MASK 0xffff0000 1070 1071 1072 /* Description FRAMES_IN_ORDER_COUNT 1073 1074 The number of frames that have been received in order (without 1075 a hole that prevented them from being forwarded immediately) 1076 1077 1078 This corresponds to the Reorder opcodes: 1079 'FWDCUR' and 'FWD BUF' 1080 1081 <legal all> 1082 */ 1083 1084 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000064 1085 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_LSB 0 1086 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MSB 23 1087 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff 1088 1089 1090 /* Description BAR_RECEIVED_COUNT 1091 1092 The number of times a BAR frame is received. 1093 1094 This corresponds to the Reorder opcodes with 'DROP' 1095 1096 The counter saturates and freezes at 0xFF 1097 <legal all> 1098 */ 1099 1100 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_OFFSET 0x00000064 1101 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_LSB 24 1102 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MSB 31 1103 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MASK 0xff000000 1104 1105 1106 /* Description MPDU_FRAMES_PROCESSED_COUNT 1107 1108 The total number of MPDU frames that have been processed 1109 by REO. 'Processing' here means that REO has received them 1110 out of the entrance ring, and retrieved the corresponding 1111 RX_REO_QUEUE Descriptor. 1112 1113 Note that this count includes duplicates, frames that later 1114 had errors, etc. 1115 1116 Note that field 'Duplicate_count' indicates how many of 1117 these MPDUs were duplicates. 1118 1119 <legal all> 1120 */ 1121 1122 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 1123 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 1124 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MSB 31 1125 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 1126 1127 1128 /* Description MSDU_FRAMES_PROCESSED_COUNT 1129 1130 The total number of MSDU frames that have been processed 1131 by REO. 'Processing' here means that REO has received them 1132 out of the entrance ring, and retrieved the corresponding 1133 RX_REO_QUEUE Descriptor. 1134 1135 Note that this count includes duplicates, frames that later 1136 had errors, etc. 1137 1138 <legal all> 1139 */ 1140 1141 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000006c 1142 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 1143 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MSB 31 1144 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 1145 1146 1147 /* Description TOTAL_PROCESSED_BYTE_COUNT 1148 1149 An approximation of the number of bytes processed for this 1150 queue. 1151 'Processing' here means that REO has received them out of 1152 the entrance ring, and retrieved the corresponding RX_REO_QUEUE 1153 Descriptor. 1154 1155 Note that this count includes duplicates, frames that later 1156 had errors, etc. 1157 1158 In 64 byte units 1159 <legal all> 1160 */ 1161 1162 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000070 1163 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 1164 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MSB 31 1165 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff 1166 1167 1168 /* Description LATE_RECEIVE_MPDU_COUNT 1169 1170 The number of MPDUs received after the window had already 1171 moved on. The 'late' sequence window is defined as (Window 1172 SSN - 256) - (Window SSN - 1) 1173 1174 This corresponds with Out of order detection in duplicate 1175 detect FSM 1176 1177 The counter saturates and freezes at 0xFFF 1178 1179 <legal all> 1180 */ 1181 1182 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000074 1183 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_LSB 0 1184 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MSB 11 1185 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff 1186 1187 1188 /* Description WINDOW_JUMP_2K 1189 1190 The number of times the window moved more then 2K 1191 1192 The counter saturates and freezes at 0xF 1193 1194 (Note: field name can not start with number: previous 2k_window_jump) 1195 1196 1197 <legal all> 1198 */ 1199 1200 #define RX_REO_QUEUE_WINDOW_JUMP_2K_OFFSET 0x00000074 1201 #define RX_REO_QUEUE_WINDOW_JUMP_2K_LSB 12 1202 #define RX_REO_QUEUE_WINDOW_JUMP_2K_MSB 15 1203 #define RX_REO_QUEUE_WINDOW_JUMP_2K_MASK 0x0000f000 1204 1205 1206 /* Description HOLE_COUNT 1207 1208 The number of times a hole was created in the receive bitmap. 1209 1210 1211 This corresponds to the Reorder opcodes with 'QCUR' 1212 1213 <legal all> 1214 */ 1215 1216 #define RX_REO_QUEUE_HOLE_COUNT_OFFSET 0x00000074 1217 #define RX_REO_QUEUE_HOLE_COUNT_LSB 16 1218 #define RX_REO_QUEUE_HOLE_COUNT_MSB 31 1219 #define RX_REO_QUEUE_HOLE_COUNT_MASK 0xffff0000 1220 1221 1222 /* Description AGING_DROP_MPDU_COUNT 1223 1224 The number of holes in the bitmap that moved due to aging 1225 counter expiry 1226 <legal all> 1227 */ 1228 1229 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_OFFSET 0x00000078 1230 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_LSB 0 1231 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MSB 15 1232 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff 1233 1234 1235 /* Description AGING_DROP_INTERVAL 1236 1237 The number of times holes got removed from the bitmap due 1238 to aging counter expiry 1239 <legal all> 1240 */ 1241 1242 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_OFFSET 0x00000078 1243 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_LSB 16 1244 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_MSB 23 1245 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_MASK 0x00ff0000 1246 1247 1248 /* Description RESERVED_30 1249 1250 <legal 0> 1251 */ 1252 1253 #define RX_REO_QUEUE_RESERVED_30_OFFSET 0x00000078 1254 #define RX_REO_QUEUE_RESERVED_30_LSB 24 1255 #define RX_REO_QUEUE_RESERVED_30_MSB 31 1256 #define RX_REO_QUEUE_RESERVED_30_MASK 0xff000000 1257 1258 1259 /* Description RESERVED_31 1260 1261 <legal 0> 1262 */ 1263 1264 #define RX_REO_QUEUE_RESERVED_31_OFFSET 0x0000007c 1265 #define RX_REO_QUEUE_RESERVED_31_LSB 0 1266 #define RX_REO_QUEUE_RESERVED_31_MSB 31 1267 #define RX_REO_QUEUE_RESERVED_31_MASK 0xffffffff 1268 1269 1270 1271 #endif // RX_REO_QUEUE 1272