1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _RX_REO_QUEUE_1K_H_ 19 #define _RX_REO_QUEUE_1K_H_ 20 #if !defined(__ASSEMBLER__) 21 #endif 22 23 #include "uniform_descriptor_header.h" 24 #define NUM_OF_DWORDS_RX_REO_QUEUE_1K 32 25 26 27 struct rx_reo_queue_1k { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 struct uniform_descriptor_header descriptor_header; 30 uint32_t rx_bitmap_319_288 : 32; // [31:0] 31 uint32_t rx_bitmap_351_320 : 32; // [31:0] 32 uint32_t rx_bitmap_383_352 : 32; // [31:0] 33 uint32_t rx_bitmap_415_384 : 32; // [31:0] 34 uint32_t rx_bitmap_447_416 : 32; // [31:0] 35 uint32_t rx_bitmap_479_448 : 32; // [31:0] 36 uint32_t rx_bitmap_511_480 : 32; // [31:0] 37 uint32_t rx_bitmap_543_512 : 32; // [31:0] 38 uint32_t rx_bitmap_575_544 : 32; // [31:0] 39 uint32_t rx_bitmap_607_576 : 32; // [31:0] 40 uint32_t rx_bitmap_639_608 : 32; // [31:0] 41 uint32_t rx_bitmap_671_640 : 32; // [31:0] 42 uint32_t rx_bitmap_703_672 : 32; // [31:0] 43 uint32_t rx_bitmap_735_704 : 32; // [31:0] 44 uint32_t rx_bitmap_767_736 : 32; // [31:0] 45 uint32_t rx_bitmap_799_768 : 32; // [31:0] 46 uint32_t rx_bitmap_831_800 : 32; // [31:0] 47 uint32_t rx_bitmap_863_832 : 32; // [31:0] 48 uint32_t rx_bitmap_895_864 : 32; // [31:0] 49 uint32_t rx_bitmap_927_896 : 32; // [31:0] 50 uint32_t rx_bitmap_959_928 : 32; // [31:0] 51 uint32_t rx_bitmap_991_960 : 32; // [31:0] 52 uint32_t rx_bitmap_1023_992 : 32; // [31:0] 53 uint32_t reserved_24 : 32; // [31:0] 54 uint32_t reserved_25 : 32; // [31:0] 55 uint32_t reserved_26 : 32; // [31:0] 56 uint32_t reserved_27 : 32; // [31:0] 57 uint32_t reserved_28 : 32; // [31:0] 58 uint32_t reserved_29 : 32; // [31:0] 59 uint32_t reserved_30 : 32; // [31:0] 60 uint32_t reserved_31 : 32; // [31:0] 61 #else 62 struct uniform_descriptor_header descriptor_header; 63 uint32_t rx_bitmap_319_288 : 32; // [31:0] 64 uint32_t rx_bitmap_351_320 : 32; // [31:0] 65 uint32_t rx_bitmap_383_352 : 32; // [31:0] 66 uint32_t rx_bitmap_415_384 : 32; // [31:0] 67 uint32_t rx_bitmap_447_416 : 32; // [31:0] 68 uint32_t rx_bitmap_479_448 : 32; // [31:0] 69 uint32_t rx_bitmap_511_480 : 32; // [31:0] 70 uint32_t rx_bitmap_543_512 : 32; // [31:0] 71 uint32_t rx_bitmap_575_544 : 32; // [31:0] 72 uint32_t rx_bitmap_607_576 : 32; // [31:0] 73 uint32_t rx_bitmap_639_608 : 32; // [31:0] 74 uint32_t rx_bitmap_671_640 : 32; // [31:0] 75 uint32_t rx_bitmap_703_672 : 32; // [31:0] 76 uint32_t rx_bitmap_735_704 : 32; // [31:0] 77 uint32_t rx_bitmap_767_736 : 32; // [31:0] 78 uint32_t rx_bitmap_799_768 : 32; // [31:0] 79 uint32_t rx_bitmap_831_800 : 32; // [31:0] 80 uint32_t rx_bitmap_863_832 : 32; // [31:0] 81 uint32_t rx_bitmap_895_864 : 32; // [31:0] 82 uint32_t rx_bitmap_927_896 : 32; // [31:0] 83 uint32_t rx_bitmap_959_928 : 32; // [31:0] 84 uint32_t rx_bitmap_991_960 : 32; // [31:0] 85 uint32_t rx_bitmap_1023_992 : 32; // [31:0] 86 uint32_t reserved_24 : 32; // [31:0] 87 uint32_t reserved_25 : 32; // [31:0] 88 uint32_t reserved_26 : 32; // [31:0] 89 uint32_t reserved_27 : 32; // [31:0] 90 uint32_t reserved_28 : 32; // [31:0] 91 uint32_t reserved_29 : 32; // [31:0] 92 uint32_t reserved_30 : 32; // [31:0] 93 uint32_t reserved_31 : 32; // [31:0] 94 #endif 95 }; 96 97 98 /* Description DESCRIPTOR_HEADER 99 100 Details about which module owns this struct. 101 Note that sub field "Buffer_type" shall be set to "Receive_REO_queue_1k_descriptor" 102 103 */ 104 105 106 /* Description OWNER 107 108 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 109 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 110 111 The owner of this data structure: 112 <enum 0 WBM_owned> Buffer Manager currently owns this data 113 structure. 114 <enum 1 SW_OR_FW_owned> Software of FW currently owns this 115 data structure. 116 <enum 2 TQM_owned> Transmit Queue Manager currently owns 117 this data structure. 118 <enum 3 RXDMA_owned> Receive DMA currently owns this data 119 structure. 120 <enum 4 REO_owned> Reorder currently owns this data structure. 121 122 <enum 5 SWITCH_owned> SWITCH currently owns this data structure. 123 124 125 <legal 0-5> 126 */ 127 128 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 129 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_LSB 0 130 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MSB 3 131 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 132 133 134 /* Description BUFFER_TYPE 135 136 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 137 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 138 139 Field describing what contents format is of this descriptor 140 141 142 <enum 0 Transmit_MSDU_Link_descriptor> 143 <enum 1 Transmit_MPDU_Link_descriptor> 144 <enum 2 Transmit_MPDU_Queue_head_descriptor> 145 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 146 <enum 4 Transmit_flow_descriptor> 147 <enum 5 Transmit_buffer> NOT TO BE USED: 148 149 <enum 6 Receive_MSDU_Link_descriptor> 150 <enum 7 Receive_MPDU_Link_descriptor> 151 <enum 8 Receive_REO_queue_descriptor> 152 <enum 9 Receive_REO_queue_1k_descriptor> 153 <enum 10 Receive_REO_queue_ext_descriptor> 154 155 <enum 11 Receive_buffer> 156 157 <enum 12 Idle_link_list_entry> 158 159 <legal 0-12> 160 */ 161 162 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 163 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 164 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 165 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 166 167 168 /* Description TX_MPDU_QUEUE_NUMBER 169 170 Consumer: TQM/Debug 171 Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) 172 173 Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor 174 175 176 Indicates the MPDU queue ID to which this MPDU descriptor 177 belongs 178 Used for tracking and debugging 179 180 Hamilton and Waikiki used bits [19:0] of word 1 of 'TX_MPDU_LINK,' 181 word 16 of 'TX_MPDU_QUEUE_HEAD' and word 1 of 'TX_MPDU_QUEUE_EXT' 182 for this. 183 <legal all> 184 */ 185 186 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 187 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 188 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 189 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 190 191 192 /* Description RESERVED_0A 193 194 <legal 0> 195 */ 196 197 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 198 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 199 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 200 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 201 202 203 /* Description RX_BITMAP_319_288 204 205 When a bit is set, the corresponding frame is currently 206 held in the re-order queue. 207 The bitmap is Fully managed by HW. 208 SW shall init this to 0, and then never ever change it 209 <legal all> 210 */ 211 212 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_OFFSET 0x00000004 213 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_LSB 0 214 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MSB 31 215 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MASK 0xffffffff 216 217 218 /* Description RX_BITMAP_351_320 219 220 See Rx_bitmap_319_288 description 221 <legal all> 222 */ 223 224 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_OFFSET 0x00000008 225 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_LSB 0 226 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MSB 31 227 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MASK 0xffffffff 228 229 230 /* Description RX_BITMAP_383_352 231 232 See Rx_bitmap_319_288 description 233 <legal all> 234 */ 235 236 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_OFFSET 0x0000000c 237 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_LSB 0 238 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MSB 31 239 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MASK 0xffffffff 240 241 242 /* Description RX_BITMAP_415_384 243 244 See Rx_bitmap_319_288 description 245 <legal all> 246 */ 247 248 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_OFFSET 0x00000010 249 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_LSB 0 250 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MSB 31 251 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MASK 0xffffffff 252 253 254 /* Description RX_BITMAP_447_416 255 256 See Rx_bitmap_319_288 description 257 <legal all> 258 */ 259 260 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_OFFSET 0x00000014 261 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_LSB 0 262 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MSB 31 263 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MASK 0xffffffff 264 265 266 /* Description RX_BITMAP_479_448 267 268 See Rx_bitmap_319_288 description 269 <legal all> 270 */ 271 272 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_OFFSET 0x00000018 273 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_LSB 0 274 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MSB 31 275 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MASK 0xffffffff 276 277 278 /* Description RX_BITMAP_511_480 279 280 See Rx_bitmap_319_288 description 281 <legal all> 282 */ 283 284 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_OFFSET 0x0000001c 285 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_LSB 0 286 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MSB 31 287 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MASK 0xffffffff 288 289 290 /* Description RX_BITMAP_543_512 291 292 See Rx_bitmap_319_288 description 293 <legal all> 294 */ 295 296 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_OFFSET 0x00000020 297 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_LSB 0 298 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MSB 31 299 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MASK 0xffffffff 300 301 302 /* Description RX_BITMAP_575_544 303 304 See Rx_bitmap_319_288 description 305 <legal all> 306 */ 307 308 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_OFFSET 0x00000024 309 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_LSB 0 310 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MSB 31 311 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MASK 0xffffffff 312 313 314 /* Description RX_BITMAP_607_576 315 316 See Rx_bitmap_319_288 description 317 <legal all> 318 */ 319 320 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_OFFSET 0x00000028 321 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_LSB 0 322 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MSB 31 323 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MASK 0xffffffff 324 325 326 /* Description RX_BITMAP_639_608 327 328 See Rx_bitmap_319_288 description 329 <legal all> 330 */ 331 332 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_OFFSET 0x0000002c 333 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_LSB 0 334 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MSB 31 335 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MASK 0xffffffff 336 337 338 /* Description RX_BITMAP_671_640 339 340 See Rx_bitmap_319_288 description 341 <legal all> 342 */ 343 344 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_OFFSET 0x00000030 345 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_LSB 0 346 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MSB 31 347 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MASK 0xffffffff 348 349 350 /* Description RX_BITMAP_703_672 351 352 See Rx_bitmap_319_288 description 353 <legal all> 354 */ 355 356 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_OFFSET 0x00000034 357 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_LSB 0 358 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MSB 31 359 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MASK 0xffffffff 360 361 362 /* Description RX_BITMAP_735_704 363 364 See Rx_bitmap_319_288 description 365 <legal all> 366 */ 367 368 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_OFFSET 0x00000038 369 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_LSB 0 370 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MSB 31 371 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MASK 0xffffffff 372 373 374 /* Description RX_BITMAP_767_736 375 376 See Rx_bitmap_319_288 description 377 <legal all> 378 */ 379 380 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_OFFSET 0x0000003c 381 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_LSB 0 382 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MSB 31 383 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MASK 0xffffffff 384 385 386 /* Description RX_BITMAP_799_768 387 388 See Rx_bitmap_319_288 description 389 <legal all> 390 */ 391 392 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_OFFSET 0x00000040 393 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_LSB 0 394 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MSB 31 395 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MASK 0xffffffff 396 397 398 /* Description RX_BITMAP_831_800 399 400 See Rx_bitmap_319_288 description 401 <legal all> 402 */ 403 404 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_OFFSET 0x00000044 405 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_LSB 0 406 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MSB 31 407 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MASK 0xffffffff 408 409 410 /* Description RX_BITMAP_863_832 411 412 See Rx_bitmap_319_288 description 413 <legal all> 414 */ 415 416 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_OFFSET 0x00000048 417 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_LSB 0 418 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MSB 31 419 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MASK 0xffffffff 420 421 422 /* Description RX_BITMAP_895_864 423 424 See Rx_bitmap_319_288 description 425 <legal all> 426 */ 427 428 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_OFFSET 0x0000004c 429 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_LSB 0 430 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MSB 31 431 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MASK 0xffffffff 432 433 434 /* Description RX_BITMAP_927_896 435 436 See Rx_bitmap_319_288 description 437 <legal all> 438 */ 439 440 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_OFFSET 0x00000050 441 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_LSB 0 442 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MSB 31 443 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MASK 0xffffffff 444 445 446 /* Description RX_BITMAP_959_928 447 448 See Rx_bitmap_319_288 description 449 <legal all> 450 */ 451 452 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_OFFSET 0x00000054 453 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_LSB 0 454 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MSB 31 455 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MASK 0xffffffff 456 457 458 /* Description RX_BITMAP_991_960 459 460 See Rx_bitmap_319_288 description 461 <legal all> 462 */ 463 464 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_OFFSET 0x00000058 465 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_LSB 0 466 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MSB 31 467 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MASK 0xffffffff 468 469 470 /* Description RX_BITMAP_1023_992 471 472 See Rx_bitmap_319_288 description 473 <legal all> 474 */ 475 476 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_OFFSET 0x0000005c 477 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_LSB 0 478 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MSB 31 479 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MASK 0xffffffff 480 481 482 /* Description RESERVED_24 483 484 <legal 0> 485 */ 486 487 #define RX_REO_QUEUE_1K_RESERVED_24_OFFSET 0x00000060 488 #define RX_REO_QUEUE_1K_RESERVED_24_LSB 0 489 #define RX_REO_QUEUE_1K_RESERVED_24_MSB 31 490 #define RX_REO_QUEUE_1K_RESERVED_24_MASK 0xffffffff 491 492 493 /* Description RESERVED_25 494 495 <legal 0> 496 */ 497 498 #define RX_REO_QUEUE_1K_RESERVED_25_OFFSET 0x00000064 499 #define RX_REO_QUEUE_1K_RESERVED_25_LSB 0 500 #define RX_REO_QUEUE_1K_RESERVED_25_MSB 31 501 #define RX_REO_QUEUE_1K_RESERVED_25_MASK 0xffffffff 502 503 504 /* Description RESERVED_26 505 506 <legal 0> 507 */ 508 509 #define RX_REO_QUEUE_1K_RESERVED_26_OFFSET 0x00000068 510 #define RX_REO_QUEUE_1K_RESERVED_26_LSB 0 511 #define RX_REO_QUEUE_1K_RESERVED_26_MSB 31 512 #define RX_REO_QUEUE_1K_RESERVED_26_MASK 0xffffffff 513 514 515 /* Description RESERVED_27 516 517 <legal 0> 518 */ 519 520 #define RX_REO_QUEUE_1K_RESERVED_27_OFFSET 0x0000006c 521 #define RX_REO_QUEUE_1K_RESERVED_27_LSB 0 522 #define RX_REO_QUEUE_1K_RESERVED_27_MSB 31 523 #define RX_REO_QUEUE_1K_RESERVED_27_MASK 0xffffffff 524 525 526 /* Description RESERVED_28 527 528 <legal 0> 529 */ 530 531 #define RX_REO_QUEUE_1K_RESERVED_28_OFFSET 0x00000070 532 #define RX_REO_QUEUE_1K_RESERVED_28_LSB 0 533 #define RX_REO_QUEUE_1K_RESERVED_28_MSB 31 534 #define RX_REO_QUEUE_1K_RESERVED_28_MASK 0xffffffff 535 536 537 /* Description RESERVED_29 538 539 <legal 0> 540 */ 541 542 #define RX_REO_QUEUE_1K_RESERVED_29_OFFSET 0x00000074 543 #define RX_REO_QUEUE_1K_RESERVED_29_LSB 0 544 #define RX_REO_QUEUE_1K_RESERVED_29_MSB 31 545 #define RX_REO_QUEUE_1K_RESERVED_29_MASK 0xffffffff 546 547 548 /* Description RESERVED_30 549 550 <legal 0> 551 */ 552 553 #define RX_REO_QUEUE_1K_RESERVED_30_OFFSET 0x00000078 554 #define RX_REO_QUEUE_1K_RESERVED_30_LSB 0 555 #define RX_REO_QUEUE_1K_RESERVED_30_MSB 31 556 #define RX_REO_QUEUE_1K_RESERVED_30_MASK 0xffffffff 557 558 559 /* Description RESERVED_31 560 561 <legal 0> 562 */ 563 564 #define RX_REO_QUEUE_1K_RESERVED_31_OFFSET 0x0000007c 565 #define RX_REO_QUEUE_1K_RESERVED_31_LSB 0 566 #define RX_REO_QUEUE_1K_RESERVED_31_MSB 31 567 #define RX_REO_QUEUE_1K_RESERVED_31_MASK 0xffffffff 568 569 570 571 #endif // RX_REO_QUEUE_1K 572