1*5113495bSYour Name 2*5113495bSYour Name /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name 18*5113495bSYour Name #ifndef _RX_REO_QUEUE_EXT_H_ 19*5113495bSYour Name #define _RX_REO_QUEUE_EXT_H_ 20*5113495bSYour Name #if !defined(__ASSEMBLER__) 21*5113495bSYour Name #endif 22*5113495bSYour Name 23*5113495bSYour Name #include "rx_mpdu_link_ptr.h" 24*5113495bSYour Name #include "uniform_descriptor_header.h" 25*5113495bSYour Name #define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32 26*5113495bSYour Name 27*5113495bSYour Name 28*5113495bSYour Name struct rx_reo_queue_ext { 29*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30*5113495bSYour Name struct uniform_descriptor_header descriptor_header; 31*5113495bSYour Name uint32_t reserved_1a : 32; // [31:0] 32*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_0; 33*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_1; 34*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_2; 35*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_3; 36*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_4; 37*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_5; 38*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_6; 39*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_7; 40*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_8; 41*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_9; 42*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_10; 43*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_11; 44*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_12; 45*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_13; 46*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_14; 47*5113495bSYour Name #else 48*5113495bSYour Name struct uniform_descriptor_header descriptor_header; 49*5113495bSYour Name uint32_t reserved_1a : 32; // [31:0] 50*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_0; 51*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_1; 52*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_2; 53*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_3; 54*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_4; 55*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_5; 56*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_6; 57*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_7; 58*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_8; 59*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_9; 60*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_10; 61*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_11; 62*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_12; 63*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_13; 64*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_14; 65*5113495bSYour Name #endif 66*5113495bSYour Name }; 67*5113495bSYour Name 68*5113495bSYour Name 69*5113495bSYour Name /* Description DESCRIPTOR_HEADER 70*5113495bSYour Name 71*5113495bSYour Name Details about which module owns this struct. 72*5113495bSYour Name Note that sub field "Buffer_type" shall be set to "Receive_REO_queue_ext_descriptor" 73*5113495bSYour Name 74*5113495bSYour Name */ 75*5113495bSYour Name 76*5113495bSYour Name 77*5113495bSYour Name /* Description OWNER 78*5113495bSYour Name 79*5113495bSYour Name Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 80*5113495bSYour Name Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 81*5113495bSYour Name 82*5113495bSYour Name The owner of this data structure: 83*5113495bSYour Name <enum 0 WBM_owned> Buffer Manager currently owns this data 84*5113495bSYour Name structure. 85*5113495bSYour Name <enum 1 SW_OR_FW_owned> Software of FW currently owns this 86*5113495bSYour Name data structure. 87*5113495bSYour Name <enum 2 TQM_owned> Transmit Queue Manager currently owns 88*5113495bSYour Name this data structure. 89*5113495bSYour Name <enum 3 RXDMA_owned> Receive DMA currently owns this data 90*5113495bSYour Name structure. 91*5113495bSYour Name <enum 4 REO_owned> Reorder currently owns this data structure. 92*5113495bSYour Name 93*5113495bSYour Name <enum 5 SWITCH_owned> SWITCH currently owns this data structure. 94*5113495bSYour Name 95*5113495bSYour Name 96*5113495bSYour Name <legal 0-5> 97*5113495bSYour Name */ 98*5113495bSYour Name 99*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 100*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_LSB 0 101*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MSB 3 102*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 103*5113495bSYour Name 104*5113495bSYour Name 105*5113495bSYour Name /* Description BUFFER_TYPE 106*5113495bSYour Name 107*5113495bSYour Name Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 108*5113495bSYour Name Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 109*5113495bSYour Name 110*5113495bSYour Name Field describing what contents format is of this descriptor 111*5113495bSYour Name 112*5113495bSYour Name 113*5113495bSYour Name <enum 0 Transmit_MSDU_Link_descriptor> 114*5113495bSYour Name <enum 1 Transmit_MPDU_Link_descriptor> 115*5113495bSYour Name <enum 2 Transmit_MPDU_Queue_head_descriptor> 116*5113495bSYour Name <enum 3 Transmit_MPDU_Queue_ext_descriptor> 117*5113495bSYour Name <enum 4 Transmit_flow_descriptor> 118*5113495bSYour Name <enum 5 Transmit_buffer> NOT TO BE USED: 119*5113495bSYour Name 120*5113495bSYour Name <enum 6 Receive_MSDU_Link_descriptor> 121*5113495bSYour Name <enum 7 Receive_MPDU_Link_descriptor> 122*5113495bSYour Name <enum 8 Receive_REO_queue_descriptor> 123*5113495bSYour Name <enum 9 Receive_REO_queue_1k_descriptor> 124*5113495bSYour Name <enum 10 Receive_REO_queue_ext_descriptor> 125*5113495bSYour Name 126*5113495bSYour Name <enum 11 Receive_buffer> 127*5113495bSYour Name 128*5113495bSYour Name <enum 12 Idle_link_list_entry> 129*5113495bSYour Name 130*5113495bSYour Name <legal 0-12> 131*5113495bSYour Name */ 132*5113495bSYour Name 133*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 134*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 135*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 136*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 137*5113495bSYour Name 138*5113495bSYour Name 139*5113495bSYour Name /* Description TX_MPDU_QUEUE_NUMBER 140*5113495bSYour Name 141*5113495bSYour Name Consumer: TQM/Debug 142*5113495bSYour Name Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) 143*5113495bSYour Name 144*5113495bSYour Name Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor 145*5113495bSYour Name 146*5113495bSYour Name 147*5113495bSYour Name Indicates the MPDU queue ID to which this MPDU descriptor 148*5113495bSYour Name belongs 149*5113495bSYour Name Used for tracking and debugging 150*5113495bSYour Name 151*5113495bSYour Name Hamilton and Waikiki used bits [19:0] of word 1 of 'TX_MPDU_LINK,' 152*5113495bSYour Name word 16 of 'TX_MPDU_QUEUE_HEAD' and word 1 of 'TX_MPDU_QUEUE_EXT' 153*5113495bSYour Name for this. 154*5113495bSYour Name <legal all> 155*5113495bSYour Name */ 156*5113495bSYour Name 157*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 158*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 159*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 160*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 161*5113495bSYour Name 162*5113495bSYour Name 163*5113495bSYour Name /* Description RESERVED_0A 164*5113495bSYour Name 165*5113495bSYour Name <legal 0> 166*5113495bSYour Name */ 167*5113495bSYour Name 168*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 169*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 170*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 171*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 172*5113495bSYour Name 173*5113495bSYour Name 174*5113495bSYour Name /* Description RESERVED_1A 175*5113495bSYour Name 176*5113495bSYour Name <legal 0> 177*5113495bSYour Name */ 178*5113495bSYour Name 179*5113495bSYour Name #define RX_REO_QUEUE_EXT_RESERVED_1A_OFFSET 0x00000004 180*5113495bSYour Name #define RX_REO_QUEUE_EXT_RESERVED_1A_LSB 0 181*5113495bSYour Name #define RX_REO_QUEUE_EXT_RESERVED_1A_MSB 31 182*5113495bSYour Name #define RX_REO_QUEUE_EXT_RESERVED_1A_MASK 0xffffffff 183*5113495bSYour Name 184*5113495bSYour Name 185*5113495bSYour Name /* Description MPDU_LINK_POINTER_0 186*5113495bSYour Name 187*5113495bSYour Name Consumer: REO 188*5113495bSYour Name Producer: REO 189*5113495bSYour Name 190*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 191*5113495bSYour Name 192*5113495bSYour Name */ 193*5113495bSYour Name 194*5113495bSYour Name 195*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 196*5113495bSYour Name 197*5113495bSYour Name Details of the physical address of an MPDU link descriptor 198*5113495bSYour Name 199*5113495bSYour Name */ 200*5113495bSYour Name 201*5113495bSYour Name 202*5113495bSYour Name /* Description BUFFER_ADDR_31_0 203*5113495bSYour Name 204*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 205*5113495bSYour Name descriptor OR Link Descriptor 206*5113495bSYour Name 207*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 208*5113495bSYour Name <legal all> 209*5113495bSYour Name */ 210*5113495bSYour Name 211*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008 212*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 213*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 214*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 215*5113495bSYour Name 216*5113495bSYour Name 217*5113495bSYour Name /* Description BUFFER_ADDR_39_32 218*5113495bSYour Name 219*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 220*5113495bSYour Name descriptor OR Link Descriptor 221*5113495bSYour Name 222*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 223*5113495bSYour Name <legal all> 224*5113495bSYour Name */ 225*5113495bSYour Name 226*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c 227*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 228*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 229*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 230*5113495bSYour Name 231*5113495bSYour Name 232*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 233*5113495bSYour Name 234*5113495bSYour Name Consumer: WBM 235*5113495bSYour Name Producer: SW/FW 236*5113495bSYour Name 237*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 238*5113495bSYour Name 239*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 240*5113495bSYour Name descriptor OR link descriptor that is being pointed to 241*5113495bSYour Name shall be returned after the frame has been processed. It 242*5113495bSYour Name is used by WBM for routing purposes. 243*5113495bSYour Name 244*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 245*5113495bSYour Name to the WMB buffer idle list 246*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 247*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 248*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 249*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 250*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 251*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 252*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 253*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 254*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 255*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 256*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 257*5113495bSYour Name ring 0 258*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 259*5113495bSYour Name ring 1 260*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 261*5113495bSYour Name ring 2 262*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 263*5113495bSYour Name ring 3 264*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 265*5113495bSYour Name ring 4 266*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 267*5113495bSYour Name ring 5 268*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 269*5113495bSYour Name ring 6 270*5113495bSYour Name 271*5113495bSYour Name <legal 0-12> 272*5113495bSYour Name */ 273*5113495bSYour Name 274*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c 275*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 276*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 277*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 278*5113495bSYour Name 279*5113495bSYour Name 280*5113495bSYour Name /* Description SW_BUFFER_COOKIE 281*5113495bSYour Name 282*5113495bSYour Name Cookie field exclusively used by SW. 283*5113495bSYour Name 284*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 285*5113495bSYour Name 286*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 287*5113495bSYour Name value on to other descriptors together with the physical 288*5113495bSYour Name address 289*5113495bSYour Name 290*5113495bSYour Name Field can be used by SW to for example associate the buffers 291*5113495bSYour Name physical address with the virtual address 292*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 293*5113495bSYour Name 294*5113495bSYour Name 295*5113495bSYour Name NOTE1: 296*5113495bSYour Name The three most significant bits can have a special meaning 297*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 298*5113495bSYour Name and field transmit_bw_restriction is set 299*5113495bSYour Name 300*5113495bSYour Name In case of NON punctured transmission: 301*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 302*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 303*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 304*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 305*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 306*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 307*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 308*5113495bSYour Name 309*5113495bSYour Name In case of punctured transmission: 310*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 311*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 312*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 313*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 314*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 315*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 316*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 317*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 318*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 319*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 320*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 321*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 322*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 323*5113495bSYour Name 324*5113495bSYour Name Note: a punctured transmission is indicated by the presence 325*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 326*5113495bSYour Name 327*5113495bSYour Name <legal all> 328*5113495bSYour Name */ 329*5113495bSYour Name 330*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c 331*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 332*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 333*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 334*5113495bSYour Name 335*5113495bSYour Name 336*5113495bSYour Name /* Description MPDU_LINK_POINTER_1 337*5113495bSYour Name 338*5113495bSYour Name Consumer: REO 339*5113495bSYour Name Producer: REO 340*5113495bSYour Name 341*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 342*5113495bSYour Name 343*5113495bSYour Name */ 344*5113495bSYour Name 345*5113495bSYour Name 346*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 347*5113495bSYour Name 348*5113495bSYour Name Details of the physical address of an MPDU link descriptor 349*5113495bSYour Name 350*5113495bSYour Name */ 351*5113495bSYour Name 352*5113495bSYour Name 353*5113495bSYour Name /* Description BUFFER_ADDR_31_0 354*5113495bSYour Name 355*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 356*5113495bSYour Name descriptor OR Link Descriptor 357*5113495bSYour Name 358*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 359*5113495bSYour Name <legal all> 360*5113495bSYour Name */ 361*5113495bSYour Name 362*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 363*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 364*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 365*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 366*5113495bSYour Name 367*5113495bSYour Name 368*5113495bSYour Name /* Description BUFFER_ADDR_39_32 369*5113495bSYour Name 370*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 371*5113495bSYour Name descriptor OR Link Descriptor 372*5113495bSYour Name 373*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 374*5113495bSYour Name <legal all> 375*5113495bSYour Name */ 376*5113495bSYour Name 377*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 378*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 379*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 380*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 381*5113495bSYour Name 382*5113495bSYour Name 383*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 384*5113495bSYour Name 385*5113495bSYour Name Consumer: WBM 386*5113495bSYour Name Producer: SW/FW 387*5113495bSYour Name 388*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 389*5113495bSYour Name 390*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 391*5113495bSYour Name descriptor OR link descriptor that is being pointed to 392*5113495bSYour Name shall be returned after the frame has been processed. It 393*5113495bSYour Name is used by WBM for routing purposes. 394*5113495bSYour Name 395*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 396*5113495bSYour Name to the WMB buffer idle list 397*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 398*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 399*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 400*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 401*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 402*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 403*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 404*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 405*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 406*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 407*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 408*5113495bSYour Name ring 0 409*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 410*5113495bSYour Name ring 1 411*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 412*5113495bSYour Name ring 2 413*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 414*5113495bSYour Name ring 3 415*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 416*5113495bSYour Name ring 4 417*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 418*5113495bSYour Name ring 5 419*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 420*5113495bSYour Name ring 6 421*5113495bSYour Name 422*5113495bSYour Name <legal 0-12> 423*5113495bSYour Name */ 424*5113495bSYour Name 425*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 426*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 427*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 428*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 429*5113495bSYour Name 430*5113495bSYour Name 431*5113495bSYour Name /* Description SW_BUFFER_COOKIE 432*5113495bSYour Name 433*5113495bSYour Name Cookie field exclusively used by SW. 434*5113495bSYour Name 435*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 436*5113495bSYour Name 437*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 438*5113495bSYour Name value on to other descriptors together with the physical 439*5113495bSYour Name address 440*5113495bSYour Name 441*5113495bSYour Name Field can be used by SW to for example associate the buffers 442*5113495bSYour Name physical address with the virtual address 443*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 444*5113495bSYour Name 445*5113495bSYour Name 446*5113495bSYour Name NOTE1: 447*5113495bSYour Name The three most significant bits can have a special meaning 448*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 449*5113495bSYour Name and field transmit_bw_restriction is set 450*5113495bSYour Name 451*5113495bSYour Name In case of NON punctured transmission: 452*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 453*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 454*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 455*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 456*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 457*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 458*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 459*5113495bSYour Name 460*5113495bSYour Name In case of punctured transmission: 461*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 462*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 463*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 464*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 465*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 466*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 467*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 468*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 469*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 470*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 471*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 472*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 473*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 474*5113495bSYour Name 475*5113495bSYour Name Note: a punctured transmission is indicated by the presence 476*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 477*5113495bSYour Name 478*5113495bSYour Name <legal all> 479*5113495bSYour Name */ 480*5113495bSYour Name 481*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 482*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 483*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 484*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 485*5113495bSYour Name 486*5113495bSYour Name 487*5113495bSYour Name /* Description MPDU_LINK_POINTER_2 488*5113495bSYour Name 489*5113495bSYour Name Consumer: REO 490*5113495bSYour Name Producer: REO 491*5113495bSYour Name 492*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 493*5113495bSYour Name 494*5113495bSYour Name */ 495*5113495bSYour Name 496*5113495bSYour Name 497*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 498*5113495bSYour Name 499*5113495bSYour Name Details of the physical address of an MPDU link descriptor 500*5113495bSYour Name 501*5113495bSYour Name */ 502*5113495bSYour Name 503*5113495bSYour Name 504*5113495bSYour Name /* Description BUFFER_ADDR_31_0 505*5113495bSYour Name 506*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 507*5113495bSYour Name descriptor OR Link Descriptor 508*5113495bSYour Name 509*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 510*5113495bSYour Name <legal all> 511*5113495bSYour Name */ 512*5113495bSYour Name 513*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018 514*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 515*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 516*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 517*5113495bSYour Name 518*5113495bSYour Name 519*5113495bSYour Name /* Description BUFFER_ADDR_39_32 520*5113495bSYour Name 521*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 522*5113495bSYour Name descriptor OR Link Descriptor 523*5113495bSYour Name 524*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 525*5113495bSYour Name <legal all> 526*5113495bSYour Name */ 527*5113495bSYour Name 528*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c 529*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 530*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 531*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 532*5113495bSYour Name 533*5113495bSYour Name 534*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 535*5113495bSYour Name 536*5113495bSYour Name Consumer: WBM 537*5113495bSYour Name Producer: SW/FW 538*5113495bSYour Name 539*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 540*5113495bSYour Name 541*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 542*5113495bSYour Name descriptor OR link descriptor that is being pointed to 543*5113495bSYour Name shall be returned after the frame has been processed. It 544*5113495bSYour Name is used by WBM for routing purposes. 545*5113495bSYour Name 546*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 547*5113495bSYour Name to the WMB buffer idle list 548*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 549*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 550*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 551*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 552*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 553*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 554*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 555*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 556*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 557*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 558*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 559*5113495bSYour Name ring 0 560*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 561*5113495bSYour Name ring 1 562*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 563*5113495bSYour Name ring 2 564*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 565*5113495bSYour Name ring 3 566*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 567*5113495bSYour Name ring 4 568*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 569*5113495bSYour Name ring 5 570*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 571*5113495bSYour Name ring 6 572*5113495bSYour Name 573*5113495bSYour Name <legal 0-12> 574*5113495bSYour Name */ 575*5113495bSYour Name 576*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c 577*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 578*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 579*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 580*5113495bSYour Name 581*5113495bSYour Name 582*5113495bSYour Name /* Description SW_BUFFER_COOKIE 583*5113495bSYour Name 584*5113495bSYour Name Cookie field exclusively used by SW. 585*5113495bSYour Name 586*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 587*5113495bSYour Name 588*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 589*5113495bSYour Name value on to other descriptors together with the physical 590*5113495bSYour Name address 591*5113495bSYour Name 592*5113495bSYour Name Field can be used by SW to for example associate the buffers 593*5113495bSYour Name physical address with the virtual address 594*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 595*5113495bSYour Name 596*5113495bSYour Name 597*5113495bSYour Name NOTE1: 598*5113495bSYour Name The three most significant bits can have a special meaning 599*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 600*5113495bSYour Name and field transmit_bw_restriction is set 601*5113495bSYour Name 602*5113495bSYour Name In case of NON punctured transmission: 603*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 604*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 605*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 606*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 607*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 608*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 609*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 610*5113495bSYour Name 611*5113495bSYour Name In case of punctured transmission: 612*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 613*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 614*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 615*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 616*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 617*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 618*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 619*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 620*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 621*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 622*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 623*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 624*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 625*5113495bSYour Name 626*5113495bSYour Name Note: a punctured transmission is indicated by the presence 627*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 628*5113495bSYour Name 629*5113495bSYour Name <legal all> 630*5113495bSYour Name */ 631*5113495bSYour Name 632*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c 633*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 634*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 635*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 636*5113495bSYour Name 637*5113495bSYour Name 638*5113495bSYour Name /* Description MPDU_LINK_POINTER_3 639*5113495bSYour Name 640*5113495bSYour Name Consumer: REO 641*5113495bSYour Name Producer: REO 642*5113495bSYour Name 643*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 644*5113495bSYour Name 645*5113495bSYour Name */ 646*5113495bSYour Name 647*5113495bSYour Name 648*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 649*5113495bSYour Name 650*5113495bSYour Name Details of the physical address of an MPDU link descriptor 651*5113495bSYour Name 652*5113495bSYour Name */ 653*5113495bSYour Name 654*5113495bSYour Name 655*5113495bSYour Name /* Description BUFFER_ADDR_31_0 656*5113495bSYour Name 657*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 658*5113495bSYour Name descriptor OR Link Descriptor 659*5113495bSYour Name 660*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 661*5113495bSYour Name <legal all> 662*5113495bSYour Name */ 663*5113495bSYour Name 664*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020 665*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 666*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 667*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 668*5113495bSYour Name 669*5113495bSYour Name 670*5113495bSYour Name /* Description BUFFER_ADDR_39_32 671*5113495bSYour Name 672*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 673*5113495bSYour Name descriptor OR Link Descriptor 674*5113495bSYour Name 675*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 676*5113495bSYour Name <legal all> 677*5113495bSYour Name */ 678*5113495bSYour Name 679*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024 680*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 681*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 682*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 683*5113495bSYour Name 684*5113495bSYour Name 685*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 686*5113495bSYour Name 687*5113495bSYour Name Consumer: WBM 688*5113495bSYour Name Producer: SW/FW 689*5113495bSYour Name 690*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 691*5113495bSYour Name 692*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 693*5113495bSYour Name descriptor OR link descriptor that is being pointed to 694*5113495bSYour Name shall be returned after the frame has been processed. It 695*5113495bSYour Name is used by WBM for routing purposes. 696*5113495bSYour Name 697*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 698*5113495bSYour Name to the WMB buffer idle list 699*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 700*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 701*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 702*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 703*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 704*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 705*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 706*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 707*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 708*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 709*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 710*5113495bSYour Name ring 0 711*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 712*5113495bSYour Name ring 1 713*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 714*5113495bSYour Name ring 2 715*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 716*5113495bSYour Name ring 3 717*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 718*5113495bSYour Name ring 4 719*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 720*5113495bSYour Name ring 5 721*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 722*5113495bSYour Name ring 6 723*5113495bSYour Name 724*5113495bSYour Name <legal 0-12> 725*5113495bSYour Name */ 726*5113495bSYour Name 727*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 728*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 729*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 730*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 731*5113495bSYour Name 732*5113495bSYour Name 733*5113495bSYour Name /* Description SW_BUFFER_COOKIE 734*5113495bSYour Name 735*5113495bSYour Name Cookie field exclusively used by SW. 736*5113495bSYour Name 737*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 738*5113495bSYour Name 739*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 740*5113495bSYour Name value on to other descriptors together with the physical 741*5113495bSYour Name address 742*5113495bSYour Name 743*5113495bSYour Name Field can be used by SW to for example associate the buffers 744*5113495bSYour Name physical address with the virtual address 745*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 746*5113495bSYour Name 747*5113495bSYour Name 748*5113495bSYour Name NOTE1: 749*5113495bSYour Name The three most significant bits can have a special meaning 750*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 751*5113495bSYour Name and field transmit_bw_restriction is set 752*5113495bSYour Name 753*5113495bSYour Name In case of NON punctured transmission: 754*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 755*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 756*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 757*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 758*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 759*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 760*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 761*5113495bSYour Name 762*5113495bSYour Name In case of punctured transmission: 763*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 764*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 765*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 766*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 767*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 768*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 769*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 770*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 771*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 772*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 773*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 774*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 775*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 776*5113495bSYour Name 777*5113495bSYour Name Note: a punctured transmission is indicated by the presence 778*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 779*5113495bSYour Name 780*5113495bSYour Name <legal all> 781*5113495bSYour Name */ 782*5113495bSYour Name 783*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024 784*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 785*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 786*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 787*5113495bSYour Name 788*5113495bSYour Name 789*5113495bSYour Name /* Description MPDU_LINK_POINTER_4 790*5113495bSYour Name 791*5113495bSYour Name Consumer: REO 792*5113495bSYour Name Producer: REO 793*5113495bSYour Name 794*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 795*5113495bSYour Name 796*5113495bSYour Name */ 797*5113495bSYour Name 798*5113495bSYour Name 799*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 800*5113495bSYour Name 801*5113495bSYour Name Details of the physical address of an MPDU link descriptor 802*5113495bSYour Name 803*5113495bSYour Name */ 804*5113495bSYour Name 805*5113495bSYour Name 806*5113495bSYour Name /* Description BUFFER_ADDR_31_0 807*5113495bSYour Name 808*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 809*5113495bSYour Name descriptor OR Link Descriptor 810*5113495bSYour Name 811*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 812*5113495bSYour Name <legal all> 813*5113495bSYour Name */ 814*5113495bSYour Name 815*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028 816*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 817*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 818*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 819*5113495bSYour Name 820*5113495bSYour Name 821*5113495bSYour Name /* Description BUFFER_ADDR_39_32 822*5113495bSYour Name 823*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 824*5113495bSYour Name descriptor OR Link Descriptor 825*5113495bSYour Name 826*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 827*5113495bSYour Name <legal all> 828*5113495bSYour Name */ 829*5113495bSYour Name 830*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c 831*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 832*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 833*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 834*5113495bSYour Name 835*5113495bSYour Name 836*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 837*5113495bSYour Name 838*5113495bSYour Name Consumer: WBM 839*5113495bSYour Name Producer: SW/FW 840*5113495bSYour Name 841*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 842*5113495bSYour Name 843*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 844*5113495bSYour Name descriptor OR link descriptor that is being pointed to 845*5113495bSYour Name shall be returned after the frame has been processed. It 846*5113495bSYour Name is used by WBM for routing purposes. 847*5113495bSYour Name 848*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 849*5113495bSYour Name to the WMB buffer idle list 850*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 851*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 852*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 853*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 854*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 855*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 856*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 857*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 858*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 859*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 860*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 861*5113495bSYour Name ring 0 862*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 863*5113495bSYour Name ring 1 864*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 865*5113495bSYour Name ring 2 866*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 867*5113495bSYour Name ring 3 868*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 869*5113495bSYour Name ring 4 870*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 871*5113495bSYour Name ring 5 872*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 873*5113495bSYour Name ring 6 874*5113495bSYour Name 875*5113495bSYour Name <legal 0-12> 876*5113495bSYour Name */ 877*5113495bSYour Name 878*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c 879*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 880*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 881*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 882*5113495bSYour Name 883*5113495bSYour Name 884*5113495bSYour Name /* Description SW_BUFFER_COOKIE 885*5113495bSYour Name 886*5113495bSYour Name Cookie field exclusively used by SW. 887*5113495bSYour Name 888*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 889*5113495bSYour Name 890*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 891*5113495bSYour Name value on to other descriptors together with the physical 892*5113495bSYour Name address 893*5113495bSYour Name 894*5113495bSYour Name Field can be used by SW to for example associate the buffers 895*5113495bSYour Name physical address with the virtual address 896*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 897*5113495bSYour Name 898*5113495bSYour Name 899*5113495bSYour Name NOTE1: 900*5113495bSYour Name The three most significant bits can have a special meaning 901*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 902*5113495bSYour Name and field transmit_bw_restriction is set 903*5113495bSYour Name 904*5113495bSYour Name In case of NON punctured transmission: 905*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 906*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 907*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 908*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 909*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 910*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 911*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 912*5113495bSYour Name 913*5113495bSYour Name In case of punctured transmission: 914*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 915*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 916*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 917*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 918*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 919*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 920*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 921*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 922*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 923*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 924*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 925*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 926*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 927*5113495bSYour Name 928*5113495bSYour Name Note: a punctured transmission is indicated by the presence 929*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 930*5113495bSYour Name 931*5113495bSYour Name <legal all> 932*5113495bSYour Name */ 933*5113495bSYour Name 934*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c 935*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 936*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 937*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 938*5113495bSYour Name 939*5113495bSYour Name 940*5113495bSYour Name /* Description MPDU_LINK_POINTER_5 941*5113495bSYour Name 942*5113495bSYour Name Consumer: REO 943*5113495bSYour Name Producer: REO 944*5113495bSYour Name 945*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 946*5113495bSYour Name 947*5113495bSYour Name */ 948*5113495bSYour Name 949*5113495bSYour Name 950*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 951*5113495bSYour Name 952*5113495bSYour Name Details of the physical address of an MPDU link descriptor 953*5113495bSYour Name 954*5113495bSYour Name */ 955*5113495bSYour Name 956*5113495bSYour Name 957*5113495bSYour Name /* Description BUFFER_ADDR_31_0 958*5113495bSYour Name 959*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 960*5113495bSYour Name descriptor OR Link Descriptor 961*5113495bSYour Name 962*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 963*5113495bSYour Name <legal all> 964*5113495bSYour Name */ 965*5113495bSYour Name 966*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030 967*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 968*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 969*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 970*5113495bSYour Name 971*5113495bSYour Name 972*5113495bSYour Name /* Description BUFFER_ADDR_39_32 973*5113495bSYour Name 974*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 975*5113495bSYour Name descriptor OR Link Descriptor 976*5113495bSYour Name 977*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 978*5113495bSYour Name <legal all> 979*5113495bSYour Name */ 980*5113495bSYour Name 981*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034 982*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 983*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 984*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 985*5113495bSYour Name 986*5113495bSYour Name 987*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 988*5113495bSYour Name 989*5113495bSYour Name Consumer: WBM 990*5113495bSYour Name Producer: SW/FW 991*5113495bSYour Name 992*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 993*5113495bSYour Name 994*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 995*5113495bSYour Name descriptor OR link descriptor that is being pointed to 996*5113495bSYour Name shall be returned after the frame has been processed. It 997*5113495bSYour Name is used by WBM for routing purposes. 998*5113495bSYour Name 999*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1000*5113495bSYour Name to the WMB buffer idle list 1001*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1002*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 1003*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 1004*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1005*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 1006*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1007*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 1008*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1009*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 1010*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 1011*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 1012*5113495bSYour Name ring 0 1013*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 1014*5113495bSYour Name ring 1 1015*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 1016*5113495bSYour Name ring 2 1017*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 1018*5113495bSYour Name ring 3 1019*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 1020*5113495bSYour Name ring 4 1021*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 1022*5113495bSYour Name ring 5 1023*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 1024*5113495bSYour Name ring 6 1025*5113495bSYour Name 1026*5113495bSYour Name <legal 0-12> 1027*5113495bSYour Name */ 1028*5113495bSYour Name 1029*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 1030*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1031*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1032*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1033*5113495bSYour Name 1034*5113495bSYour Name 1035*5113495bSYour Name /* Description SW_BUFFER_COOKIE 1036*5113495bSYour Name 1037*5113495bSYour Name Cookie field exclusively used by SW. 1038*5113495bSYour Name 1039*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1040*5113495bSYour Name 1041*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 1042*5113495bSYour Name value on to other descriptors together with the physical 1043*5113495bSYour Name address 1044*5113495bSYour Name 1045*5113495bSYour Name Field can be used by SW to for example associate the buffers 1046*5113495bSYour Name physical address with the virtual address 1047*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 1048*5113495bSYour Name 1049*5113495bSYour Name 1050*5113495bSYour Name NOTE1: 1051*5113495bSYour Name The three most significant bits can have a special meaning 1052*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1053*5113495bSYour Name and field transmit_bw_restriction is set 1054*5113495bSYour Name 1055*5113495bSYour Name In case of NON punctured transmission: 1056*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1057*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1058*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1059*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1060*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1061*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1062*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1063*5113495bSYour Name 1064*5113495bSYour Name In case of punctured transmission: 1065*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1066*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1067*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1068*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1069*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1070*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1071*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1072*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1073*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1074*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1075*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1076*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1077*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1078*5113495bSYour Name 1079*5113495bSYour Name Note: a punctured transmission is indicated by the presence 1080*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1081*5113495bSYour Name 1082*5113495bSYour Name <legal all> 1083*5113495bSYour Name */ 1084*5113495bSYour Name 1085*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034 1086*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1087*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1088*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1089*5113495bSYour Name 1090*5113495bSYour Name 1091*5113495bSYour Name /* Description MPDU_LINK_POINTER_6 1092*5113495bSYour Name 1093*5113495bSYour Name Consumer: REO 1094*5113495bSYour Name Producer: REO 1095*5113495bSYour Name 1096*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 1097*5113495bSYour Name 1098*5113495bSYour Name */ 1099*5113495bSYour Name 1100*5113495bSYour Name 1101*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 1102*5113495bSYour Name 1103*5113495bSYour Name Details of the physical address of an MPDU link descriptor 1104*5113495bSYour Name 1105*5113495bSYour Name */ 1106*5113495bSYour Name 1107*5113495bSYour Name 1108*5113495bSYour Name /* Description BUFFER_ADDR_31_0 1109*5113495bSYour Name 1110*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1111*5113495bSYour Name descriptor OR Link Descriptor 1112*5113495bSYour Name 1113*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1114*5113495bSYour Name <legal all> 1115*5113495bSYour Name */ 1116*5113495bSYour Name 1117*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038 1118*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1119*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1120*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1121*5113495bSYour Name 1122*5113495bSYour Name 1123*5113495bSYour Name /* Description BUFFER_ADDR_39_32 1124*5113495bSYour Name 1125*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1126*5113495bSYour Name descriptor OR Link Descriptor 1127*5113495bSYour Name 1128*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1129*5113495bSYour Name <legal all> 1130*5113495bSYour Name */ 1131*5113495bSYour Name 1132*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c 1133*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1134*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1135*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1136*5113495bSYour Name 1137*5113495bSYour Name 1138*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 1139*5113495bSYour Name 1140*5113495bSYour Name Consumer: WBM 1141*5113495bSYour Name Producer: SW/FW 1142*5113495bSYour Name 1143*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1144*5113495bSYour Name 1145*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1146*5113495bSYour Name descriptor OR link descriptor that is being pointed to 1147*5113495bSYour Name shall be returned after the frame has been processed. It 1148*5113495bSYour Name is used by WBM for routing purposes. 1149*5113495bSYour Name 1150*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1151*5113495bSYour Name to the WMB buffer idle list 1152*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1153*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 1154*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 1155*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1156*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 1157*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1158*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 1159*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1160*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 1161*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 1162*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 1163*5113495bSYour Name ring 0 1164*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 1165*5113495bSYour Name ring 1 1166*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 1167*5113495bSYour Name ring 2 1168*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 1169*5113495bSYour Name ring 3 1170*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 1171*5113495bSYour Name ring 4 1172*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 1173*5113495bSYour Name ring 5 1174*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 1175*5113495bSYour Name ring 6 1176*5113495bSYour Name 1177*5113495bSYour Name <legal 0-12> 1178*5113495bSYour Name */ 1179*5113495bSYour Name 1180*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c 1181*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1182*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1183*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1184*5113495bSYour Name 1185*5113495bSYour Name 1186*5113495bSYour Name /* Description SW_BUFFER_COOKIE 1187*5113495bSYour Name 1188*5113495bSYour Name Cookie field exclusively used by SW. 1189*5113495bSYour Name 1190*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1191*5113495bSYour Name 1192*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 1193*5113495bSYour Name value on to other descriptors together with the physical 1194*5113495bSYour Name address 1195*5113495bSYour Name 1196*5113495bSYour Name Field can be used by SW to for example associate the buffers 1197*5113495bSYour Name physical address with the virtual address 1198*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 1199*5113495bSYour Name 1200*5113495bSYour Name 1201*5113495bSYour Name NOTE1: 1202*5113495bSYour Name The three most significant bits can have a special meaning 1203*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1204*5113495bSYour Name and field transmit_bw_restriction is set 1205*5113495bSYour Name 1206*5113495bSYour Name In case of NON punctured transmission: 1207*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1208*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1209*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1210*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1211*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1212*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1213*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1214*5113495bSYour Name 1215*5113495bSYour Name In case of punctured transmission: 1216*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1217*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1218*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1219*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1220*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1221*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1222*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1223*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1224*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1225*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1226*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1227*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1228*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1229*5113495bSYour Name 1230*5113495bSYour Name Note: a punctured transmission is indicated by the presence 1231*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1232*5113495bSYour Name 1233*5113495bSYour Name <legal all> 1234*5113495bSYour Name */ 1235*5113495bSYour Name 1236*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c 1237*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1238*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1239*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1240*5113495bSYour Name 1241*5113495bSYour Name 1242*5113495bSYour Name /* Description MPDU_LINK_POINTER_7 1243*5113495bSYour Name 1244*5113495bSYour Name Consumer: REO 1245*5113495bSYour Name Producer: REO 1246*5113495bSYour Name 1247*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 1248*5113495bSYour Name 1249*5113495bSYour Name */ 1250*5113495bSYour Name 1251*5113495bSYour Name 1252*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 1253*5113495bSYour Name 1254*5113495bSYour Name Details of the physical address of an MPDU link descriptor 1255*5113495bSYour Name 1256*5113495bSYour Name */ 1257*5113495bSYour Name 1258*5113495bSYour Name 1259*5113495bSYour Name /* Description BUFFER_ADDR_31_0 1260*5113495bSYour Name 1261*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1262*5113495bSYour Name descriptor OR Link Descriptor 1263*5113495bSYour Name 1264*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1265*5113495bSYour Name <legal all> 1266*5113495bSYour Name */ 1267*5113495bSYour Name 1268*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040 1269*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1270*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1271*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1272*5113495bSYour Name 1273*5113495bSYour Name 1274*5113495bSYour Name /* Description BUFFER_ADDR_39_32 1275*5113495bSYour Name 1276*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1277*5113495bSYour Name descriptor OR Link Descriptor 1278*5113495bSYour Name 1279*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1280*5113495bSYour Name <legal all> 1281*5113495bSYour Name */ 1282*5113495bSYour Name 1283*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044 1284*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1285*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1286*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1287*5113495bSYour Name 1288*5113495bSYour Name 1289*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 1290*5113495bSYour Name 1291*5113495bSYour Name Consumer: WBM 1292*5113495bSYour Name Producer: SW/FW 1293*5113495bSYour Name 1294*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1295*5113495bSYour Name 1296*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1297*5113495bSYour Name descriptor OR link descriptor that is being pointed to 1298*5113495bSYour Name shall be returned after the frame has been processed. It 1299*5113495bSYour Name is used by WBM for routing purposes. 1300*5113495bSYour Name 1301*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1302*5113495bSYour Name to the WMB buffer idle list 1303*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1304*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 1305*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 1306*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1307*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 1308*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1309*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 1310*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1311*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 1312*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 1313*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 1314*5113495bSYour Name ring 0 1315*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 1316*5113495bSYour Name ring 1 1317*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 1318*5113495bSYour Name ring 2 1319*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 1320*5113495bSYour Name ring 3 1321*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 1322*5113495bSYour Name ring 4 1323*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 1324*5113495bSYour Name ring 5 1325*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 1326*5113495bSYour Name ring 6 1327*5113495bSYour Name 1328*5113495bSYour Name <legal 0-12> 1329*5113495bSYour Name */ 1330*5113495bSYour Name 1331*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 1332*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1333*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1334*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1335*5113495bSYour Name 1336*5113495bSYour Name 1337*5113495bSYour Name /* Description SW_BUFFER_COOKIE 1338*5113495bSYour Name 1339*5113495bSYour Name Cookie field exclusively used by SW. 1340*5113495bSYour Name 1341*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1342*5113495bSYour Name 1343*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 1344*5113495bSYour Name value on to other descriptors together with the physical 1345*5113495bSYour Name address 1346*5113495bSYour Name 1347*5113495bSYour Name Field can be used by SW to for example associate the buffers 1348*5113495bSYour Name physical address with the virtual address 1349*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 1350*5113495bSYour Name 1351*5113495bSYour Name 1352*5113495bSYour Name NOTE1: 1353*5113495bSYour Name The three most significant bits can have a special meaning 1354*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1355*5113495bSYour Name and field transmit_bw_restriction is set 1356*5113495bSYour Name 1357*5113495bSYour Name In case of NON punctured transmission: 1358*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1359*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1360*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1361*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1362*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1363*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1364*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1365*5113495bSYour Name 1366*5113495bSYour Name In case of punctured transmission: 1367*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1368*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1369*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1370*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1371*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1372*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1373*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1374*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1375*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1376*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1377*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1378*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1379*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1380*5113495bSYour Name 1381*5113495bSYour Name Note: a punctured transmission is indicated by the presence 1382*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1383*5113495bSYour Name 1384*5113495bSYour Name <legal all> 1385*5113495bSYour Name */ 1386*5113495bSYour Name 1387*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044 1388*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1389*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1390*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1391*5113495bSYour Name 1392*5113495bSYour Name 1393*5113495bSYour Name /* Description MPDU_LINK_POINTER_8 1394*5113495bSYour Name 1395*5113495bSYour Name Consumer: REO 1396*5113495bSYour Name Producer: REO 1397*5113495bSYour Name 1398*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 1399*5113495bSYour Name 1400*5113495bSYour Name */ 1401*5113495bSYour Name 1402*5113495bSYour Name 1403*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 1404*5113495bSYour Name 1405*5113495bSYour Name Details of the physical address of an MPDU link descriptor 1406*5113495bSYour Name 1407*5113495bSYour Name */ 1408*5113495bSYour Name 1409*5113495bSYour Name 1410*5113495bSYour Name /* Description BUFFER_ADDR_31_0 1411*5113495bSYour Name 1412*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1413*5113495bSYour Name descriptor OR Link Descriptor 1414*5113495bSYour Name 1415*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1416*5113495bSYour Name <legal all> 1417*5113495bSYour Name */ 1418*5113495bSYour Name 1419*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048 1420*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1421*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1422*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1423*5113495bSYour Name 1424*5113495bSYour Name 1425*5113495bSYour Name /* Description BUFFER_ADDR_39_32 1426*5113495bSYour Name 1427*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1428*5113495bSYour Name descriptor OR Link Descriptor 1429*5113495bSYour Name 1430*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1431*5113495bSYour Name <legal all> 1432*5113495bSYour Name */ 1433*5113495bSYour Name 1434*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c 1435*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1436*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1437*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1438*5113495bSYour Name 1439*5113495bSYour Name 1440*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 1441*5113495bSYour Name 1442*5113495bSYour Name Consumer: WBM 1443*5113495bSYour Name Producer: SW/FW 1444*5113495bSYour Name 1445*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1446*5113495bSYour Name 1447*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1448*5113495bSYour Name descriptor OR link descriptor that is being pointed to 1449*5113495bSYour Name shall be returned after the frame has been processed. It 1450*5113495bSYour Name is used by WBM for routing purposes. 1451*5113495bSYour Name 1452*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1453*5113495bSYour Name to the WMB buffer idle list 1454*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1455*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 1456*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 1457*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1458*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 1459*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1460*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 1461*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1462*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 1463*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 1464*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 1465*5113495bSYour Name ring 0 1466*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 1467*5113495bSYour Name ring 1 1468*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 1469*5113495bSYour Name ring 2 1470*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 1471*5113495bSYour Name ring 3 1472*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 1473*5113495bSYour Name ring 4 1474*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 1475*5113495bSYour Name ring 5 1476*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 1477*5113495bSYour Name ring 6 1478*5113495bSYour Name 1479*5113495bSYour Name <legal 0-12> 1480*5113495bSYour Name */ 1481*5113495bSYour Name 1482*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c 1483*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1484*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1485*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1486*5113495bSYour Name 1487*5113495bSYour Name 1488*5113495bSYour Name /* Description SW_BUFFER_COOKIE 1489*5113495bSYour Name 1490*5113495bSYour Name Cookie field exclusively used by SW. 1491*5113495bSYour Name 1492*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1493*5113495bSYour Name 1494*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 1495*5113495bSYour Name value on to other descriptors together with the physical 1496*5113495bSYour Name address 1497*5113495bSYour Name 1498*5113495bSYour Name Field can be used by SW to for example associate the buffers 1499*5113495bSYour Name physical address with the virtual address 1500*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 1501*5113495bSYour Name 1502*5113495bSYour Name 1503*5113495bSYour Name NOTE1: 1504*5113495bSYour Name The three most significant bits can have a special meaning 1505*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1506*5113495bSYour Name and field transmit_bw_restriction is set 1507*5113495bSYour Name 1508*5113495bSYour Name In case of NON punctured transmission: 1509*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1510*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1511*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1512*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1513*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1514*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1515*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1516*5113495bSYour Name 1517*5113495bSYour Name In case of punctured transmission: 1518*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1519*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1520*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1521*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1522*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1523*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1524*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1525*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1526*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1527*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1528*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1529*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1530*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1531*5113495bSYour Name 1532*5113495bSYour Name Note: a punctured transmission is indicated by the presence 1533*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1534*5113495bSYour Name 1535*5113495bSYour Name <legal all> 1536*5113495bSYour Name */ 1537*5113495bSYour Name 1538*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c 1539*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1540*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1541*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1542*5113495bSYour Name 1543*5113495bSYour Name 1544*5113495bSYour Name /* Description MPDU_LINK_POINTER_9 1545*5113495bSYour Name 1546*5113495bSYour Name Consumer: REO 1547*5113495bSYour Name Producer: REO 1548*5113495bSYour Name 1549*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 1550*5113495bSYour Name 1551*5113495bSYour Name */ 1552*5113495bSYour Name 1553*5113495bSYour Name 1554*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 1555*5113495bSYour Name 1556*5113495bSYour Name Details of the physical address of an MPDU link descriptor 1557*5113495bSYour Name 1558*5113495bSYour Name */ 1559*5113495bSYour Name 1560*5113495bSYour Name 1561*5113495bSYour Name /* Description BUFFER_ADDR_31_0 1562*5113495bSYour Name 1563*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1564*5113495bSYour Name descriptor OR Link Descriptor 1565*5113495bSYour Name 1566*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1567*5113495bSYour Name <legal all> 1568*5113495bSYour Name */ 1569*5113495bSYour Name 1570*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050 1571*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1572*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1573*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1574*5113495bSYour Name 1575*5113495bSYour Name 1576*5113495bSYour Name /* Description BUFFER_ADDR_39_32 1577*5113495bSYour Name 1578*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1579*5113495bSYour Name descriptor OR Link Descriptor 1580*5113495bSYour Name 1581*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1582*5113495bSYour Name <legal all> 1583*5113495bSYour Name */ 1584*5113495bSYour Name 1585*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054 1586*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1587*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1588*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1589*5113495bSYour Name 1590*5113495bSYour Name 1591*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 1592*5113495bSYour Name 1593*5113495bSYour Name Consumer: WBM 1594*5113495bSYour Name Producer: SW/FW 1595*5113495bSYour Name 1596*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1597*5113495bSYour Name 1598*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1599*5113495bSYour Name descriptor OR link descriptor that is being pointed to 1600*5113495bSYour Name shall be returned after the frame has been processed. It 1601*5113495bSYour Name is used by WBM for routing purposes. 1602*5113495bSYour Name 1603*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1604*5113495bSYour Name to the WMB buffer idle list 1605*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1606*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 1607*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 1608*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1609*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 1610*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1611*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 1612*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1613*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 1614*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 1615*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 1616*5113495bSYour Name ring 0 1617*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 1618*5113495bSYour Name ring 1 1619*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 1620*5113495bSYour Name ring 2 1621*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 1622*5113495bSYour Name ring 3 1623*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 1624*5113495bSYour Name ring 4 1625*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 1626*5113495bSYour Name ring 5 1627*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 1628*5113495bSYour Name ring 6 1629*5113495bSYour Name 1630*5113495bSYour Name <legal 0-12> 1631*5113495bSYour Name */ 1632*5113495bSYour Name 1633*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 1634*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1635*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1636*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1637*5113495bSYour Name 1638*5113495bSYour Name 1639*5113495bSYour Name /* Description SW_BUFFER_COOKIE 1640*5113495bSYour Name 1641*5113495bSYour Name Cookie field exclusively used by SW. 1642*5113495bSYour Name 1643*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1644*5113495bSYour Name 1645*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 1646*5113495bSYour Name value on to other descriptors together with the physical 1647*5113495bSYour Name address 1648*5113495bSYour Name 1649*5113495bSYour Name Field can be used by SW to for example associate the buffers 1650*5113495bSYour Name physical address with the virtual address 1651*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 1652*5113495bSYour Name 1653*5113495bSYour Name 1654*5113495bSYour Name NOTE1: 1655*5113495bSYour Name The three most significant bits can have a special meaning 1656*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1657*5113495bSYour Name and field transmit_bw_restriction is set 1658*5113495bSYour Name 1659*5113495bSYour Name In case of NON punctured transmission: 1660*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1661*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1662*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1663*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1664*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1665*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1666*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1667*5113495bSYour Name 1668*5113495bSYour Name In case of punctured transmission: 1669*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1670*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1671*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1672*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1673*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1674*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1675*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1676*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1677*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1678*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1679*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1680*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1681*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1682*5113495bSYour Name 1683*5113495bSYour Name Note: a punctured transmission is indicated by the presence 1684*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1685*5113495bSYour Name 1686*5113495bSYour Name <legal all> 1687*5113495bSYour Name */ 1688*5113495bSYour Name 1689*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054 1690*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1691*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1692*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1693*5113495bSYour Name 1694*5113495bSYour Name 1695*5113495bSYour Name /* Description MPDU_LINK_POINTER_10 1696*5113495bSYour Name 1697*5113495bSYour Name Consumer: REO 1698*5113495bSYour Name Producer: REO 1699*5113495bSYour Name 1700*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 1701*5113495bSYour Name 1702*5113495bSYour Name */ 1703*5113495bSYour Name 1704*5113495bSYour Name 1705*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 1706*5113495bSYour Name 1707*5113495bSYour Name Details of the physical address of an MPDU link descriptor 1708*5113495bSYour Name 1709*5113495bSYour Name */ 1710*5113495bSYour Name 1711*5113495bSYour Name 1712*5113495bSYour Name /* Description BUFFER_ADDR_31_0 1713*5113495bSYour Name 1714*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1715*5113495bSYour Name descriptor OR Link Descriptor 1716*5113495bSYour Name 1717*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1718*5113495bSYour Name <legal all> 1719*5113495bSYour Name */ 1720*5113495bSYour Name 1721*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058 1722*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1723*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1724*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1725*5113495bSYour Name 1726*5113495bSYour Name 1727*5113495bSYour Name /* Description BUFFER_ADDR_39_32 1728*5113495bSYour Name 1729*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1730*5113495bSYour Name descriptor OR Link Descriptor 1731*5113495bSYour Name 1732*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1733*5113495bSYour Name <legal all> 1734*5113495bSYour Name */ 1735*5113495bSYour Name 1736*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c 1737*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1738*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1739*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1740*5113495bSYour Name 1741*5113495bSYour Name 1742*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 1743*5113495bSYour Name 1744*5113495bSYour Name Consumer: WBM 1745*5113495bSYour Name Producer: SW/FW 1746*5113495bSYour Name 1747*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1748*5113495bSYour Name 1749*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1750*5113495bSYour Name descriptor OR link descriptor that is being pointed to 1751*5113495bSYour Name shall be returned after the frame has been processed. It 1752*5113495bSYour Name is used by WBM for routing purposes. 1753*5113495bSYour Name 1754*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1755*5113495bSYour Name to the WMB buffer idle list 1756*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1757*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 1758*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 1759*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1760*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 1761*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1762*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 1763*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1764*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 1765*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 1766*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 1767*5113495bSYour Name ring 0 1768*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 1769*5113495bSYour Name ring 1 1770*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 1771*5113495bSYour Name ring 2 1772*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 1773*5113495bSYour Name ring 3 1774*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 1775*5113495bSYour Name ring 4 1776*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 1777*5113495bSYour Name ring 5 1778*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 1779*5113495bSYour Name ring 6 1780*5113495bSYour Name 1781*5113495bSYour Name <legal 0-12> 1782*5113495bSYour Name */ 1783*5113495bSYour Name 1784*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c 1785*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1786*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1787*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1788*5113495bSYour Name 1789*5113495bSYour Name 1790*5113495bSYour Name /* Description SW_BUFFER_COOKIE 1791*5113495bSYour Name 1792*5113495bSYour Name Cookie field exclusively used by SW. 1793*5113495bSYour Name 1794*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1795*5113495bSYour Name 1796*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 1797*5113495bSYour Name value on to other descriptors together with the physical 1798*5113495bSYour Name address 1799*5113495bSYour Name 1800*5113495bSYour Name Field can be used by SW to for example associate the buffers 1801*5113495bSYour Name physical address with the virtual address 1802*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 1803*5113495bSYour Name 1804*5113495bSYour Name 1805*5113495bSYour Name NOTE1: 1806*5113495bSYour Name The three most significant bits can have a special meaning 1807*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1808*5113495bSYour Name and field transmit_bw_restriction is set 1809*5113495bSYour Name 1810*5113495bSYour Name In case of NON punctured transmission: 1811*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1812*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1813*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1814*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1815*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1816*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1817*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1818*5113495bSYour Name 1819*5113495bSYour Name In case of punctured transmission: 1820*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1821*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1822*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1823*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1824*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1825*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1826*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1827*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1828*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1829*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1830*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1831*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1832*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1833*5113495bSYour Name 1834*5113495bSYour Name Note: a punctured transmission is indicated by the presence 1835*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1836*5113495bSYour Name 1837*5113495bSYour Name <legal all> 1838*5113495bSYour Name */ 1839*5113495bSYour Name 1840*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c 1841*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1842*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1843*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1844*5113495bSYour Name 1845*5113495bSYour Name 1846*5113495bSYour Name /* Description MPDU_LINK_POINTER_11 1847*5113495bSYour Name 1848*5113495bSYour Name Consumer: REO 1849*5113495bSYour Name Producer: REO 1850*5113495bSYour Name 1851*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 1852*5113495bSYour Name 1853*5113495bSYour Name */ 1854*5113495bSYour Name 1855*5113495bSYour Name 1856*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 1857*5113495bSYour Name 1858*5113495bSYour Name Details of the physical address of an MPDU link descriptor 1859*5113495bSYour Name 1860*5113495bSYour Name */ 1861*5113495bSYour Name 1862*5113495bSYour Name 1863*5113495bSYour Name /* Description BUFFER_ADDR_31_0 1864*5113495bSYour Name 1865*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1866*5113495bSYour Name descriptor OR Link Descriptor 1867*5113495bSYour Name 1868*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1869*5113495bSYour Name <legal all> 1870*5113495bSYour Name */ 1871*5113495bSYour Name 1872*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060 1873*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1874*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1875*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1876*5113495bSYour Name 1877*5113495bSYour Name 1878*5113495bSYour Name /* Description BUFFER_ADDR_39_32 1879*5113495bSYour Name 1880*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1881*5113495bSYour Name descriptor OR Link Descriptor 1882*5113495bSYour Name 1883*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1884*5113495bSYour Name <legal all> 1885*5113495bSYour Name */ 1886*5113495bSYour Name 1887*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064 1888*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1889*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1890*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1891*5113495bSYour Name 1892*5113495bSYour Name 1893*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 1894*5113495bSYour Name 1895*5113495bSYour Name Consumer: WBM 1896*5113495bSYour Name Producer: SW/FW 1897*5113495bSYour Name 1898*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1899*5113495bSYour Name 1900*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1901*5113495bSYour Name descriptor OR link descriptor that is being pointed to 1902*5113495bSYour Name shall be returned after the frame has been processed. It 1903*5113495bSYour Name is used by WBM for routing purposes. 1904*5113495bSYour Name 1905*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1906*5113495bSYour Name to the WMB buffer idle list 1907*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1908*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 1909*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 1910*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1911*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 1912*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1913*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 1914*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1915*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 1916*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 1917*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 1918*5113495bSYour Name ring 0 1919*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 1920*5113495bSYour Name ring 1 1921*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 1922*5113495bSYour Name ring 2 1923*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 1924*5113495bSYour Name ring 3 1925*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 1926*5113495bSYour Name ring 4 1927*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 1928*5113495bSYour Name ring 5 1929*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 1930*5113495bSYour Name ring 6 1931*5113495bSYour Name 1932*5113495bSYour Name <legal 0-12> 1933*5113495bSYour Name */ 1934*5113495bSYour Name 1935*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 1936*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1937*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1938*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1939*5113495bSYour Name 1940*5113495bSYour Name 1941*5113495bSYour Name /* Description SW_BUFFER_COOKIE 1942*5113495bSYour Name 1943*5113495bSYour Name Cookie field exclusively used by SW. 1944*5113495bSYour Name 1945*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1946*5113495bSYour Name 1947*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 1948*5113495bSYour Name value on to other descriptors together with the physical 1949*5113495bSYour Name address 1950*5113495bSYour Name 1951*5113495bSYour Name Field can be used by SW to for example associate the buffers 1952*5113495bSYour Name physical address with the virtual address 1953*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 1954*5113495bSYour Name 1955*5113495bSYour Name 1956*5113495bSYour Name NOTE1: 1957*5113495bSYour Name The three most significant bits can have a special meaning 1958*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1959*5113495bSYour Name and field transmit_bw_restriction is set 1960*5113495bSYour Name 1961*5113495bSYour Name In case of NON punctured transmission: 1962*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1963*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1964*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1965*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1966*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1967*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1968*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1969*5113495bSYour Name 1970*5113495bSYour Name In case of punctured transmission: 1971*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1972*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1973*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1974*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1975*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1976*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1977*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1978*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1979*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1980*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1981*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1982*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1983*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1984*5113495bSYour Name 1985*5113495bSYour Name Note: a punctured transmission is indicated by the presence 1986*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1987*5113495bSYour Name 1988*5113495bSYour Name <legal all> 1989*5113495bSYour Name */ 1990*5113495bSYour Name 1991*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064 1992*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1993*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1994*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1995*5113495bSYour Name 1996*5113495bSYour Name 1997*5113495bSYour Name /* Description MPDU_LINK_POINTER_12 1998*5113495bSYour Name 1999*5113495bSYour Name Consumer: REO 2000*5113495bSYour Name Producer: REO 2001*5113495bSYour Name 2002*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 2003*5113495bSYour Name 2004*5113495bSYour Name */ 2005*5113495bSYour Name 2006*5113495bSYour Name 2007*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 2008*5113495bSYour Name 2009*5113495bSYour Name Details of the physical address of an MPDU link descriptor 2010*5113495bSYour Name 2011*5113495bSYour Name */ 2012*5113495bSYour Name 2013*5113495bSYour Name 2014*5113495bSYour Name /* Description BUFFER_ADDR_31_0 2015*5113495bSYour Name 2016*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 2017*5113495bSYour Name descriptor OR Link Descriptor 2018*5113495bSYour Name 2019*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2020*5113495bSYour Name <legal all> 2021*5113495bSYour Name */ 2022*5113495bSYour Name 2023*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068 2024*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2025*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 2026*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2027*5113495bSYour Name 2028*5113495bSYour Name 2029*5113495bSYour Name /* Description BUFFER_ADDR_39_32 2030*5113495bSYour Name 2031*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 2032*5113495bSYour Name descriptor OR Link Descriptor 2033*5113495bSYour Name 2034*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2035*5113495bSYour Name <legal all> 2036*5113495bSYour Name */ 2037*5113495bSYour Name 2038*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c 2039*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2040*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 2041*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2042*5113495bSYour Name 2043*5113495bSYour Name 2044*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 2045*5113495bSYour Name 2046*5113495bSYour Name Consumer: WBM 2047*5113495bSYour Name Producer: SW/FW 2048*5113495bSYour Name 2049*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2050*5113495bSYour Name 2051*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 2052*5113495bSYour Name descriptor OR link descriptor that is being pointed to 2053*5113495bSYour Name shall be returned after the frame has been processed. It 2054*5113495bSYour Name is used by WBM for routing purposes. 2055*5113495bSYour Name 2056*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2057*5113495bSYour Name to the WMB buffer idle list 2058*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 2059*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 2060*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 2061*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 2062*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 2063*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 2064*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 2065*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 2066*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 2067*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 2068*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 2069*5113495bSYour Name ring 0 2070*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 2071*5113495bSYour Name ring 1 2072*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 2073*5113495bSYour Name ring 2 2074*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 2075*5113495bSYour Name ring 3 2076*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 2077*5113495bSYour Name ring 4 2078*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 2079*5113495bSYour Name ring 5 2080*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 2081*5113495bSYour Name ring 6 2082*5113495bSYour Name 2083*5113495bSYour Name <legal 0-12> 2084*5113495bSYour Name */ 2085*5113495bSYour Name 2086*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c 2087*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2088*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 2089*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 2090*5113495bSYour Name 2091*5113495bSYour Name 2092*5113495bSYour Name /* Description SW_BUFFER_COOKIE 2093*5113495bSYour Name 2094*5113495bSYour Name Cookie field exclusively used by SW. 2095*5113495bSYour Name 2096*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2097*5113495bSYour Name 2098*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 2099*5113495bSYour Name value on to other descriptors together with the physical 2100*5113495bSYour Name address 2101*5113495bSYour Name 2102*5113495bSYour Name Field can be used by SW to for example associate the buffers 2103*5113495bSYour Name physical address with the virtual address 2104*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 2105*5113495bSYour Name 2106*5113495bSYour Name 2107*5113495bSYour Name NOTE1: 2108*5113495bSYour Name The three most significant bits can have a special meaning 2109*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 2110*5113495bSYour Name and field transmit_bw_restriction is set 2111*5113495bSYour Name 2112*5113495bSYour Name In case of NON punctured transmission: 2113*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 2114*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 2115*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 2116*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 2117*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 2118*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 2119*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 2120*5113495bSYour Name 2121*5113495bSYour Name In case of punctured transmission: 2122*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 2123*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 2124*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 2125*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 2126*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 2127*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 2128*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 2129*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 2130*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 2131*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 2132*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 2133*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 2134*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 2135*5113495bSYour Name 2136*5113495bSYour Name Note: a punctured transmission is indicated by the presence 2137*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 2138*5113495bSYour Name 2139*5113495bSYour Name <legal all> 2140*5113495bSYour Name */ 2141*5113495bSYour Name 2142*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c 2143*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 2144*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 2145*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 2146*5113495bSYour Name 2147*5113495bSYour Name 2148*5113495bSYour Name /* Description MPDU_LINK_POINTER_13 2149*5113495bSYour Name 2150*5113495bSYour Name Consumer: REO 2151*5113495bSYour Name Producer: REO 2152*5113495bSYour Name 2153*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 2154*5113495bSYour Name 2155*5113495bSYour Name */ 2156*5113495bSYour Name 2157*5113495bSYour Name 2158*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 2159*5113495bSYour Name 2160*5113495bSYour Name Details of the physical address of an MPDU link descriptor 2161*5113495bSYour Name 2162*5113495bSYour Name */ 2163*5113495bSYour Name 2164*5113495bSYour Name 2165*5113495bSYour Name /* Description BUFFER_ADDR_31_0 2166*5113495bSYour Name 2167*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 2168*5113495bSYour Name descriptor OR Link Descriptor 2169*5113495bSYour Name 2170*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2171*5113495bSYour Name <legal all> 2172*5113495bSYour Name */ 2173*5113495bSYour Name 2174*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070 2175*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2176*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 2177*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2178*5113495bSYour Name 2179*5113495bSYour Name 2180*5113495bSYour Name /* Description BUFFER_ADDR_39_32 2181*5113495bSYour Name 2182*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 2183*5113495bSYour Name descriptor OR Link Descriptor 2184*5113495bSYour Name 2185*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2186*5113495bSYour Name <legal all> 2187*5113495bSYour Name */ 2188*5113495bSYour Name 2189*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074 2190*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2191*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 2192*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2193*5113495bSYour Name 2194*5113495bSYour Name 2195*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 2196*5113495bSYour Name 2197*5113495bSYour Name Consumer: WBM 2198*5113495bSYour Name Producer: SW/FW 2199*5113495bSYour Name 2200*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2201*5113495bSYour Name 2202*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 2203*5113495bSYour Name descriptor OR link descriptor that is being pointed to 2204*5113495bSYour Name shall be returned after the frame has been processed. It 2205*5113495bSYour Name is used by WBM for routing purposes. 2206*5113495bSYour Name 2207*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2208*5113495bSYour Name to the WMB buffer idle list 2209*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 2210*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 2211*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 2212*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 2213*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 2214*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 2215*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 2216*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 2217*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 2218*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 2219*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 2220*5113495bSYour Name ring 0 2221*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 2222*5113495bSYour Name ring 1 2223*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 2224*5113495bSYour Name ring 2 2225*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 2226*5113495bSYour Name ring 3 2227*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 2228*5113495bSYour Name ring 4 2229*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 2230*5113495bSYour Name ring 5 2231*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 2232*5113495bSYour Name ring 6 2233*5113495bSYour Name 2234*5113495bSYour Name <legal 0-12> 2235*5113495bSYour Name */ 2236*5113495bSYour Name 2237*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 2238*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2239*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 2240*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 2241*5113495bSYour Name 2242*5113495bSYour Name 2243*5113495bSYour Name /* Description SW_BUFFER_COOKIE 2244*5113495bSYour Name 2245*5113495bSYour Name Cookie field exclusively used by SW. 2246*5113495bSYour Name 2247*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2248*5113495bSYour Name 2249*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 2250*5113495bSYour Name value on to other descriptors together with the physical 2251*5113495bSYour Name address 2252*5113495bSYour Name 2253*5113495bSYour Name Field can be used by SW to for example associate the buffers 2254*5113495bSYour Name physical address with the virtual address 2255*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 2256*5113495bSYour Name 2257*5113495bSYour Name 2258*5113495bSYour Name NOTE1: 2259*5113495bSYour Name The three most significant bits can have a special meaning 2260*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 2261*5113495bSYour Name and field transmit_bw_restriction is set 2262*5113495bSYour Name 2263*5113495bSYour Name In case of NON punctured transmission: 2264*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 2265*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 2266*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 2267*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 2268*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 2269*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 2270*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 2271*5113495bSYour Name 2272*5113495bSYour Name In case of punctured transmission: 2273*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 2274*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 2275*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 2276*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 2277*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 2278*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 2279*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 2280*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 2281*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 2282*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 2283*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 2284*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 2285*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 2286*5113495bSYour Name 2287*5113495bSYour Name Note: a punctured transmission is indicated by the presence 2288*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 2289*5113495bSYour Name 2290*5113495bSYour Name <legal all> 2291*5113495bSYour Name */ 2292*5113495bSYour Name 2293*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074 2294*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 2295*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 2296*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 2297*5113495bSYour Name 2298*5113495bSYour Name 2299*5113495bSYour Name /* Description MPDU_LINK_POINTER_14 2300*5113495bSYour Name 2301*5113495bSYour Name Consumer: REO 2302*5113495bSYour Name Producer: REO 2303*5113495bSYour Name 2304*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 2305*5113495bSYour Name 2306*5113495bSYour Name */ 2307*5113495bSYour Name 2308*5113495bSYour Name 2309*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 2310*5113495bSYour Name 2311*5113495bSYour Name Details of the physical address of an MPDU link descriptor 2312*5113495bSYour Name 2313*5113495bSYour Name */ 2314*5113495bSYour Name 2315*5113495bSYour Name 2316*5113495bSYour Name /* Description BUFFER_ADDR_31_0 2317*5113495bSYour Name 2318*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 2319*5113495bSYour Name descriptor OR Link Descriptor 2320*5113495bSYour Name 2321*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2322*5113495bSYour Name <legal all> 2323*5113495bSYour Name */ 2324*5113495bSYour Name 2325*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078 2326*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2327*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 2328*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2329*5113495bSYour Name 2330*5113495bSYour Name 2331*5113495bSYour Name /* Description BUFFER_ADDR_39_32 2332*5113495bSYour Name 2333*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 2334*5113495bSYour Name descriptor OR Link Descriptor 2335*5113495bSYour Name 2336*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2337*5113495bSYour Name <legal all> 2338*5113495bSYour Name */ 2339*5113495bSYour Name 2340*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c 2341*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2342*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 2343*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2344*5113495bSYour Name 2345*5113495bSYour Name 2346*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 2347*5113495bSYour Name 2348*5113495bSYour Name Consumer: WBM 2349*5113495bSYour Name Producer: SW/FW 2350*5113495bSYour Name 2351*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2352*5113495bSYour Name 2353*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 2354*5113495bSYour Name descriptor OR link descriptor that is being pointed to 2355*5113495bSYour Name shall be returned after the frame has been processed. It 2356*5113495bSYour Name is used by WBM for routing purposes. 2357*5113495bSYour Name 2358*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2359*5113495bSYour Name to the WMB buffer idle list 2360*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 2361*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 2362*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 2363*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 2364*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 2365*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 2366*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 2367*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 2368*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 2369*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 2370*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 2371*5113495bSYour Name ring 0 2372*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 2373*5113495bSYour Name ring 1 2374*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 2375*5113495bSYour Name ring 2 2376*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 2377*5113495bSYour Name ring 3 2378*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 2379*5113495bSYour Name ring 4 2380*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 2381*5113495bSYour Name ring 5 2382*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 2383*5113495bSYour Name ring 6 2384*5113495bSYour Name 2385*5113495bSYour Name <legal 0-12> 2386*5113495bSYour Name */ 2387*5113495bSYour Name 2388*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c 2389*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2390*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 2391*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 2392*5113495bSYour Name 2393*5113495bSYour Name 2394*5113495bSYour Name /* Description SW_BUFFER_COOKIE 2395*5113495bSYour Name 2396*5113495bSYour Name Cookie field exclusively used by SW. 2397*5113495bSYour Name 2398*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2399*5113495bSYour Name 2400*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 2401*5113495bSYour Name value on to other descriptors together with the physical 2402*5113495bSYour Name address 2403*5113495bSYour Name 2404*5113495bSYour Name Field can be used by SW to for example associate the buffers 2405*5113495bSYour Name physical address with the virtual address 2406*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 2407*5113495bSYour Name 2408*5113495bSYour Name 2409*5113495bSYour Name NOTE1: 2410*5113495bSYour Name The three most significant bits can have a special meaning 2411*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 2412*5113495bSYour Name and field transmit_bw_restriction is set 2413*5113495bSYour Name 2414*5113495bSYour Name In case of NON punctured transmission: 2415*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 2416*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 2417*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 2418*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 2419*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 2420*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 2421*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 2422*5113495bSYour Name 2423*5113495bSYour Name In case of punctured transmission: 2424*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 2425*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 2426*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 2427*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 2428*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 2429*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 2430*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 2431*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 2432*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 2433*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 2434*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 2435*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 2436*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 2437*5113495bSYour Name 2438*5113495bSYour Name Note: a punctured transmission is indicated by the presence 2439*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 2440*5113495bSYour Name 2441*5113495bSYour Name <legal all> 2442*5113495bSYour Name */ 2443*5113495bSYour Name 2444*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c 2445*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 2446*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 2447*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 2448*5113495bSYour Name 2449*5113495bSYour Name 2450*5113495bSYour Name 2451*5113495bSYour Name #endif // RX_REO_QUEUE_EXT 2452