1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _RX_REO_QUEUE_EXT_H_ 19 #define _RX_REO_QUEUE_EXT_H_ 20 #if !defined(__ASSEMBLER__) 21 #endif 22 23 #include "rx_mpdu_link_ptr.h" 24 #include "uniform_descriptor_header.h" 25 #define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32 26 27 28 struct rx_reo_queue_ext { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct uniform_descriptor_header descriptor_header; 31 uint32_t reserved_1a : 32; // [31:0] 32 struct rx_mpdu_link_ptr mpdu_link_pointer_0; 33 struct rx_mpdu_link_ptr mpdu_link_pointer_1; 34 struct rx_mpdu_link_ptr mpdu_link_pointer_2; 35 struct rx_mpdu_link_ptr mpdu_link_pointer_3; 36 struct rx_mpdu_link_ptr mpdu_link_pointer_4; 37 struct rx_mpdu_link_ptr mpdu_link_pointer_5; 38 struct rx_mpdu_link_ptr mpdu_link_pointer_6; 39 struct rx_mpdu_link_ptr mpdu_link_pointer_7; 40 struct rx_mpdu_link_ptr mpdu_link_pointer_8; 41 struct rx_mpdu_link_ptr mpdu_link_pointer_9; 42 struct rx_mpdu_link_ptr mpdu_link_pointer_10; 43 struct rx_mpdu_link_ptr mpdu_link_pointer_11; 44 struct rx_mpdu_link_ptr mpdu_link_pointer_12; 45 struct rx_mpdu_link_ptr mpdu_link_pointer_13; 46 struct rx_mpdu_link_ptr mpdu_link_pointer_14; 47 #else 48 struct uniform_descriptor_header descriptor_header; 49 uint32_t reserved_1a : 32; // [31:0] 50 struct rx_mpdu_link_ptr mpdu_link_pointer_0; 51 struct rx_mpdu_link_ptr mpdu_link_pointer_1; 52 struct rx_mpdu_link_ptr mpdu_link_pointer_2; 53 struct rx_mpdu_link_ptr mpdu_link_pointer_3; 54 struct rx_mpdu_link_ptr mpdu_link_pointer_4; 55 struct rx_mpdu_link_ptr mpdu_link_pointer_5; 56 struct rx_mpdu_link_ptr mpdu_link_pointer_6; 57 struct rx_mpdu_link_ptr mpdu_link_pointer_7; 58 struct rx_mpdu_link_ptr mpdu_link_pointer_8; 59 struct rx_mpdu_link_ptr mpdu_link_pointer_9; 60 struct rx_mpdu_link_ptr mpdu_link_pointer_10; 61 struct rx_mpdu_link_ptr mpdu_link_pointer_11; 62 struct rx_mpdu_link_ptr mpdu_link_pointer_12; 63 struct rx_mpdu_link_ptr mpdu_link_pointer_13; 64 struct rx_mpdu_link_ptr mpdu_link_pointer_14; 65 #endif 66 }; 67 68 69 /* Description DESCRIPTOR_HEADER 70 71 Details about which module owns this struct. 72 Note that sub field "Buffer_type" shall be set to "Receive_REO_queue_ext_descriptor" 73 74 */ 75 76 77 /* Description OWNER 78 79 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 80 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 81 82 The owner of this data structure: 83 <enum 0 WBM_owned> Buffer Manager currently owns this data 84 structure. 85 <enum 1 SW_OR_FW_owned> Software of FW currently owns this 86 data structure. 87 <enum 2 TQM_owned> Transmit Queue Manager currently owns 88 this data structure. 89 <enum 3 RXDMA_owned> Receive DMA currently owns this data 90 structure. 91 <enum 4 REO_owned> Reorder currently owns this data structure. 92 93 <enum 5 SWITCH_owned> SWITCH currently owns this data structure. 94 95 96 <legal 0-5> 97 */ 98 99 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 100 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_LSB 0 101 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MSB 3 102 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 103 104 105 /* Description BUFFER_TYPE 106 107 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 108 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 109 110 Field describing what contents format is of this descriptor 111 112 113 <enum 0 Transmit_MSDU_Link_descriptor> 114 <enum 1 Transmit_MPDU_Link_descriptor> 115 <enum 2 Transmit_MPDU_Queue_head_descriptor> 116 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 117 <enum 4 Transmit_flow_descriptor> 118 <enum 5 Transmit_buffer> NOT TO BE USED: 119 120 <enum 6 Receive_MSDU_Link_descriptor> 121 <enum 7 Receive_MPDU_Link_descriptor> 122 <enum 8 Receive_REO_queue_descriptor> 123 <enum 9 Receive_REO_queue_1k_descriptor> 124 <enum 10 Receive_REO_queue_ext_descriptor> 125 126 <enum 11 Receive_buffer> 127 128 <enum 12 Idle_link_list_entry> 129 130 <legal 0-12> 131 */ 132 133 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 134 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 135 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 136 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 137 138 139 /* Description TX_MPDU_QUEUE_NUMBER 140 141 Consumer: TQM/Debug 142 Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) 143 144 Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor 145 146 147 Indicates the MPDU queue ID to which this MPDU descriptor 148 belongs 149 Used for tracking and debugging 150 151 Hamilton and Waikiki used bits [19:0] of word 1 of 'TX_MPDU_LINK,' 152 word 16 of 'TX_MPDU_QUEUE_HEAD' and word 1 of 'TX_MPDU_QUEUE_EXT' 153 for this. 154 <legal all> 155 */ 156 157 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 158 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 159 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 160 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 161 162 163 /* Description RESERVED_0A 164 165 <legal 0> 166 */ 167 168 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 169 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 170 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 171 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 172 173 174 /* Description RESERVED_1A 175 176 <legal 0> 177 */ 178 179 #define RX_REO_QUEUE_EXT_RESERVED_1A_OFFSET 0x00000004 180 #define RX_REO_QUEUE_EXT_RESERVED_1A_LSB 0 181 #define RX_REO_QUEUE_EXT_RESERVED_1A_MSB 31 182 #define RX_REO_QUEUE_EXT_RESERVED_1A_MASK 0xffffffff 183 184 185 /* Description MPDU_LINK_POINTER_0 186 187 Consumer: REO 188 Producer: REO 189 190 Pointer to the next MPDU_link descriptor in the MPDU queue 191 192 */ 193 194 195 /* Description MPDU_LINK_DESC_ADDR_INFO 196 197 Details of the physical address of an MPDU link descriptor 198 199 */ 200 201 202 /* Description BUFFER_ADDR_31_0 203 204 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 205 descriptor OR Link Descriptor 206 207 In case of 'NULL' pointer, this field is set to 0 208 <legal all> 209 */ 210 211 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008 212 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 213 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 214 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 215 216 217 /* Description BUFFER_ADDR_39_32 218 219 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 220 descriptor OR Link Descriptor 221 222 In case of 'NULL' pointer, this field is set to 0 223 <legal all> 224 */ 225 226 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c 227 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 228 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 229 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 230 231 232 /* Description RETURN_BUFFER_MANAGER 233 234 Consumer: WBM 235 Producer: SW/FW 236 237 In case of 'NULL' pointer, this field is set to 0 238 239 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 240 descriptor OR link descriptor that is being pointed to 241 shall be returned after the frame has been processed. It 242 is used by WBM for routing purposes. 243 244 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 245 to the WMB buffer idle list 246 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 247 to the WBM idle link descriptor idle list, where the chip 248 0 WBM is chosen in case of a multi-chip config 249 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 250 to the chip 1 WBM idle link descriptor idle list 251 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 252 to the chip 2 WBM idle link descriptor idle list 253 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 254 returned to chip 3 WBM idle link descriptor idle list 255 <enum 4 FW_BM> This buffer shall be returned to the FW 256 <enum 5 SW0_BM> This buffer shall be returned to the SW, 257 ring 0 258 <enum 6 SW1_BM> This buffer shall be returned to the SW, 259 ring 1 260 <enum 7 SW2_BM> This buffer shall be returned to the SW, 261 ring 2 262 <enum 8 SW3_BM> This buffer shall be returned to the SW, 263 ring 3 264 <enum 9 SW4_BM> This buffer shall be returned to the SW, 265 ring 4 266 <enum 10 SW5_BM> This buffer shall be returned to the SW, 267 ring 5 268 <enum 11 SW6_BM> This buffer shall be returned to the SW, 269 ring 6 270 271 <legal 0-12> 272 */ 273 274 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c 275 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 276 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 277 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 278 279 280 /* Description SW_BUFFER_COOKIE 281 282 Cookie field exclusively used by SW. 283 284 In case of 'NULL' pointer, this field is set to 0 285 286 HW ignores the contents, accept that it passes the programmed 287 value on to other descriptors together with the physical 288 address 289 290 Field can be used by SW to for example associate the buffers 291 physical address with the virtual address 292 The bit definitions as used by SW are within SW HLD specification 293 294 295 NOTE1: 296 The three most significant bits can have a special meaning 297 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 298 and field transmit_bw_restriction is set 299 300 In case of NON punctured transmission: 301 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 302 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 303 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 304 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 305 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 306 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 307 Sw_buffer_cookie[19:18] = 2'b11: reserved 308 309 In case of punctured transmission: 310 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 311 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 312 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 313 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 314 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 315 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 316 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 317 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 318 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 319 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 320 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 321 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 322 Sw_buffer_cookie[19:18] = 2'b11: reserved 323 324 Note: a punctured transmission is indicated by the presence 325 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 326 327 <legal all> 328 */ 329 330 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c 331 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 332 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 333 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 334 335 336 /* Description MPDU_LINK_POINTER_1 337 338 Consumer: REO 339 Producer: REO 340 341 Pointer to the next MPDU_link descriptor in the MPDU queue 342 343 */ 344 345 346 /* Description MPDU_LINK_DESC_ADDR_INFO 347 348 Details of the physical address of an MPDU link descriptor 349 350 */ 351 352 353 /* Description BUFFER_ADDR_31_0 354 355 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 356 descriptor OR Link Descriptor 357 358 In case of 'NULL' pointer, this field is set to 0 359 <legal all> 360 */ 361 362 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 363 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 364 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 365 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 366 367 368 /* Description BUFFER_ADDR_39_32 369 370 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 371 descriptor OR Link Descriptor 372 373 In case of 'NULL' pointer, this field is set to 0 374 <legal all> 375 */ 376 377 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 378 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 379 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 380 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 381 382 383 /* Description RETURN_BUFFER_MANAGER 384 385 Consumer: WBM 386 Producer: SW/FW 387 388 In case of 'NULL' pointer, this field is set to 0 389 390 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 391 descriptor OR link descriptor that is being pointed to 392 shall be returned after the frame has been processed. It 393 is used by WBM for routing purposes. 394 395 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 396 to the WMB buffer idle list 397 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 398 to the WBM idle link descriptor idle list, where the chip 399 0 WBM is chosen in case of a multi-chip config 400 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 401 to the chip 1 WBM idle link descriptor idle list 402 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 403 to the chip 2 WBM idle link descriptor idle list 404 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 405 returned to chip 3 WBM idle link descriptor idle list 406 <enum 4 FW_BM> This buffer shall be returned to the FW 407 <enum 5 SW0_BM> This buffer shall be returned to the SW, 408 ring 0 409 <enum 6 SW1_BM> This buffer shall be returned to the SW, 410 ring 1 411 <enum 7 SW2_BM> This buffer shall be returned to the SW, 412 ring 2 413 <enum 8 SW3_BM> This buffer shall be returned to the SW, 414 ring 3 415 <enum 9 SW4_BM> This buffer shall be returned to the SW, 416 ring 4 417 <enum 10 SW5_BM> This buffer shall be returned to the SW, 418 ring 5 419 <enum 11 SW6_BM> This buffer shall be returned to the SW, 420 ring 6 421 422 <legal 0-12> 423 */ 424 425 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 426 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 427 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 428 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 429 430 431 /* Description SW_BUFFER_COOKIE 432 433 Cookie field exclusively used by SW. 434 435 In case of 'NULL' pointer, this field is set to 0 436 437 HW ignores the contents, accept that it passes the programmed 438 value on to other descriptors together with the physical 439 address 440 441 Field can be used by SW to for example associate the buffers 442 physical address with the virtual address 443 The bit definitions as used by SW are within SW HLD specification 444 445 446 NOTE1: 447 The three most significant bits can have a special meaning 448 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 449 and field transmit_bw_restriction is set 450 451 In case of NON punctured transmission: 452 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 453 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 454 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 455 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 456 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 457 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 458 Sw_buffer_cookie[19:18] = 2'b11: reserved 459 460 In case of punctured transmission: 461 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 462 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 463 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 464 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 465 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 466 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 467 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 468 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 469 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 470 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 471 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 472 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 473 Sw_buffer_cookie[19:18] = 2'b11: reserved 474 475 Note: a punctured transmission is indicated by the presence 476 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 477 478 <legal all> 479 */ 480 481 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 482 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 483 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 484 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 485 486 487 /* Description MPDU_LINK_POINTER_2 488 489 Consumer: REO 490 Producer: REO 491 492 Pointer to the next MPDU_link descriptor in the MPDU queue 493 494 */ 495 496 497 /* Description MPDU_LINK_DESC_ADDR_INFO 498 499 Details of the physical address of an MPDU link descriptor 500 501 */ 502 503 504 /* Description BUFFER_ADDR_31_0 505 506 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 507 descriptor OR Link Descriptor 508 509 In case of 'NULL' pointer, this field is set to 0 510 <legal all> 511 */ 512 513 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018 514 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 515 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 516 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 517 518 519 /* Description BUFFER_ADDR_39_32 520 521 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 522 descriptor OR Link Descriptor 523 524 In case of 'NULL' pointer, this field is set to 0 525 <legal all> 526 */ 527 528 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c 529 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 530 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 531 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 532 533 534 /* Description RETURN_BUFFER_MANAGER 535 536 Consumer: WBM 537 Producer: SW/FW 538 539 In case of 'NULL' pointer, this field is set to 0 540 541 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 542 descriptor OR link descriptor that is being pointed to 543 shall be returned after the frame has been processed. It 544 is used by WBM for routing purposes. 545 546 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 547 to the WMB buffer idle list 548 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 549 to the WBM idle link descriptor idle list, where the chip 550 0 WBM is chosen in case of a multi-chip config 551 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 552 to the chip 1 WBM idle link descriptor idle list 553 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 554 to the chip 2 WBM idle link descriptor idle list 555 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 556 returned to chip 3 WBM idle link descriptor idle list 557 <enum 4 FW_BM> This buffer shall be returned to the FW 558 <enum 5 SW0_BM> This buffer shall be returned to the SW, 559 ring 0 560 <enum 6 SW1_BM> This buffer shall be returned to the SW, 561 ring 1 562 <enum 7 SW2_BM> This buffer shall be returned to the SW, 563 ring 2 564 <enum 8 SW3_BM> This buffer shall be returned to the SW, 565 ring 3 566 <enum 9 SW4_BM> This buffer shall be returned to the SW, 567 ring 4 568 <enum 10 SW5_BM> This buffer shall be returned to the SW, 569 ring 5 570 <enum 11 SW6_BM> This buffer shall be returned to the SW, 571 ring 6 572 573 <legal 0-12> 574 */ 575 576 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c 577 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 578 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 579 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 580 581 582 /* Description SW_BUFFER_COOKIE 583 584 Cookie field exclusively used by SW. 585 586 In case of 'NULL' pointer, this field is set to 0 587 588 HW ignores the contents, accept that it passes the programmed 589 value on to other descriptors together with the physical 590 address 591 592 Field can be used by SW to for example associate the buffers 593 physical address with the virtual address 594 The bit definitions as used by SW are within SW HLD specification 595 596 597 NOTE1: 598 The three most significant bits can have a special meaning 599 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 600 and field transmit_bw_restriction is set 601 602 In case of NON punctured transmission: 603 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 604 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 605 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 606 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 607 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 608 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 609 Sw_buffer_cookie[19:18] = 2'b11: reserved 610 611 In case of punctured transmission: 612 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 613 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 614 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 615 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 616 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 617 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 618 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 619 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 620 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 621 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 622 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 623 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 624 Sw_buffer_cookie[19:18] = 2'b11: reserved 625 626 Note: a punctured transmission is indicated by the presence 627 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 628 629 <legal all> 630 */ 631 632 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c 633 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 634 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 635 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 636 637 638 /* Description MPDU_LINK_POINTER_3 639 640 Consumer: REO 641 Producer: REO 642 643 Pointer to the next MPDU_link descriptor in the MPDU queue 644 645 */ 646 647 648 /* Description MPDU_LINK_DESC_ADDR_INFO 649 650 Details of the physical address of an MPDU link descriptor 651 652 */ 653 654 655 /* Description BUFFER_ADDR_31_0 656 657 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 658 descriptor OR Link Descriptor 659 660 In case of 'NULL' pointer, this field is set to 0 661 <legal all> 662 */ 663 664 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020 665 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 666 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 667 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 668 669 670 /* Description BUFFER_ADDR_39_32 671 672 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 673 descriptor OR Link Descriptor 674 675 In case of 'NULL' pointer, this field is set to 0 676 <legal all> 677 */ 678 679 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024 680 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 681 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 682 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 683 684 685 /* Description RETURN_BUFFER_MANAGER 686 687 Consumer: WBM 688 Producer: SW/FW 689 690 In case of 'NULL' pointer, this field is set to 0 691 692 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 693 descriptor OR link descriptor that is being pointed to 694 shall be returned after the frame has been processed. It 695 is used by WBM for routing purposes. 696 697 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 698 to the WMB buffer idle list 699 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 700 to the WBM idle link descriptor idle list, where the chip 701 0 WBM is chosen in case of a multi-chip config 702 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 703 to the chip 1 WBM idle link descriptor idle list 704 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 705 to the chip 2 WBM idle link descriptor idle list 706 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 707 returned to chip 3 WBM idle link descriptor idle list 708 <enum 4 FW_BM> This buffer shall be returned to the FW 709 <enum 5 SW0_BM> This buffer shall be returned to the SW, 710 ring 0 711 <enum 6 SW1_BM> This buffer shall be returned to the SW, 712 ring 1 713 <enum 7 SW2_BM> This buffer shall be returned to the SW, 714 ring 2 715 <enum 8 SW3_BM> This buffer shall be returned to the SW, 716 ring 3 717 <enum 9 SW4_BM> This buffer shall be returned to the SW, 718 ring 4 719 <enum 10 SW5_BM> This buffer shall be returned to the SW, 720 ring 5 721 <enum 11 SW6_BM> This buffer shall be returned to the SW, 722 ring 6 723 724 <legal 0-12> 725 */ 726 727 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 728 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 729 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 730 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 731 732 733 /* Description SW_BUFFER_COOKIE 734 735 Cookie field exclusively used by SW. 736 737 In case of 'NULL' pointer, this field is set to 0 738 739 HW ignores the contents, accept that it passes the programmed 740 value on to other descriptors together with the physical 741 address 742 743 Field can be used by SW to for example associate the buffers 744 physical address with the virtual address 745 The bit definitions as used by SW are within SW HLD specification 746 747 748 NOTE1: 749 The three most significant bits can have a special meaning 750 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 751 and field transmit_bw_restriction is set 752 753 In case of NON punctured transmission: 754 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 755 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 756 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 757 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 758 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 759 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 760 Sw_buffer_cookie[19:18] = 2'b11: reserved 761 762 In case of punctured transmission: 763 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 764 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 765 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 766 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 767 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 768 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 769 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 770 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 771 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 772 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 773 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 774 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 775 Sw_buffer_cookie[19:18] = 2'b11: reserved 776 777 Note: a punctured transmission is indicated by the presence 778 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 779 780 <legal all> 781 */ 782 783 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024 784 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 785 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 786 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 787 788 789 /* Description MPDU_LINK_POINTER_4 790 791 Consumer: REO 792 Producer: REO 793 794 Pointer to the next MPDU_link descriptor in the MPDU queue 795 796 */ 797 798 799 /* Description MPDU_LINK_DESC_ADDR_INFO 800 801 Details of the physical address of an MPDU link descriptor 802 803 */ 804 805 806 /* Description BUFFER_ADDR_31_0 807 808 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 809 descriptor OR Link Descriptor 810 811 In case of 'NULL' pointer, this field is set to 0 812 <legal all> 813 */ 814 815 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028 816 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 817 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 818 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 819 820 821 /* Description BUFFER_ADDR_39_32 822 823 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 824 descriptor OR Link Descriptor 825 826 In case of 'NULL' pointer, this field is set to 0 827 <legal all> 828 */ 829 830 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c 831 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 832 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 833 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 834 835 836 /* Description RETURN_BUFFER_MANAGER 837 838 Consumer: WBM 839 Producer: SW/FW 840 841 In case of 'NULL' pointer, this field is set to 0 842 843 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 844 descriptor OR link descriptor that is being pointed to 845 shall be returned after the frame has been processed. It 846 is used by WBM for routing purposes. 847 848 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 849 to the WMB buffer idle list 850 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 851 to the WBM idle link descriptor idle list, where the chip 852 0 WBM is chosen in case of a multi-chip config 853 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 854 to the chip 1 WBM idle link descriptor idle list 855 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 856 to the chip 2 WBM idle link descriptor idle list 857 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 858 returned to chip 3 WBM idle link descriptor idle list 859 <enum 4 FW_BM> This buffer shall be returned to the FW 860 <enum 5 SW0_BM> This buffer shall be returned to the SW, 861 ring 0 862 <enum 6 SW1_BM> This buffer shall be returned to the SW, 863 ring 1 864 <enum 7 SW2_BM> This buffer shall be returned to the SW, 865 ring 2 866 <enum 8 SW3_BM> This buffer shall be returned to the SW, 867 ring 3 868 <enum 9 SW4_BM> This buffer shall be returned to the SW, 869 ring 4 870 <enum 10 SW5_BM> This buffer shall be returned to the SW, 871 ring 5 872 <enum 11 SW6_BM> This buffer shall be returned to the SW, 873 ring 6 874 875 <legal 0-12> 876 */ 877 878 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c 879 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 880 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 881 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 882 883 884 /* Description SW_BUFFER_COOKIE 885 886 Cookie field exclusively used by SW. 887 888 In case of 'NULL' pointer, this field is set to 0 889 890 HW ignores the contents, accept that it passes the programmed 891 value on to other descriptors together with the physical 892 address 893 894 Field can be used by SW to for example associate the buffers 895 physical address with the virtual address 896 The bit definitions as used by SW are within SW HLD specification 897 898 899 NOTE1: 900 The three most significant bits can have a special meaning 901 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 902 and field transmit_bw_restriction is set 903 904 In case of NON punctured transmission: 905 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 906 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 907 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 908 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 909 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 910 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 911 Sw_buffer_cookie[19:18] = 2'b11: reserved 912 913 In case of punctured transmission: 914 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 915 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 916 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 917 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 918 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 919 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 920 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 921 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 922 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 923 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 924 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 925 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 926 Sw_buffer_cookie[19:18] = 2'b11: reserved 927 928 Note: a punctured transmission is indicated by the presence 929 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 930 931 <legal all> 932 */ 933 934 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c 935 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 936 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 937 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 938 939 940 /* Description MPDU_LINK_POINTER_5 941 942 Consumer: REO 943 Producer: REO 944 945 Pointer to the next MPDU_link descriptor in the MPDU queue 946 947 */ 948 949 950 /* Description MPDU_LINK_DESC_ADDR_INFO 951 952 Details of the physical address of an MPDU link descriptor 953 954 */ 955 956 957 /* Description BUFFER_ADDR_31_0 958 959 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 960 descriptor OR Link Descriptor 961 962 In case of 'NULL' pointer, this field is set to 0 963 <legal all> 964 */ 965 966 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030 967 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 968 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 969 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 970 971 972 /* Description BUFFER_ADDR_39_32 973 974 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 975 descriptor OR Link Descriptor 976 977 In case of 'NULL' pointer, this field is set to 0 978 <legal all> 979 */ 980 981 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034 982 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 983 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 984 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 985 986 987 /* Description RETURN_BUFFER_MANAGER 988 989 Consumer: WBM 990 Producer: SW/FW 991 992 In case of 'NULL' pointer, this field is set to 0 993 994 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 995 descriptor OR link descriptor that is being pointed to 996 shall be returned after the frame has been processed. It 997 is used by WBM for routing purposes. 998 999 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1000 to the WMB buffer idle list 1001 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1002 to the WBM idle link descriptor idle list, where the chip 1003 0 WBM is chosen in case of a multi-chip config 1004 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1005 to the chip 1 WBM idle link descriptor idle list 1006 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1007 to the chip 2 WBM idle link descriptor idle list 1008 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1009 returned to chip 3 WBM idle link descriptor idle list 1010 <enum 4 FW_BM> This buffer shall be returned to the FW 1011 <enum 5 SW0_BM> This buffer shall be returned to the SW, 1012 ring 0 1013 <enum 6 SW1_BM> This buffer shall be returned to the SW, 1014 ring 1 1015 <enum 7 SW2_BM> This buffer shall be returned to the SW, 1016 ring 2 1017 <enum 8 SW3_BM> This buffer shall be returned to the SW, 1018 ring 3 1019 <enum 9 SW4_BM> This buffer shall be returned to the SW, 1020 ring 4 1021 <enum 10 SW5_BM> This buffer shall be returned to the SW, 1022 ring 5 1023 <enum 11 SW6_BM> This buffer shall be returned to the SW, 1024 ring 6 1025 1026 <legal 0-12> 1027 */ 1028 1029 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 1030 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1031 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1032 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1033 1034 1035 /* Description SW_BUFFER_COOKIE 1036 1037 Cookie field exclusively used by SW. 1038 1039 In case of 'NULL' pointer, this field is set to 0 1040 1041 HW ignores the contents, accept that it passes the programmed 1042 value on to other descriptors together with the physical 1043 address 1044 1045 Field can be used by SW to for example associate the buffers 1046 physical address with the virtual address 1047 The bit definitions as used by SW are within SW HLD specification 1048 1049 1050 NOTE1: 1051 The three most significant bits can have a special meaning 1052 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1053 and field transmit_bw_restriction is set 1054 1055 In case of NON punctured transmission: 1056 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1057 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1058 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1059 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1060 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1061 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1062 Sw_buffer_cookie[19:18] = 2'b11: reserved 1063 1064 In case of punctured transmission: 1065 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1066 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1067 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1068 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1069 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1070 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1071 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1072 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1073 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1074 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1075 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1076 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1077 Sw_buffer_cookie[19:18] = 2'b11: reserved 1078 1079 Note: a punctured transmission is indicated by the presence 1080 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1081 1082 <legal all> 1083 */ 1084 1085 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034 1086 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1087 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1088 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1089 1090 1091 /* Description MPDU_LINK_POINTER_6 1092 1093 Consumer: REO 1094 Producer: REO 1095 1096 Pointer to the next MPDU_link descriptor in the MPDU queue 1097 1098 */ 1099 1100 1101 /* Description MPDU_LINK_DESC_ADDR_INFO 1102 1103 Details of the physical address of an MPDU link descriptor 1104 1105 */ 1106 1107 1108 /* Description BUFFER_ADDR_31_0 1109 1110 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1111 descriptor OR Link Descriptor 1112 1113 In case of 'NULL' pointer, this field is set to 0 1114 <legal all> 1115 */ 1116 1117 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038 1118 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1119 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1120 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1121 1122 1123 /* Description BUFFER_ADDR_39_32 1124 1125 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1126 descriptor OR Link Descriptor 1127 1128 In case of 'NULL' pointer, this field is set to 0 1129 <legal all> 1130 */ 1131 1132 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c 1133 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1134 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1135 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1136 1137 1138 /* Description RETURN_BUFFER_MANAGER 1139 1140 Consumer: WBM 1141 Producer: SW/FW 1142 1143 In case of 'NULL' pointer, this field is set to 0 1144 1145 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1146 descriptor OR link descriptor that is being pointed to 1147 shall be returned after the frame has been processed. It 1148 is used by WBM for routing purposes. 1149 1150 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1151 to the WMB buffer idle list 1152 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1153 to the WBM idle link descriptor idle list, where the chip 1154 0 WBM is chosen in case of a multi-chip config 1155 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1156 to the chip 1 WBM idle link descriptor idle list 1157 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1158 to the chip 2 WBM idle link descriptor idle list 1159 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1160 returned to chip 3 WBM idle link descriptor idle list 1161 <enum 4 FW_BM> This buffer shall be returned to the FW 1162 <enum 5 SW0_BM> This buffer shall be returned to the SW, 1163 ring 0 1164 <enum 6 SW1_BM> This buffer shall be returned to the SW, 1165 ring 1 1166 <enum 7 SW2_BM> This buffer shall be returned to the SW, 1167 ring 2 1168 <enum 8 SW3_BM> This buffer shall be returned to the SW, 1169 ring 3 1170 <enum 9 SW4_BM> This buffer shall be returned to the SW, 1171 ring 4 1172 <enum 10 SW5_BM> This buffer shall be returned to the SW, 1173 ring 5 1174 <enum 11 SW6_BM> This buffer shall be returned to the SW, 1175 ring 6 1176 1177 <legal 0-12> 1178 */ 1179 1180 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c 1181 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1182 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1183 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1184 1185 1186 /* Description SW_BUFFER_COOKIE 1187 1188 Cookie field exclusively used by SW. 1189 1190 In case of 'NULL' pointer, this field is set to 0 1191 1192 HW ignores the contents, accept that it passes the programmed 1193 value on to other descriptors together with the physical 1194 address 1195 1196 Field can be used by SW to for example associate the buffers 1197 physical address with the virtual address 1198 The bit definitions as used by SW are within SW HLD specification 1199 1200 1201 NOTE1: 1202 The three most significant bits can have a special meaning 1203 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1204 and field transmit_bw_restriction is set 1205 1206 In case of NON punctured transmission: 1207 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1208 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1209 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1210 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1211 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1212 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1213 Sw_buffer_cookie[19:18] = 2'b11: reserved 1214 1215 In case of punctured transmission: 1216 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1217 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1218 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1219 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1220 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1221 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1222 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1223 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1224 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1225 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1226 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1227 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1228 Sw_buffer_cookie[19:18] = 2'b11: reserved 1229 1230 Note: a punctured transmission is indicated by the presence 1231 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1232 1233 <legal all> 1234 */ 1235 1236 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c 1237 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1238 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1239 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1240 1241 1242 /* Description MPDU_LINK_POINTER_7 1243 1244 Consumer: REO 1245 Producer: REO 1246 1247 Pointer to the next MPDU_link descriptor in the MPDU queue 1248 1249 */ 1250 1251 1252 /* Description MPDU_LINK_DESC_ADDR_INFO 1253 1254 Details of the physical address of an MPDU link descriptor 1255 1256 */ 1257 1258 1259 /* Description BUFFER_ADDR_31_0 1260 1261 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1262 descriptor OR Link Descriptor 1263 1264 In case of 'NULL' pointer, this field is set to 0 1265 <legal all> 1266 */ 1267 1268 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040 1269 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1270 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1271 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1272 1273 1274 /* Description BUFFER_ADDR_39_32 1275 1276 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1277 descriptor OR Link Descriptor 1278 1279 In case of 'NULL' pointer, this field is set to 0 1280 <legal all> 1281 */ 1282 1283 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044 1284 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1285 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1286 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1287 1288 1289 /* Description RETURN_BUFFER_MANAGER 1290 1291 Consumer: WBM 1292 Producer: SW/FW 1293 1294 In case of 'NULL' pointer, this field is set to 0 1295 1296 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1297 descriptor OR link descriptor that is being pointed to 1298 shall be returned after the frame has been processed. It 1299 is used by WBM for routing purposes. 1300 1301 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1302 to the WMB buffer idle list 1303 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1304 to the WBM idle link descriptor idle list, where the chip 1305 0 WBM is chosen in case of a multi-chip config 1306 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1307 to the chip 1 WBM idle link descriptor idle list 1308 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1309 to the chip 2 WBM idle link descriptor idle list 1310 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1311 returned to chip 3 WBM idle link descriptor idle list 1312 <enum 4 FW_BM> This buffer shall be returned to the FW 1313 <enum 5 SW0_BM> This buffer shall be returned to the SW, 1314 ring 0 1315 <enum 6 SW1_BM> This buffer shall be returned to the SW, 1316 ring 1 1317 <enum 7 SW2_BM> This buffer shall be returned to the SW, 1318 ring 2 1319 <enum 8 SW3_BM> This buffer shall be returned to the SW, 1320 ring 3 1321 <enum 9 SW4_BM> This buffer shall be returned to the SW, 1322 ring 4 1323 <enum 10 SW5_BM> This buffer shall be returned to the SW, 1324 ring 5 1325 <enum 11 SW6_BM> This buffer shall be returned to the SW, 1326 ring 6 1327 1328 <legal 0-12> 1329 */ 1330 1331 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 1332 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1333 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1334 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1335 1336 1337 /* Description SW_BUFFER_COOKIE 1338 1339 Cookie field exclusively used by SW. 1340 1341 In case of 'NULL' pointer, this field is set to 0 1342 1343 HW ignores the contents, accept that it passes the programmed 1344 value on to other descriptors together with the physical 1345 address 1346 1347 Field can be used by SW to for example associate the buffers 1348 physical address with the virtual address 1349 The bit definitions as used by SW are within SW HLD specification 1350 1351 1352 NOTE1: 1353 The three most significant bits can have a special meaning 1354 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1355 and field transmit_bw_restriction is set 1356 1357 In case of NON punctured transmission: 1358 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1359 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1360 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1361 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1362 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1363 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1364 Sw_buffer_cookie[19:18] = 2'b11: reserved 1365 1366 In case of punctured transmission: 1367 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1368 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1369 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1370 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1371 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1372 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1373 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1374 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1375 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1376 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1377 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1378 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1379 Sw_buffer_cookie[19:18] = 2'b11: reserved 1380 1381 Note: a punctured transmission is indicated by the presence 1382 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1383 1384 <legal all> 1385 */ 1386 1387 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044 1388 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1389 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1390 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1391 1392 1393 /* Description MPDU_LINK_POINTER_8 1394 1395 Consumer: REO 1396 Producer: REO 1397 1398 Pointer to the next MPDU_link descriptor in the MPDU queue 1399 1400 */ 1401 1402 1403 /* Description MPDU_LINK_DESC_ADDR_INFO 1404 1405 Details of the physical address of an MPDU link descriptor 1406 1407 */ 1408 1409 1410 /* Description BUFFER_ADDR_31_0 1411 1412 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1413 descriptor OR Link Descriptor 1414 1415 In case of 'NULL' pointer, this field is set to 0 1416 <legal all> 1417 */ 1418 1419 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048 1420 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1421 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1422 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1423 1424 1425 /* Description BUFFER_ADDR_39_32 1426 1427 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1428 descriptor OR Link Descriptor 1429 1430 In case of 'NULL' pointer, this field is set to 0 1431 <legal all> 1432 */ 1433 1434 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c 1435 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1436 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1437 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1438 1439 1440 /* Description RETURN_BUFFER_MANAGER 1441 1442 Consumer: WBM 1443 Producer: SW/FW 1444 1445 In case of 'NULL' pointer, this field is set to 0 1446 1447 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1448 descriptor OR link descriptor that is being pointed to 1449 shall be returned after the frame has been processed. It 1450 is used by WBM for routing purposes. 1451 1452 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1453 to the WMB buffer idle list 1454 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1455 to the WBM idle link descriptor idle list, where the chip 1456 0 WBM is chosen in case of a multi-chip config 1457 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1458 to the chip 1 WBM idle link descriptor idle list 1459 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1460 to the chip 2 WBM idle link descriptor idle list 1461 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1462 returned to chip 3 WBM idle link descriptor idle list 1463 <enum 4 FW_BM> This buffer shall be returned to the FW 1464 <enum 5 SW0_BM> This buffer shall be returned to the SW, 1465 ring 0 1466 <enum 6 SW1_BM> This buffer shall be returned to the SW, 1467 ring 1 1468 <enum 7 SW2_BM> This buffer shall be returned to the SW, 1469 ring 2 1470 <enum 8 SW3_BM> This buffer shall be returned to the SW, 1471 ring 3 1472 <enum 9 SW4_BM> This buffer shall be returned to the SW, 1473 ring 4 1474 <enum 10 SW5_BM> This buffer shall be returned to the SW, 1475 ring 5 1476 <enum 11 SW6_BM> This buffer shall be returned to the SW, 1477 ring 6 1478 1479 <legal 0-12> 1480 */ 1481 1482 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c 1483 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1484 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1485 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1486 1487 1488 /* Description SW_BUFFER_COOKIE 1489 1490 Cookie field exclusively used by SW. 1491 1492 In case of 'NULL' pointer, this field is set to 0 1493 1494 HW ignores the contents, accept that it passes the programmed 1495 value on to other descriptors together with the physical 1496 address 1497 1498 Field can be used by SW to for example associate the buffers 1499 physical address with the virtual address 1500 The bit definitions as used by SW are within SW HLD specification 1501 1502 1503 NOTE1: 1504 The three most significant bits can have a special meaning 1505 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1506 and field transmit_bw_restriction is set 1507 1508 In case of NON punctured transmission: 1509 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1510 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1511 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1512 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1513 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1514 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1515 Sw_buffer_cookie[19:18] = 2'b11: reserved 1516 1517 In case of punctured transmission: 1518 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1519 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1520 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1521 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1522 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1523 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1524 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1525 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1526 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1527 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1528 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1529 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1530 Sw_buffer_cookie[19:18] = 2'b11: reserved 1531 1532 Note: a punctured transmission is indicated by the presence 1533 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1534 1535 <legal all> 1536 */ 1537 1538 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c 1539 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1540 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1541 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1542 1543 1544 /* Description MPDU_LINK_POINTER_9 1545 1546 Consumer: REO 1547 Producer: REO 1548 1549 Pointer to the next MPDU_link descriptor in the MPDU queue 1550 1551 */ 1552 1553 1554 /* Description MPDU_LINK_DESC_ADDR_INFO 1555 1556 Details of the physical address of an MPDU link descriptor 1557 1558 */ 1559 1560 1561 /* Description BUFFER_ADDR_31_0 1562 1563 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1564 descriptor OR Link Descriptor 1565 1566 In case of 'NULL' pointer, this field is set to 0 1567 <legal all> 1568 */ 1569 1570 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050 1571 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1572 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1573 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1574 1575 1576 /* Description BUFFER_ADDR_39_32 1577 1578 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1579 descriptor OR Link Descriptor 1580 1581 In case of 'NULL' pointer, this field is set to 0 1582 <legal all> 1583 */ 1584 1585 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054 1586 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1587 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1588 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1589 1590 1591 /* Description RETURN_BUFFER_MANAGER 1592 1593 Consumer: WBM 1594 Producer: SW/FW 1595 1596 In case of 'NULL' pointer, this field is set to 0 1597 1598 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1599 descriptor OR link descriptor that is being pointed to 1600 shall be returned after the frame has been processed. It 1601 is used by WBM for routing purposes. 1602 1603 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1604 to the WMB buffer idle list 1605 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1606 to the WBM idle link descriptor idle list, where the chip 1607 0 WBM is chosen in case of a multi-chip config 1608 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1609 to the chip 1 WBM idle link descriptor idle list 1610 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1611 to the chip 2 WBM idle link descriptor idle list 1612 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1613 returned to chip 3 WBM idle link descriptor idle list 1614 <enum 4 FW_BM> This buffer shall be returned to the FW 1615 <enum 5 SW0_BM> This buffer shall be returned to the SW, 1616 ring 0 1617 <enum 6 SW1_BM> This buffer shall be returned to the SW, 1618 ring 1 1619 <enum 7 SW2_BM> This buffer shall be returned to the SW, 1620 ring 2 1621 <enum 8 SW3_BM> This buffer shall be returned to the SW, 1622 ring 3 1623 <enum 9 SW4_BM> This buffer shall be returned to the SW, 1624 ring 4 1625 <enum 10 SW5_BM> This buffer shall be returned to the SW, 1626 ring 5 1627 <enum 11 SW6_BM> This buffer shall be returned to the SW, 1628 ring 6 1629 1630 <legal 0-12> 1631 */ 1632 1633 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 1634 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1635 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1636 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1637 1638 1639 /* Description SW_BUFFER_COOKIE 1640 1641 Cookie field exclusively used by SW. 1642 1643 In case of 'NULL' pointer, this field is set to 0 1644 1645 HW ignores the contents, accept that it passes the programmed 1646 value on to other descriptors together with the physical 1647 address 1648 1649 Field can be used by SW to for example associate the buffers 1650 physical address with the virtual address 1651 The bit definitions as used by SW are within SW HLD specification 1652 1653 1654 NOTE1: 1655 The three most significant bits can have a special meaning 1656 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1657 and field transmit_bw_restriction is set 1658 1659 In case of NON punctured transmission: 1660 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1661 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1662 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1663 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1664 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1665 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1666 Sw_buffer_cookie[19:18] = 2'b11: reserved 1667 1668 In case of punctured transmission: 1669 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1670 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1671 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1672 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1673 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1674 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1675 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1676 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1677 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1678 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1679 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1680 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1681 Sw_buffer_cookie[19:18] = 2'b11: reserved 1682 1683 Note: a punctured transmission is indicated by the presence 1684 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1685 1686 <legal all> 1687 */ 1688 1689 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054 1690 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1691 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1692 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1693 1694 1695 /* Description MPDU_LINK_POINTER_10 1696 1697 Consumer: REO 1698 Producer: REO 1699 1700 Pointer to the next MPDU_link descriptor in the MPDU queue 1701 1702 */ 1703 1704 1705 /* Description MPDU_LINK_DESC_ADDR_INFO 1706 1707 Details of the physical address of an MPDU link descriptor 1708 1709 */ 1710 1711 1712 /* Description BUFFER_ADDR_31_0 1713 1714 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1715 descriptor OR Link Descriptor 1716 1717 In case of 'NULL' pointer, this field is set to 0 1718 <legal all> 1719 */ 1720 1721 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058 1722 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1723 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1724 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1725 1726 1727 /* Description BUFFER_ADDR_39_32 1728 1729 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1730 descriptor OR Link Descriptor 1731 1732 In case of 'NULL' pointer, this field is set to 0 1733 <legal all> 1734 */ 1735 1736 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c 1737 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1738 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1739 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1740 1741 1742 /* Description RETURN_BUFFER_MANAGER 1743 1744 Consumer: WBM 1745 Producer: SW/FW 1746 1747 In case of 'NULL' pointer, this field is set to 0 1748 1749 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1750 descriptor OR link descriptor that is being pointed to 1751 shall be returned after the frame has been processed. It 1752 is used by WBM for routing purposes. 1753 1754 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1755 to the WMB buffer idle list 1756 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1757 to the WBM idle link descriptor idle list, where the chip 1758 0 WBM is chosen in case of a multi-chip config 1759 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1760 to the chip 1 WBM idle link descriptor idle list 1761 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1762 to the chip 2 WBM idle link descriptor idle list 1763 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1764 returned to chip 3 WBM idle link descriptor idle list 1765 <enum 4 FW_BM> This buffer shall be returned to the FW 1766 <enum 5 SW0_BM> This buffer shall be returned to the SW, 1767 ring 0 1768 <enum 6 SW1_BM> This buffer shall be returned to the SW, 1769 ring 1 1770 <enum 7 SW2_BM> This buffer shall be returned to the SW, 1771 ring 2 1772 <enum 8 SW3_BM> This buffer shall be returned to the SW, 1773 ring 3 1774 <enum 9 SW4_BM> This buffer shall be returned to the SW, 1775 ring 4 1776 <enum 10 SW5_BM> This buffer shall be returned to the SW, 1777 ring 5 1778 <enum 11 SW6_BM> This buffer shall be returned to the SW, 1779 ring 6 1780 1781 <legal 0-12> 1782 */ 1783 1784 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c 1785 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1786 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1787 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1788 1789 1790 /* Description SW_BUFFER_COOKIE 1791 1792 Cookie field exclusively used by SW. 1793 1794 In case of 'NULL' pointer, this field is set to 0 1795 1796 HW ignores the contents, accept that it passes the programmed 1797 value on to other descriptors together with the physical 1798 address 1799 1800 Field can be used by SW to for example associate the buffers 1801 physical address with the virtual address 1802 The bit definitions as used by SW are within SW HLD specification 1803 1804 1805 NOTE1: 1806 The three most significant bits can have a special meaning 1807 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1808 and field transmit_bw_restriction is set 1809 1810 In case of NON punctured transmission: 1811 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1812 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1813 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1814 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1815 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1816 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1817 Sw_buffer_cookie[19:18] = 2'b11: reserved 1818 1819 In case of punctured transmission: 1820 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1821 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1822 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1823 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1824 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1825 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1826 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1827 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1828 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1829 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1830 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1831 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1832 Sw_buffer_cookie[19:18] = 2'b11: reserved 1833 1834 Note: a punctured transmission is indicated by the presence 1835 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1836 1837 <legal all> 1838 */ 1839 1840 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c 1841 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1842 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1843 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1844 1845 1846 /* Description MPDU_LINK_POINTER_11 1847 1848 Consumer: REO 1849 Producer: REO 1850 1851 Pointer to the next MPDU_link descriptor in the MPDU queue 1852 1853 */ 1854 1855 1856 /* Description MPDU_LINK_DESC_ADDR_INFO 1857 1858 Details of the physical address of an MPDU link descriptor 1859 1860 */ 1861 1862 1863 /* Description BUFFER_ADDR_31_0 1864 1865 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1866 descriptor OR Link Descriptor 1867 1868 In case of 'NULL' pointer, this field is set to 0 1869 <legal all> 1870 */ 1871 1872 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060 1873 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1874 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1875 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1876 1877 1878 /* Description BUFFER_ADDR_39_32 1879 1880 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1881 descriptor OR Link Descriptor 1882 1883 In case of 'NULL' pointer, this field is set to 0 1884 <legal all> 1885 */ 1886 1887 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064 1888 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1889 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1890 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1891 1892 1893 /* Description RETURN_BUFFER_MANAGER 1894 1895 Consumer: WBM 1896 Producer: SW/FW 1897 1898 In case of 'NULL' pointer, this field is set to 0 1899 1900 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1901 descriptor OR link descriptor that is being pointed to 1902 shall be returned after the frame has been processed. It 1903 is used by WBM for routing purposes. 1904 1905 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1906 to the WMB buffer idle list 1907 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1908 to the WBM idle link descriptor idle list, where the chip 1909 0 WBM is chosen in case of a multi-chip config 1910 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1911 to the chip 1 WBM idle link descriptor idle list 1912 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1913 to the chip 2 WBM idle link descriptor idle list 1914 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1915 returned to chip 3 WBM idle link descriptor idle list 1916 <enum 4 FW_BM> This buffer shall be returned to the FW 1917 <enum 5 SW0_BM> This buffer shall be returned to the SW, 1918 ring 0 1919 <enum 6 SW1_BM> This buffer shall be returned to the SW, 1920 ring 1 1921 <enum 7 SW2_BM> This buffer shall be returned to the SW, 1922 ring 2 1923 <enum 8 SW3_BM> This buffer shall be returned to the SW, 1924 ring 3 1925 <enum 9 SW4_BM> This buffer shall be returned to the SW, 1926 ring 4 1927 <enum 10 SW5_BM> This buffer shall be returned to the SW, 1928 ring 5 1929 <enum 11 SW6_BM> This buffer shall be returned to the SW, 1930 ring 6 1931 1932 <legal 0-12> 1933 */ 1934 1935 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 1936 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1937 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1938 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1939 1940 1941 /* Description SW_BUFFER_COOKIE 1942 1943 Cookie field exclusively used by SW. 1944 1945 In case of 'NULL' pointer, this field is set to 0 1946 1947 HW ignores the contents, accept that it passes the programmed 1948 value on to other descriptors together with the physical 1949 address 1950 1951 Field can be used by SW to for example associate the buffers 1952 physical address with the virtual address 1953 The bit definitions as used by SW are within SW HLD specification 1954 1955 1956 NOTE1: 1957 The three most significant bits can have a special meaning 1958 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1959 and field transmit_bw_restriction is set 1960 1961 In case of NON punctured transmission: 1962 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1963 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1964 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1965 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1966 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1967 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1968 Sw_buffer_cookie[19:18] = 2'b11: reserved 1969 1970 In case of punctured transmission: 1971 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1972 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1973 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1974 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1975 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1976 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1977 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1978 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1979 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1980 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1981 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1982 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1983 Sw_buffer_cookie[19:18] = 2'b11: reserved 1984 1985 Note: a punctured transmission is indicated by the presence 1986 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1987 1988 <legal all> 1989 */ 1990 1991 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064 1992 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1993 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1994 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1995 1996 1997 /* Description MPDU_LINK_POINTER_12 1998 1999 Consumer: REO 2000 Producer: REO 2001 2002 Pointer to the next MPDU_link descriptor in the MPDU queue 2003 2004 */ 2005 2006 2007 /* Description MPDU_LINK_DESC_ADDR_INFO 2008 2009 Details of the physical address of an MPDU link descriptor 2010 2011 */ 2012 2013 2014 /* Description BUFFER_ADDR_31_0 2015 2016 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 2017 descriptor OR Link Descriptor 2018 2019 In case of 'NULL' pointer, this field is set to 0 2020 <legal all> 2021 */ 2022 2023 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068 2024 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2025 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 2026 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2027 2028 2029 /* Description BUFFER_ADDR_39_32 2030 2031 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 2032 descriptor OR Link Descriptor 2033 2034 In case of 'NULL' pointer, this field is set to 0 2035 <legal all> 2036 */ 2037 2038 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c 2039 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2040 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 2041 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2042 2043 2044 /* Description RETURN_BUFFER_MANAGER 2045 2046 Consumer: WBM 2047 Producer: SW/FW 2048 2049 In case of 'NULL' pointer, this field is set to 0 2050 2051 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 2052 descriptor OR link descriptor that is being pointed to 2053 shall be returned after the frame has been processed. It 2054 is used by WBM for routing purposes. 2055 2056 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2057 to the WMB buffer idle list 2058 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 2059 to the WBM idle link descriptor idle list, where the chip 2060 0 WBM is chosen in case of a multi-chip config 2061 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 2062 to the chip 1 WBM idle link descriptor idle list 2063 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 2064 to the chip 2 WBM idle link descriptor idle list 2065 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 2066 returned to chip 3 WBM idle link descriptor idle list 2067 <enum 4 FW_BM> This buffer shall be returned to the FW 2068 <enum 5 SW0_BM> This buffer shall be returned to the SW, 2069 ring 0 2070 <enum 6 SW1_BM> This buffer shall be returned to the SW, 2071 ring 1 2072 <enum 7 SW2_BM> This buffer shall be returned to the SW, 2073 ring 2 2074 <enum 8 SW3_BM> This buffer shall be returned to the SW, 2075 ring 3 2076 <enum 9 SW4_BM> This buffer shall be returned to the SW, 2077 ring 4 2078 <enum 10 SW5_BM> This buffer shall be returned to the SW, 2079 ring 5 2080 <enum 11 SW6_BM> This buffer shall be returned to the SW, 2081 ring 6 2082 2083 <legal 0-12> 2084 */ 2085 2086 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c 2087 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2088 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 2089 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 2090 2091 2092 /* Description SW_BUFFER_COOKIE 2093 2094 Cookie field exclusively used by SW. 2095 2096 In case of 'NULL' pointer, this field is set to 0 2097 2098 HW ignores the contents, accept that it passes the programmed 2099 value on to other descriptors together with the physical 2100 address 2101 2102 Field can be used by SW to for example associate the buffers 2103 physical address with the virtual address 2104 The bit definitions as used by SW are within SW HLD specification 2105 2106 2107 NOTE1: 2108 The three most significant bits can have a special meaning 2109 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 2110 and field transmit_bw_restriction is set 2111 2112 In case of NON punctured transmission: 2113 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 2114 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 2115 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 2116 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 2117 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 2118 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 2119 Sw_buffer_cookie[19:18] = 2'b11: reserved 2120 2121 In case of punctured transmission: 2122 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 2123 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 2124 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 2125 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 2126 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 2127 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 2128 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 2129 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 2130 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 2131 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 2132 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 2133 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 2134 Sw_buffer_cookie[19:18] = 2'b11: reserved 2135 2136 Note: a punctured transmission is indicated by the presence 2137 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 2138 2139 <legal all> 2140 */ 2141 2142 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c 2143 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 2144 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 2145 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 2146 2147 2148 /* Description MPDU_LINK_POINTER_13 2149 2150 Consumer: REO 2151 Producer: REO 2152 2153 Pointer to the next MPDU_link descriptor in the MPDU queue 2154 2155 */ 2156 2157 2158 /* Description MPDU_LINK_DESC_ADDR_INFO 2159 2160 Details of the physical address of an MPDU link descriptor 2161 2162 */ 2163 2164 2165 /* Description BUFFER_ADDR_31_0 2166 2167 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 2168 descriptor OR Link Descriptor 2169 2170 In case of 'NULL' pointer, this field is set to 0 2171 <legal all> 2172 */ 2173 2174 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070 2175 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2176 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 2177 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2178 2179 2180 /* Description BUFFER_ADDR_39_32 2181 2182 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 2183 descriptor OR Link Descriptor 2184 2185 In case of 'NULL' pointer, this field is set to 0 2186 <legal all> 2187 */ 2188 2189 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074 2190 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2191 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 2192 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2193 2194 2195 /* Description RETURN_BUFFER_MANAGER 2196 2197 Consumer: WBM 2198 Producer: SW/FW 2199 2200 In case of 'NULL' pointer, this field is set to 0 2201 2202 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 2203 descriptor OR link descriptor that is being pointed to 2204 shall be returned after the frame has been processed. It 2205 is used by WBM for routing purposes. 2206 2207 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2208 to the WMB buffer idle list 2209 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 2210 to the WBM idle link descriptor idle list, where the chip 2211 0 WBM is chosen in case of a multi-chip config 2212 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 2213 to the chip 1 WBM idle link descriptor idle list 2214 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 2215 to the chip 2 WBM idle link descriptor idle list 2216 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 2217 returned to chip 3 WBM idle link descriptor idle list 2218 <enum 4 FW_BM> This buffer shall be returned to the FW 2219 <enum 5 SW0_BM> This buffer shall be returned to the SW, 2220 ring 0 2221 <enum 6 SW1_BM> This buffer shall be returned to the SW, 2222 ring 1 2223 <enum 7 SW2_BM> This buffer shall be returned to the SW, 2224 ring 2 2225 <enum 8 SW3_BM> This buffer shall be returned to the SW, 2226 ring 3 2227 <enum 9 SW4_BM> This buffer shall be returned to the SW, 2228 ring 4 2229 <enum 10 SW5_BM> This buffer shall be returned to the SW, 2230 ring 5 2231 <enum 11 SW6_BM> This buffer shall be returned to the SW, 2232 ring 6 2233 2234 <legal 0-12> 2235 */ 2236 2237 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 2238 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2239 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 2240 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 2241 2242 2243 /* Description SW_BUFFER_COOKIE 2244 2245 Cookie field exclusively used by SW. 2246 2247 In case of 'NULL' pointer, this field is set to 0 2248 2249 HW ignores the contents, accept that it passes the programmed 2250 value on to other descriptors together with the physical 2251 address 2252 2253 Field can be used by SW to for example associate the buffers 2254 physical address with the virtual address 2255 The bit definitions as used by SW are within SW HLD specification 2256 2257 2258 NOTE1: 2259 The three most significant bits can have a special meaning 2260 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 2261 and field transmit_bw_restriction is set 2262 2263 In case of NON punctured transmission: 2264 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 2265 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 2266 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 2267 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 2268 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 2269 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 2270 Sw_buffer_cookie[19:18] = 2'b11: reserved 2271 2272 In case of punctured transmission: 2273 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 2274 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 2275 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 2276 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 2277 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 2278 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 2279 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 2280 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 2281 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 2282 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 2283 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 2284 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 2285 Sw_buffer_cookie[19:18] = 2'b11: reserved 2286 2287 Note: a punctured transmission is indicated by the presence 2288 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 2289 2290 <legal all> 2291 */ 2292 2293 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074 2294 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 2295 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 2296 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 2297 2298 2299 /* Description MPDU_LINK_POINTER_14 2300 2301 Consumer: REO 2302 Producer: REO 2303 2304 Pointer to the next MPDU_link descriptor in the MPDU queue 2305 2306 */ 2307 2308 2309 /* Description MPDU_LINK_DESC_ADDR_INFO 2310 2311 Details of the physical address of an MPDU link descriptor 2312 2313 */ 2314 2315 2316 /* Description BUFFER_ADDR_31_0 2317 2318 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 2319 descriptor OR Link Descriptor 2320 2321 In case of 'NULL' pointer, this field is set to 0 2322 <legal all> 2323 */ 2324 2325 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078 2326 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2327 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 2328 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2329 2330 2331 /* Description BUFFER_ADDR_39_32 2332 2333 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 2334 descriptor OR Link Descriptor 2335 2336 In case of 'NULL' pointer, this field is set to 0 2337 <legal all> 2338 */ 2339 2340 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c 2341 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2342 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 2343 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2344 2345 2346 /* Description RETURN_BUFFER_MANAGER 2347 2348 Consumer: WBM 2349 Producer: SW/FW 2350 2351 In case of 'NULL' pointer, this field is set to 0 2352 2353 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 2354 descriptor OR link descriptor that is being pointed to 2355 shall be returned after the frame has been processed. It 2356 is used by WBM for routing purposes. 2357 2358 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2359 to the WMB buffer idle list 2360 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 2361 to the WBM idle link descriptor idle list, where the chip 2362 0 WBM is chosen in case of a multi-chip config 2363 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 2364 to the chip 1 WBM idle link descriptor idle list 2365 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 2366 to the chip 2 WBM idle link descriptor idle list 2367 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 2368 returned to chip 3 WBM idle link descriptor idle list 2369 <enum 4 FW_BM> This buffer shall be returned to the FW 2370 <enum 5 SW0_BM> This buffer shall be returned to the SW, 2371 ring 0 2372 <enum 6 SW1_BM> This buffer shall be returned to the SW, 2373 ring 1 2374 <enum 7 SW2_BM> This buffer shall be returned to the SW, 2375 ring 2 2376 <enum 8 SW3_BM> This buffer shall be returned to the SW, 2377 ring 3 2378 <enum 9 SW4_BM> This buffer shall be returned to the SW, 2379 ring 4 2380 <enum 10 SW5_BM> This buffer shall be returned to the SW, 2381 ring 5 2382 <enum 11 SW6_BM> This buffer shall be returned to the SW, 2383 ring 6 2384 2385 <legal 0-12> 2386 */ 2387 2388 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c 2389 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2390 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 2391 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 2392 2393 2394 /* Description SW_BUFFER_COOKIE 2395 2396 Cookie field exclusively used by SW. 2397 2398 In case of 'NULL' pointer, this field is set to 0 2399 2400 HW ignores the contents, accept that it passes the programmed 2401 value on to other descriptors together with the physical 2402 address 2403 2404 Field can be used by SW to for example associate the buffers 2405 physical address with the virtual address 2406 The bit definitions as used by SW are within SW HLD specification 2407 2408 2409 NOTE1: 2410 The three most significant bits can have a special meaning 2411 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 2412 and field transmit_bw_restriction is set 2413 2414 In case of NON punctured transmission: 2415 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 2416 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 2417 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 2418 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 2419 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 2420 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 2421 Sw_buffer_cookie[19:18] = 2'b11: reserved 2422 2423 In case of punctured transmission: 2424 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 2425 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 2426 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 2427 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 2428 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 2429 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 2430 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 2431 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 2432 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 2433 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 2434 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 2435 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 2436 Sw_buffer_cookie[19:18] = 2'b11: reserved 2437 2438 Note: a punctured transmission is indicated by the presence 2439 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 2440 2441 <legal all> 2442 */ 2443 2444 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c 2445 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 2446 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 2447 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 2448 2449 2450 2451 #endif // RX_REO_QUEUE_EXT 2452