1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ 27 #define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1 32 33 34 struct rx_rxpcu_classification_overview { 35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 36 uint32_t filter_pass_mpdus : 1, // [0:0] 37 filter_pass_mpdus_fcs_ok : 1, // [1:1] 38 monitor_direct_mpdus : 1, // [2:2] 39 monitor_direct_mpdus_fcs_ok : 1, // [3:3] 40 monitor_other_mpdus : 1, // [4:4] 41 monitor_other_mpdus_fcs_ok : 1, // [5:5] 42 phyrx_abort_received : 1, // [6:6] 43 filter_pass_monitor_ovrd_mpdus : 1, // [7:7] 44 filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, // [8:8] 45 reserved_0 : 7, // [15:9] 46 phy_ppdu_id : 16; // [31:16] 47 #else 48 uint32_t phy_ppdu_id : 16, // [31:16] 49 reserved_0 : 7, // [15:9] 50 filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, // [8:8] 51 filter_pass_monitor_ovrd_mpdus : 1, // [7:7] 52 phyrx_abort_received : 1, // [6:6] 53 monitor_other_mpdus_fcs_ok : 1, // [5:5] 54 monitor_other_mpdus : 1, // [4:4] 55 monitor_direct_mpdus_fcs_ok : 1, // [3:3] 56 monitor_direct_mpdus : 1, // [2:2] 57 filter_pass_mpdus_fcs_ok : 1, // [1:1] 58 filter_pass_mpdus : 1; // [0:0] 59 #endif 60 }; 61 62 63 /* Description FILTER_PASS_MPDUS 64 65 When set, at least one Filter Pass MPDU has been received. 66 FCS might or might not have been passing. 67 68 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 69 this field is the "OR of all the users. 70 <legal all> 71 */ 72 73 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_OFFSET 0x00000000 74 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_LSB 0 75 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MSB 0 76 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MASK 0x00000001 77 78 79 /* Description FILTER_PASS_MPDUS_FCS_OK 80 81 When set, at least one Filter Pass MPDU has been received 82 that has a correct FCS. 83 84 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 85 this field is the "OR of all the users. 86 87 <legal all> 88 */ 89 90 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 91 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_LSB 1 92 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MSB 1 93 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 94 95 96 /* Description MONITOR_DIRECT_MPDUS 97 98 When set, at least one Monitor Direct MPDU has been received. 99 FCS might or might not have been passing 100 101 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 102 this field is the "OR of all the users. 103 <legal all> 104 */ 105 106 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 107 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_LSB 2 108 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MSB 2 109 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MASK 0x00000004 110 111 112 /* Description MONITOR_DIRECT_MPDUS_FCS_OK 113 114 When set, at least one Monitor Direct MPDU has been received 115 that has a correct FCS. 116 117 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 118 this field is the "OR of all the users. 119 120 <legal all> 121 */ 122 123 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 124 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 125 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 126 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 127 128 129 /* Description MONITOR_OTHER_MPDUS 130 131 When set, at least one Monitor Direct MPDU has been received. 132 FCS might or might not have been passing. 133 134 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 135 this field is the "OR of all the users. 136 <legal all> 137 */ 138 139 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 140 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_LSB 4 141 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MSB 4 142 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MASK 0x00000010 143 144 145 /* Description MONITOR_OTHER_MPDUS_FCS_OK 146 147 When set, at least one Monitor Direct MPDU has been received 148 that has a correct FCS. 149 150 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 151 this field is the "OR of all the users. 152 <legal all> 153 */ 154 155 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 156 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 157 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 158 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 159 160 161 /* Description PHYRX_ABORT_RECEIVED 162 163 When set, PPDU reception was aborted by the PHY 164 <legal all> 165 */ 166 167 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 168 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_LSB 6 169 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MSB 6 170 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MASK 0x00000040 171 172 173 /* Description FILTER_PASS_MONITOR_OVRD_MPDUS 174 175 When set, at least one 'Filter Pass Monitor Override' MPDU 176 has been received. FCS might or might not have been passing. 177 178 179 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 180 this field is the "OR of all the users. 181 <legal all> 182 */ 183 184 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000 185 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 186 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 187 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080 188 189 190 /* Description FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK 191 192 When set, at least one 'Filter Pass Monitor Override' MPDU 193 has been received that has a correct FCS. 194 195 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 196 this field is the "OR of all the users. 197 198 <legal all> 199 */ 200 201 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000 202 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 203 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 204 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100 205 206 207 /* Description RESERVED_0 208 209 <legal 0> 210 */ 211 212 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_OFFSET 0x00000000 213 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_LSB 9 214 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MSB 15 215 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MASK 0x0000fe00 216 217 218 /* Description PHY_PPDU_ID 219 220 A ppdu counter value that PHY increments for every PPDU 221 received. The counter value wraps around 222 <legal all> 223 */ 224 225 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_OFFSET 0x00000000 226 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_LSB 16 227 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MSB 31 228 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MASK 0xffff0000 229 230 231 232 #endif // RX_RXPCU_CLASSIFICATION_OVERVIEW 233