1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RXPCU_PPDU_END_INFO_H_ 27 #define _RXPCU_PPDU_END_INFO_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "phyrx_abort_request_info.h" 32 #include "macrx_abort_request_info.h" 33 #include "rxpcu_ppdu_end_layout_info.h" 34 #define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 28 35 36 #define NUM_OF_QWORDS_RXPCU_PPDU_END_INFO 14 37 38 39 struct rxpcu_ppdu_end_info { 40 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 41 uint32_t wb_timestamp_lower_32 : 32; // [31:0] 42 uint32_t wb_timestamp_upper_32 : 32; // [31:0] 43 uint32_t rx_antenna : 24, // [23:0] 44 tx_ht_vht_ack : 1, // [24:24] 45 unsupported_mu_nc : 1, // [25:25] 46 otp_txbf_disable : 1, // [26:26] 47 previous_tlv_corrupted : 1, // [27:27] 48 phyrx_abort_request_info_valid : 1, // [28:28] 49 macrx_abort_request_info_valid : 1, // [29:29] 50 reserved : 2; // [31:30] 51 uint32_t coex_bt_tx_from_start_of_rx : 1, // [0:0] 52 coex_bt_tx_after_start_of_rx : 1, // [1:1] 53 coex_wan_tx_from_start_of_rx : 1, // [2:2] 54 coex_wan_tx_after_start_of_rx : 1, // [3:3] 55 coex_wlan_tx_from_start_of_rx : 1, // [4:4] 56 coex_wlan_tx_after_start_of_rx : 1, // [5:5] 57 mpdu_delimiter_errors_seen : 1, // [6:6] 58 ftm_tm : 2, // [8:7] 59 dialog_token : 8, // [16:9] 60 follow_up_dialog_token : 8, // [24:17] 61 bb_captured_channel : 1, // [25:25] 62 bb_captured_reason : 3, // [28:26] 63 bb_captured_timeout : 1, // [29:29] 64 reserved_3 : 2; // [31:30] 65 uint32_t before_mpdu_count_passing_fcs : 10, // [9:0] 66 before_mpdu_count_failing_fcs : 10, // [19:10] 67 after_mpdu_count_passing_fcs : 10, // [29:20] 68 reserved_4 : 2; // [31:30] 69 uint32_t after_mpdu_count_failing_fcs : 10, // [9:0] 70 reserved_5 : 22; // [31:10] 71 uint32_t phy_timestamp_tx_lower_32 : 32; // [31:0] 72 uint32_t phy_timestamp_tx_upper_32 : 32; // [31:0] 73 uint32_t bb_length : 16, // [15:0] 74 bb_data : 1, // [16:16] 75 reserved_8 : 3, // [19:17] 76 first_bt_broadcast_status_details : 12; // [31:20] 77 uint32_t rx_ppdu_duration : 24, // [23:0] 78 reserved_9 : 8; // [31:24] 79 uint32_t ast_index : 16, // [15:0] 80 ast_index_valid : 1, // [16:16] 81 reserved_10 : 3, // [19:17] 82 second_bt_broadcast_status_details : 12; // [31:20] 83 struct phyrx_abort_request_info phyrx_abort_request_info_details; 84 struct macrx_abort_request_info macrx_abort_request_info_details; 85 uint16_t pre_bt_broadcast_status_details : 12, // [27:16] 86 reserved_12a : 4; // [31:28] 87 uint32_t non_qos_sn_info_valid : 1, // [0:0] 88 reserved_13a : 5, // [5:1] 89 non_qos_sn_highest : 12, // [17:6] 90 non_qos_sn_highest_retry_setting : 1, // [18:18] 91 non_qos_sn_lowest : 12, // [30:19] 92 non_qos_sn_lowest_retry_setting : 1; // [31:31] 93 uint32_t qos_sn_1_info_valid : 1, // [0:0] 94 reserved_14a : 1, // [1:1] 95 qos_sn_1_tid : 4, // [5:2] 96 qos_sn_1_highest : 12, // [17:6] 97 qos_sn_1_highest_retry_setting : 1, // [18:18] 98 qos_sn_1_lowest : 12, // [30:19] 99 qos_sn_1_lowest_retry_setting : 1; // [31:31] 100 uint32_t qos_sn_2_info_valid : 1, // [0:0] 101 reserved_15a : 1, // [1:1] 102 qos_sn_2_tid : 4, // [5:2] 103 qos_sn_2_highest : 12, // [17:6] 104 qos_sn_2_highest_retry_setting : 1, // [18:18] 105 qos_sn_2_lowest : 12, // [30:19] 106 qos_sn_2_lowest_retry_setting : 1; // [31:31] 107 struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; 108 uint32_t corrupted_due_to_fifo_delay : 1, // [0:0] 109 qos_sn_1_more_frag_state : 1, // [1:1] 110 qos_sn_1_frag_num_state : 4, // [5:2] 111 qos_sn_2_more_frag_state : 1, // [6:6] 112 qos_sn_2_frag_num_state : 4, // [10:7] 113 reserved_26a : 21; // [31:11] 114 uint32_t rx_ppdu_end_marker : 32; // [31:0] 115 #else 116 uint32_t wb_timestamp_lower_32 : 32; // [31:0] 117 uint32_t wb_timestamp_upper_32 : 32; // [31:0] 118 uint32_t reserved : 2, // [31:30] 119 macrx_abort_request_info_valid : 1, // [29:29] 120 phyrx_abort_request_info_valid : 1, // [28:28] 121 previous_tlv_corrupted : 1, // [27:27] 122 otp_txbf_disable : 1, // [26:26] 123 unsupported_mu_nc : 1, // [25:25] 124 tx_ht_vht_ack : 1, // [24:24] 125 rx_antenna : 24; // [23:0] 126 uint32_t reserved_3 : 2, // [31:30] 127 bb_captured_timeout : 1, // [29:29] 128 bb_captured_reason : 3, // [28:26] 129 bb_captured_channel : 1, // [25:25] 130 follow_up_dialog_token : 8, // [24:17] 131 dialog_token : 8, // [16:9] 132 ftm_tm : 2, // [8:7] 133 mpdu_delimiter_errors_seen : 1, // [6:6] 134 coex_wlan_tx_after_start_of_rx : 1, // [5:5] 135 coex_wlan_tx_from_start_of_rx : 1, // [4:4] 136 coex_wan_tx_after_start_of_rx : 1, // [3:3] 137 coex_wan_tx_from_start_of_rx : 1, // [2:2] 138 coex_bt_tx_after_start_of_rx : 1, // [1:1] 139 coex_bt_tx_from_start_of_rx : 1; // [0:0] 140 uint32_t reserved_4 : 2, // [31:30] 141 after_mpdu_count_passing_fcs : 10, // [29:20] 142 before_mpdu_count_failing_fcs : 10, // [19:10] 143 before_mpdu_count_passing_fcs : 10; // [9:0] 144 uint32_t reserved_5 : 22, // [31:10] 145 after_mpdu_count_failing_fcs : 10; // [9:0] 146 uint32_t phy_timestamp_tx_lower_32 : 32; // [31:0] 147 uint32_t phy_timestamp_tx_upper_32 : 32; // [31:0] 148 uint32_t first_bt_broadcast_status_details : 12, // [31:20] 149 reserved_8 : 3, // [19:17] 150 bb_data : 1, // [16:16] 151 bb_length : 16; // [15:0] 152 uint32_t reserved_9 : 8, // [31:24] 153 rx_ppdu_duration : 24; // [23:0] 154 uint32_t second_bt_broadcast_status_details : 12, // [31:20] 155 reserved_10 : 3, // [19:17] 156 ast_index_valid : 1, // [16:16] 157 ast_index : 16; // [15:0] 158 struct phyrx_abort_request_info phyrx_abort_request_info_details; 159 uint32_t reserved_12a : 4, // [31:28] 160 pre_bt_broadcast_status_details : 12; // [27:16] 161 struct macrx_abort_request_info macrx_abort_request_info_details; 162 uint32_t non_qos_sn_lowest_retry_setting : 1, // [31:31] 163 non_qos_sn_lowest : 12, // [30:19] 164 non_qos_sn_highest_retry_setting : 1, // [18:18] 165 non_qos_sn_highest : 12, // [17:6] 166 reserved_13a : 5, // [5:1] 167 non_qos_sn_info_valid : 1; // [0:0] 168 uint32_t qos_sn_1_lowest_retry_setting : 1, // [31:31] 169 qos_sn_1_lowest : 12, // [30:19] 170 qos_sn_1_highest_retry_setting : 1, // [18:18] 171 qos_sn_1_highest : 12, // [17:6] 172 qos_sn_1_tid : 4, // [5:2] 173 reserved_14a : 1, // [1:1] 174 qos_sn_1_info_valid : 1; // [0:0] 175 uint32_t qos_sn_2_lowest_retry_setting : 1, // [31:31] 176 qos_sn_2_lowest : 12, // [30:19] 177 qos_sn_2_highest_retry_setting : 1, // [18:18] 178 qos_sn_2_highest : 12, // [17:6] 179 qos_sn_2_tid : 4, // [5:2] 180 reserved_15a : 1, // [1:1] 181 qos_sn_2_info_valid : 1; // [0:0] 182 struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; 183 uint32_t reserved_26a : 21, // [31:11] 184 qos_sn_2_frag_num_state : 4, // [10:7] 185 qos_sn_2_more_frag_state : 1, // [6:6] 186 qos_sn_1_frag_num_state : 4, // [5:2] 187 qos_sn_1_more_frag_state : 1, // [1:1] 188 corrupted_due_to_fifo_delay : 1; // [0:0] 189 uint32_t rx_ppdu_end_marker : 32; // [31:0] 190 #endif 191 }; 192 193 194 /* Description WB_TIMESTAMP_LOWER_32 195 196 WLAN/BT timestamp is a 1 usec resolution timestamp which 197 does not get updated based on receive beacon like TSF. 198 The same rules for capturing tsf_timestamp are used to 199 capture the wb_timestamp. This field represents the lower 200 32 bits of the 64-bit timestamp 201 */ 202 203 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 204 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB 0 205 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB 31 206 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff 207 208 209 /* Description WB_TIMESTAMP_UPPER_32 210 211 WLAN/BT timestamp is a 1 usec resolution timestamp which 212 does not get updated based on receive beacon like TSF. 213 The same rules for capturing tsf_timestamp are used to 214 capture the wb_timestamp. This field represents the upper 215 32 bits of the 64-bit timestamp 216 */ 217 218 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 219 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB 32 220 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB 63 221 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 222 223 224 /* Description RX_ANTENNA 225 226 Receive antenna value ??? 227 */ 228 229 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET 0x0000000000000008 230 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB 0 231 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB 23 232 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK 0x0000000000ffffff 233 234 235 /* Description TX_HT_VHT_ACK 236 237 Indicates that a HT or VHT Ack/BA frame was transmitted 238 in response to this receive packet. 239 */ 240 241 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET 0x0000000000000008 242 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB 24 243 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB 24 244 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK 0x0000000001000000 245 246 247 /* Description UNSUPPORTED_MU_NC 248 249 Set if MU Nc > 2 in received NDPA. 250 If this bit is set, even though AID and BSSID are matched, 251 MAC doesn't send tx_expect_ndp to PHY, because MU Nc > 2 252 is not supported in Helium. 253 */ 254 255 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET 0x0000000000000008 256 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB 25 257 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB 25 258 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK 0x0000000002000000 259 260 261 /* Description OTP_TXBF_DISABLE 262 263 Set if either OTP_SUBFEE_DISABLE or OTP_TXBF_DISABLE is 264 set and if RXPU receives directed NDPA frame. Then, RXPCU 265 should not send TX_EXPECT_NDP TLV to SW but set this bit 266 to inform SW. 267 */ 268 269 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET 0x0000000000000008 270 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB 26 271 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB 26 272 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK 0x0000000004000000 273 274 275 /* Description PREVIOUS_TLV_CORRUPTED 276 277 When set, the TLV preceding this RXPCU_END_INFO TLV within 278 the RX_PPDU_END TLV, is corrupted. Not the entire TLV was 279 received.... Likely due to an abort scenario... If abort 280 is to blame, see the abort data datastructure for details. 281 282 <legal all> 283 */ 284 285 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET 0x0000000000000008 286 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB 27 287 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB 27 288 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK 0x0000000008000000 289 290 291 /* Description PHYRX_ABORT_REQUEST_INFO_VALID 292 293 When set, the PHY sent an PHYRX_ABORT_REQUEST TLV to RXPCU. 294 The abort fields embedded in this TLV contain valid info. 295 296 <legal all> 297 */ 298 299 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 300 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 301 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB 28 302 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000010000000 303 304 305 /* Description MACRX_ABORT_REQUEST_INFO_VALID 306 307 When set, the MAC sent an MACRX_ABORT_REQUEST TLV to PHYRX. 308 The abort fields embedded in this TLV contain valid info. 309 310 <legal all> 311 */ 312 313 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 314 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 315 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB 29 316 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000020000000 317 318 319 /* Description RESERVED 320 321 <legal 0> 322 */ 323 324 #define RXPCU_PPDU_END_INFO_RESERVED_OFFSET 0x0000000000000008 325 #define RXPCU_PPDU_END_INFO_RESERVED_LSB 30 326 #define RXPCU_PPDU_END_INFO_RESERVED_MSB 31 327 #define RXPCU_PPDU_END_INFO_RESERVED_MASK 0x00000000c0000000 328 329 330 /* Description COEX_BT_TX_FROM_START_OF_RX 331 332 Set when BT TX was ongoing when WLAN RX started 333 */ 334 335 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 336 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB 32 337 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB 32 338 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK 0x0000000100000000 339 340 341 /* Description COEX_BT_TX_AFTER_START_OF_RX 342 343 Set when BT TX started while WLAN RX was already ongoing 344 345 */ 346 347 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 348 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB 33 349 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB 33 350 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x0000000200000000 351 352 353 /* Description COEX_WAN_TX_FROM_START_OF_RX 354 355 Set when WAN TX was ongoing when WLAN RX started 356 */ 357 358 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 359 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB 34 360 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB 34 361 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x0000000400000000 362 363 364 /* Description COEX_WAN_TX_AFTER_START_OF_RX 365 366 Set when WAN TX started while WLAN RX was already ongoing 367 368 */ 369 370 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 371 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB 35 372 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB 35 373 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x0000000800000000 374 375 376 /* Description COEX_WLAN_TX_FROM_START_OF_RX 377 378 Set when other WLAN TX was ongoing when WLAN RX started 379 */ 380 381 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 382 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB 36 383 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB 36 384 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x0000001000000000 385 386 387 /* Description COEX_WLAN_TX_AFTER_START_OF_RX 388 389 Set when other WLAN TX started while WLAN RX was already 390 ongoing 391 */ 392 393 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 394 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 37 395 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB 37 396 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x0000002000000000 397 398 399 /* Description MPDU_DELIMITER_ERRORS_SEEN 400 401 When set, MPDU delimiter errors have been detected during 402 this PPDU reception 403 */ 404 405 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000000000008 406 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB 38 407 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB 38 408 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x0000004000000000 409 410 411 /* Description FTM_TM 412 413 Indicate the timestamp is for the FTM or TM frame 414 415 0: non TM or FTM frame 416 1: FTM frame 417 2: TM frame 418 3: reserved 419 <legal all> 420 */ 421 422 #define RXPCU_PPDU_END_INFO_FTM_TM_OFFSET 0x0000000000000008 423 #define RXPCU_PPDU_END_INFO_FTM_TM_LSB 39 424 #define RXPCU_PPDU_END_INFO_FTM_TM_MSB 40 425 #define RXPCU_PPDU_END_INFO_FTM_TM_MASK 0x0000018000000000 426 427 428 /* Description DIALOG_TOKEN 429 430 The dialog token in the FTM or TM frame. Only valid when 431 the FTM is set. Clear to 254 for a non-FTM frame 432 <legal all> 433 */ 434 435 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET 0x0000000000000008 436 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB 41 437 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB 48 438 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK 0x0001fe0000000000 439 440 441 /* Description FOLLOW_UP_DIALOG_TOKEN 442 443 The follow up dialog token in the FTM or TM frame. Only 444 valid when the FTM is set. Clear to 0 for a non-FTM frame, 445 The follow up dialog token in the FTM frame. Only valid 446 when the FTM is set. Clear to 255 for a non-FTM frame<legal 447 all> 448 */ 449 450 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000000000008 451 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB 49 452 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB 56 453 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe000000000000 454 455 456 /* Description BB_CAPTURED_CHANNEL 457 458 Set by RXPCU when MACRX_FREEZE_CAPTURE_CHANNEL TLV is sent 459 to PHY, FW check it to correlate current PPDU TLVs with 460 uploaded channel information. 461 462 <legal all> 463 */ 464 465 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET 0x0000000000000008 466 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB 57 467 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB 57 468 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK 0x0200000000000000 469 470 471 /* Description BB_CAPTURED_REASON 472 473 Copy "capture_reason" of MACRX_FREEZE_CAPTURE_CHANNEL TLV 474 to here for FW usage. Valid when bb_captured_channel or 475 bb_captured_timeout is set. 476 477 This field indicates why the MAC asked to capture the channel 478 479 <enum 0 freeze_reason_TM> 480 <enum 1 freeze_reason_FTM> 481 <enum 2 freeze_reason_ACK_resp_to_TM_FTM> 482 <enum 3 freeze_reason_TA_RA_TYPE_FILTER> 483 <enum 4 freeze_reason_NDPA_NDP> 484 <enum 5 freeze_reason_ALL_PACKET> 485 486 <legal 0-5> 487 */ 488 489 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET 0x0000000000000008 490 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB 58 491 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB 60 492 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK 0x1c00000000000000 493 494 495 /* Description BB_CAPTURED_TIMEOUT 496 497 Set by RxPCU to indicate channel capture condition is meet, 498 but MACRX_FREEZE_CAPTURE_CHANNEL is not sent to PHY due 499 to AST long delay, which means the rx_frame_falling edge 500 to FREEZE TLV ready time exceed the threshold time defined 501 by RXPCU register FREEZE_TLV_DELAY_CNT_THRESH. 502 Bb_captured_reason is still valid in this case. 503 504 <legal all> 505 */ 506 507 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000000000008 508 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB 61 509 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB 61 510 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK 0x2000000000000000 511 512 513 /* Description RESERVED_3 514 515 <legal 0> 516 */ 517 518 #define RXPCU_PPDU_END_INFO_RESERVED_3_OFFSET 0x0000000000000008 519 #define RXPCU_PPDU_END_INFO_RESERVED_3_LSB 62 520 #define RXPCU_PPDU_END_INFO_RESERVED_3_MSB 63 521 #define RXPCU_PPDU_END_INFO_RESERVED_3_MASK 0xc000000000000000 522 523 524 /* Description BEFORE_MPDU_COUNT_PASSING_FCS 525 526 Number of MPDUs received in this PPDU that passed the FCS 527 check before the Coex TX started 528 529 The counter saturates at 0x3FF. 530 <legal all> 531 */ 532 533 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 534 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 535 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB 9 536 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x00000000000003ff 537 538 539 /* Description BEFORE_MPDU_COUNT_FAILING_FCS 540 541 Number of MPDUs received in this PPDU that failed the FCS 542 check before the Coex TX started 543 544 The counter saturates at 0x3FF. 545 <legal all> 546 */ 547 548 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 549 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 550 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB 19 551 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x00000000000ffc00 552 553 554 /* Description AFTER_MPDU_COUNT_PASSING_FCS 555 556 Number of MPDUs received in this PPDU that passed the FCS 557 check after the moment the Coex TX started 558 559 (Note: The partially received MPDU when the COEX tx start 560 event came in falls in the "after" category) 561 562 The counter saturates at 0x3FF. 563 <legal all> 564 */ 565 566 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 567 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 568 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB 29 569 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x000000003ff00000 570 571 572 /* Description RESERVED_4 573 574 <legal 0> 575 */ 576 577 #define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET 0x0000000000000010 578 #define RXPCU_PPDU_END_INFO_RESERVED_4_LSB 30 579 #define RXPCU_PPDU_END_INFO_RESERVED_4_MSB 31 580 #define RXPCU_PPDU_END_INFO_RESERVED_4_MASK 0x00000000c0000000 581 582 583 /* Description AFTER_MPDU_COUNT_FAILING_FCS 584 585 Number of MPDUs received in this PPDU that failed the FCS 586 check after the moment the Coex TX started 587 588 (Note: The partially received MPDU when the COEX tx start 589 event came in falls in the "after" category) 590 591 The counter saturates at 0x3FF. 592 <legal all> 593 */ 594 595 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 596 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB 32 597 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB 41 598 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff00000000 599 600 601 /* Description RESERVED_5 602 603 <legal 0> 604 */ 605 606 #define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET 0x0000000000000010 607 #define RXPCU_PPDU_END_INFO_RESERVED_5_LSB 42 608 #define RXPCU_PPDU_END_INFO_RESERVED_5_MSB 63 609 #define RXPCU_PPDU_END_INFO_RESERVED_5_MASK 0xfffffc0000000000 610 611 612 /* Description PHY_TIMESTAMP_TX_LOWER_32 613 614 The PHY timestamp in the AMPI of the most recent rising 615 edge (TODO: of what ???) after the TX_PHY_DESC. This field 616 indicates the lower 32 bits of the timestamp 617 */ 618 619 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x0000000000000018 620 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 621 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB 31 622 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK 0x00000000ffffffff 623 624 625 /* Description PHY_TIMESTAMP_TX_UPPER_32 626 627 The PHY timestamp in the AMPI of the most recent rising 628 edge (TODO: of what ???) after the TX_PHY_DESC. This field 629 indicates the upper 32 bits of the timestamp 630 */ 631 632 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000000000000018 633 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB 32 634 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB 63 635 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff00000000 636 637 638 /* Description BB_LENGTH 639 640 Indicates the number of bytes of baseband information for 641 PPDUs where the BB descriptor preamble type is 0x80 to 642 0xFF which indicates that this is not a normal PPDU but 643 rather contains baseband debug information. 644 TODO: Is this still needed ??? 645 */ 646 647 #define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET 0x0000000000000020 648 #define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB 0 649 #define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB 15 650 #define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK 0x000000000000ffff 651 652 653 /* Description BB_DATA 654 655 Indicates that BB data associated with this PPDU will exist 656 in the receive buffer. The exact contents of this BB data 657 can be found by decoding the BB TLV in the buffer associated 658 with the BB data. See vector_fragment in the Helium_mac_phy_interface.docx 659 660 */ 661 662 #define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET 0x0000000000000020 663 #define RXPCU_PPDU_END_INFO_BB_DATA_LSB 16 664 #define RXPCU_PPDU_END_INFO_BB_DATA_MSB 16 665 #define RXPCU_PPDU_END_INFO_BB_DATA_MASK 0x0000000000010000 666 667 668 /* Description RESERVED_8 669 670 Reserved: HW should fill with 0, FW should ignore. 671 */ 672 673 #define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET 0x0000000000000020 674 #define RXPCU_PPDU_END_INFO_RESERVED_8_LSB 17 675 #define RXPCU_PPDU_END_INFO_RESERVED_8_MSB 19 676 #define RXPCU_PPDU_END_INFO_RESERVED_8_MASK 0x00000000000e0000 677 678 679 /* Description FIRST_BT_BROADCAST_STATUS_DETAILS 680 681 Same contents as field "bt_broadcast_status_details" for 682 the first received COEX_STATUS_BROADCAST tlv during this 683 PPDU reception. 684 685 If no COEX_STATUS_BROADCAST tlv is received during this 686 PPDU reception, this field will be set to 0 687 688 689 For detailed info see doc: TBD 690 <legal all> 691 */ 692 693 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000020 694 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 695 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 31 696 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 697 698 699 /* Description RX_PPDU_DURATION 700 701 The length of this PPDU reception in us 702 */ 703 704 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 0x0000000000000020 705 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 32 706 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB 55 707 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 0x00ffffff00000000 708 709 710 /* Description RESERVED_9 711 712 <legal 0> 713 */ 714 715 #define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET 0x0000000000000020 716 #define RXPCU_PPDU_END_INFO_RESERVED_9_LSB 56 717 #define RXPCU_PPDU_END_INFO_RESERVED_9_MSB 63 718 #define RXPCU_PPDU_END_INFO_RESERVED_9_MASK 0xff00000000000000 719 720 721 /* Description AST_INDEX 722 723 The AST index of the receive Ack/BA. This information is 724 provided from the TXPCU to the RXPCU for receive Ack/BA 725 for implicit beamforming. 726 <legal all> 727 */ 728 729 #define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET 0x0000000000000028 730 #define RXPCU_PPDU_END_INFO_AST_INDEX_LSB 0 731 #define RXPCU_PPDU_END_INFO_AST_INDEX_MSB 15 732 #define RXPCU_PPDU_END_INFO_AST_INDEX_MASK 0x000000000000ffff 733 734 735 /* Description AST_INDEX_VALID 736 737 Indicates that ast_index is valid. Should only be set for 738 receive Ack/BA where single stream implicit sounding is 739 captured. 740 */ 741 742 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET 0x0000000000000028 743 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB 16 744 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB 16 745 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK 0x0000000000010000 746 747 748 /* Description RESERVED_10 749 750 <legal 0> 751 */ 752 753 #define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET 0x0000000000000028 754 #define RXPCU_PPDU_END_INFO_RESERVED_10_LSB 17 755 #define RXPCU_PPDU_END_INFO_RESERVED_10_MSB 19 756 #define RXPCU_PPDU_END_INFO_RESERVED_10_MASK 0x00000000000e0000 757 758 759 /* Description SECOND_BT_BROADCAST_STATUS_DETAILS 760 761 Same contents as field "bt_broadcast_status_details" for 762 the second received COEX_STATUS_BROADCAST tlv during this 763 PPDU reception. 764 765 If no second COEX_STATUS_BROADCAST tlv is received during 766 this PPDU reception, this field will be set to 0 767 768 769 For detailed info see doc: TBD 770 <legal all> 771 */ 772 773 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000028 774 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 775 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 31 776 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 777 778 779 /* Description PHYRX_ABORT_REQUEST_INFO_DETAILS 780 781 Field only valid when Phyrx_abort_request_info_valid is 782 set 783 The reason why PHY generated an abort request 784 */ 785 786 787 /* Description PHYRX_ABORT_REASON 788 789 <enum 0 phyrx_err_phy_off> Reception aborted due to receiving 790 a PHY_OFF TLV 791 <enum 1 phyrx_err_synth_off> 792 <enum 2 phyrx_err_ofdma_timing> 793 <enum 3 phyrx_err_ofdma_signal_parity> 794 <enum 4 phyrx_err_ofdma_rate_illegal> 795 <enum 5 phyrx_err_ofdma_length_illegal> 796 <enum 6 phyrx_err_ofdma_restart> 797 <enum 7 phyrx_err_ofdma_service> 798 <enum 8 phyrx_err_ppdu_ofdma_power_drop> 799 800 <enum 9 phyrx_err_cck_blokker> 801 <enum 10 phyrx_err_cck_timing> 802 <enum 11 phyrx_err_cck_header_crc> 803 <enum 12 phyrx_err_cck_rate_illegal> 804 <enum 13 phyrx_err_cck_length_illegal> 805 <enum 14 phyrx_err_cck_restart> 806 <enum 15 phyrx_err_cck_service> 807 <enum 16 phyrx_err_cck_power_drop> 808 809 <enum 17 phyrx_err_ht_crc_err> 810 <enum 18 phyrx_err_ht_length_illegal> 811 <enum 19 phyrx_err_ht_rate_illegal> 812 <enum 20 phyrx_err_ht_zlf> 813 <enum 21 phyrx_err_false_radar_ext> 814 <enum 22 phyrx_err_green_field> 815 <enum 60 phyrx_err_ht_nsym_lt_zero> 816 817 <enum 23 phyrx_err_bw_gt_dyn_bw> 818 <enum 24 phyrx_err_leg_ht_mismatch> 819 <enum 25 phyrx_err_vht_crc_error> 820 <enum 26 phyrx_err_vht_siga_unsupported> 821 <enum 27 phyrx_err_vht_lsig_len_invalid> 822 <enum 28 phyrx_err_vht_ndp_or_zlf> 823 <enum 29 phyrx_err_vht_nsym_lt_zero> 824 <enum 30 phyrx_err_vht_rx_extra_symbol_mismatch> 825 <enum 31 phyrx_err_vht_rx_skip_group_id0> 826 <enum 32 phyrx_err_vht_rx_skip_group_id1to62> 827 <enum 33 phyrx_err_vht_rx_skip_group_id63> 828 <enum 34 phyrx_err_ofdm_ldpc_decoder_disabled> 829 <enum 35 phyrx_err_defer_nap> 830 831 <enum 61 phyrx_err_vht_lsig_rate_mismatch> 832 <enum 62 phyrx_err_vht_paid_gid_mismatch> 833 <enum 63 phyrx_err_vht_unsupported_bw> 834 <enum 64 phyrx_err_vht_gi_disam_mismatch> 835 836 <enum 36 phyrx_err_fdomain_timeout> 837 <enum 37 phyrx_err_lsig_rel_check> 838 <enum 38 phyrx_err_bt_collision> 839 <enum 39 phyrx_err_unsupported_mu_feedback> 840 <enum 40 phyrx_err_ppdu_tx_interrupt_rx> 841 <enum 41 phyrx_err_unsupported_cbf> 842 843 <enum 42 phyrx_err_other> Should not really be used. If 844 needed, ask for documentation update 845 846 <enum 43 phyrx_err_he_siga_unsupported > <enum 44 phyrx_err_he_crc_error 847 > <enum 45 phyrx_err_he_sigb_unsupported > <enum 46 phyrx_err_he_mu_mode_unsupported 848 > <enum 47 phyrx_err_he_ndp_or_zlf > <enum 48 phyrx_err_he_nsym_lt_zero 849 > <enum 49 phyrx_err_he_ru_params_unsupported > <enum 50 850 phyrx_err_he_num_users_unsupported ><enum 51 phyrx_err_he_sounding_params_unsupported 851 > 852 <enum 54 phyrx_err_he_sigb_crc_error> 853 <enum 55 phyrx_err_he_ext_su_unsupported> 854 <enum 56 phyrx_err_he_trig_unsupported> 855 <enum 57 phyrx_err_he_lsig_len_invalid> 856 <enum 58 phyrx_err_he_lsig_rate_mismatch> 857 <enum 59 phyrx_err_ofdma_signal_reliability> 858 859 <enum 77 phyrx_err_wur_detection> 860 861 <enum 72 phyrx_err_u_sig_crc_error> 862 <enum 73 phyrx_err_u_sig_unsupported_mode> 863 <enum 74 phyrx_err_u_sig_rsvd_err> 864 <enum 75 phyrx_err_u_sig_mcs_error> 865 <enum 76 phyrx_err_u_sig_bw_error> 866 <enum 79 phyrx_err_u_sig_320_channel_mismatch> 867 <enum 71 phyrx_err_eht_sig_crc_error> 868 <enum 78 phyrx_err_eht_sig_unsupported_mode> 869 870 <enum 80 phyrx_err_ehtplus_er_detection> 871 872 <enum 52 phyrx_err_MU_UL_no_power_detected> 873 <enum 53 phyrx_err_MU_UL_not_for_me> 874 875 <enum 65 phyrx_err_rx_wdg_timeout> 876 <enum 66 phyrx_err_sizing_evt_unexpected> 877 <enum 67 phyrx_err_spectralscan> 878 <enum 68 phyrx_err_radar_misdetected_as_ofdm> 879 <enum 69 phyrx_err_rx_stuck> 880 <enum 70 phyrx_err_invalid_11b_state> 881 882 <legal 0 - 80> 883 */ 884 885 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000028 886 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 32 887 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 39 888 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff00000000 889 890 891 /* Description PHY_ENTERS_NAP_STATE 892 893 When set, PHY enters PHY NAP state after sending this abort 894 895 896 Note that nap and defer state are mutually exclusive. 897 898 Field put pro-actively in place....usage still to be agreed 899 upon. 900 <legal all> 901 */ 902 903 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000000000000028 904 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 40 905 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 40 906 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x0000010000000000 907 908 909 /* Description PHY_ENTERS_DEFER_STATE 910 911 When set, PHY enters PHY defer state after sending this 912 abort 913 914 Note that nap and defer state are mutually exclusive. 915 916 Field put pro-actively in place....usage still to be agreed 917 upon. 918 <legal all> 919 */ 920 921 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000000000000028 922 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 41 923 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 41 924 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x0000020000000000 925 926 927 /* Description RESERVED_0 928 929 <legal 0> 930 */ 931 932 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000028 933 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 42 934 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 47 935 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000fc0000000000 936 937 938 /* Description RECEIVE_DURATION 939 940 The remaining receive duration of this PPDU in the medium 941 (in us). When PHY does not know this duration when this 942 TLV is generated, the field will be set to 0. 943 The timing reference point is the reception by the MAC of 944 this TLV. The value shall be accurate to within 2us. 945 946 In case Phy_enters_nap_state and/or Phy_enters_defer_state 947 is set, there is a possibility that MAC PMM can also decide 948 to go into a low(er) power state. 949 <legal all> 950 */ 951 952 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000000000000028 953 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 48 954 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB 63 955 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff000000000000 956 957 958 /* Description MACRX_ABORT_REQUEST_INFO_DETAILS 959 960 Field only valid when macrx_abort_request_info_valid is 961 set 962 The reason why MACRX generated an abort request 963 */ 964 965 966 /* Description MACRX_ABORT_REASON 967 968 <enum 0 macrx_abort_sw_initiated> 969 <enum 1 macrx_abort_obss_reception> Upon receiving this 970 abort reason, PHY should stop reception of the current frame 971 and go back into a search mode 972 <enum 2 macrx_abort_other> 973 <enum 3 macrx_abort_sw_initiated_channel_switch> MAC FW 974 issued an abort for channel switch reasons 975 <enum 4 macrx_abort_sw_initiated_power_save> MAC FW issued 976 an abort power save reasons 977 <enum 5 macrx_abort_too_much_bad_data> RXPCU is terminating 978 the current ongoing reception, as the data that MAC is 979 receiving seems to be all garbage... The PER is too high, 980 or in case of MU UL, Likely the trigger frame never got 981 properly received by any of the targeted MU UL devices. 982 After the abort, PHYRX can resume a normal search mode. 983 <enum 6 macrx_abort_ul_mu_early_abort> RXPCU is terminating 984 the current ongoing UL MU reception, because at the end 985 of the "early_termination_window," the required number 986 of users with at least one valid MPDU delimiter was not 987 reached. Likely the trigger frame never got properly received 988 by the required number of targeted devices. After the abort, 989 PHYRX can resume a normal search mode. 990 991 <legal 0-6> 992 */ 993 994 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000030 995 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 996 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7 997 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000ff 998 999 1000 /* Description RESERVED_0 1001 1002 <legal 0> 1003 */ 1004 1005 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000030 1006 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 1007 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 1008 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x000000000000ff00 1009 1010 1011 /* Description PRE_BT_BROADCAST_STATUS_DETAILS 1012 1013 Same contents as field "bt_broadcast_status_details" of 1014 the last received COEX_STATUS_BROADCAST tlv before this 1015 PPDU reception. 1016 After power up, this field is all initialized to 0 1017 1018 For detailed info see doc: TBD 1019 <legal all> 1020 */ 1021 1022 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000030 1023 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 16 1024 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 27 1025 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x000000000fff0000 1026 1027 1028 /* Description RESERVED_12A 1029 1030 Bits: [27:16] 1031 Same contents as field "bt_broadcast_status_details" of 1032 the last received COEX_STATUS_BROADCAST tlv before this 1033 PPDU reception. 1034 After power up, this field is all initialized to 0 1035 1036 Bits: [31:28]: always 0 1037 1038 1039 For detailed info see doc: TBD 1040 <legal all> 1041 */ 1042 1043 #define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET 0x0000000000000030 1044 #define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB 28 1045 #define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB 31 1046 #define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK 0x00000000f0000000 1047 1048 1049 /* Description NON_QOS_SN_INFO_VALID 1050 1051 When set, the non_QoS_SN_... fields contain valid info. 1052 1053 This field will ONLY be set upon the very first reception 1054 of a non QoS frame. 1055 1056 <legal all> 1057 */ 1058 1059 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET 0x0000000000000030 1060 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB 32 1061 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB 32 1062 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK 0x0000000100000000 1063 1064 1065 /* Description RESERVED_13A 1066 1067 <legal 0> 1068 */ 1069 1070 #define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET 0x0000000000000030 1071 #define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB 33 1072 #define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB 37 1073 #define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK 0x0000003e00000000 1074 1075 1076 /* Description NON_QOS_SN_HIGHEST 1077 1078 Field only valid when non_QoS_SN_info_valid is set 1079 1080 Lowest and highest are defined based on a 2K window. 1081 When only 1 non-QoS frame is received, the 'highest' and 1082 'lowest' fields will have the same values. 1083 1084 The highest MPDU sequence number for a non-QoS frame received 1085 in this PPDU 1086 <legal all> 1087 */ 1088 1089 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET 0x0000000000000030 1090 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB 38 1091 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB 49 1092 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK 0x0003ffc000000000 1093 1094 1095 /* Description NON_QOS_SN_HIGHEST_RETRY_SETTING 1096 1097 Field only valid when non_QoS_SN_info_valid is set 1098 1099 The 'retry' bit setting of the highest MPDU sequence number 1100 non-QOS frame received in this PPDU 1101 <legal all> 1102 */ 1103 1104 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000030 1105 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB 50 1106 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB 50 1107 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 1108 1109 1110 /* Description NON_QOS_SN_LOWEST 1111 1112 Field only valid when non_QoS_SN_info_valid is set 1113 1114 Lowest and highest are defined based on a 2K window. 1115 When only 1 non-QoS frame is received, the 'highest' and 1116 'lowest' fields will have the same values. 1117 1118 The lowest MPDU sequence number for a non-QoS frame received 1119 in this PPDU 1120 <legal all> 1121 */ 1122 1123 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET 0x0000000000000030 1124 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB 51 1125 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB 62 1126 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK 0x7ff8000000000000 1127 1128 1129 /* Description NON_QOS_SN_LOWEST_RETRY_SETTING 1130 1131 Field only valid when non_QoS_SN_info_valid is set 1132 1133 The 'retry' bit setting of the lowest MPDU sequence number 1134 non-QoS frame received in this PPDU 1135 <legal all> 1136 */ 1137 1138 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000030 1139 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB 63 1140 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB 63 1141 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 1142 1143 1144 /* Description QOS_SN_1_INFO_VALID 1145 1146 When set, the QoS_SN_1_... fields contain valid info. 1147 1148 This field will ONLY be set upon the very first reception 1149 of a QoS frame. 1150 1151 <legal all> 1152 */ 1153 1154 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET 0x0000000000000038 1155 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB 0 1156 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB 0 1157 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK 0x0000000000000001 1158 1159 1160 /* Description RESERVED_14A 1161 1162 <legal 0> 1163 */ 1164 1165 #define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET 0x0000000000000038 1166 #define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB 1 1167 #define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB 1 1168 #define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK 0x0000000000000002 1169 1170 1171 /* Description QOS_SN_1_TID 1172 1173 Field only valid when QoS_SN_1_info_valid is set. 1174 1175 The TID of the frames related to the QoS_SN_1_... fields 1176 1177 <legal all> 1178 */ 1179 1180 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET 0x0000000000000038 1181 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB 2 1182 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB 5 1183 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK 0x000000000000003c 1184 1185 1186 /* Description QOS_SN_1_HIGHEST 1187 1188 Field only valid when QoS_SN_1_info_valid is set. 1189 1190 Lowest and highest are defined based on a 2K window. 1191 When only 1 QoS frame of the relevant TID is received, the 1192 'highest' and 'lowest' fields will have the same values. 1193 1194 1195 The highest MPDU sequence number for a QoS frame with TID 1196 QoS_SN_1_TID received in this PPDU 1197 <legal all> 1198 */ 1199 1200 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET 0x0000000000000038 1201 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB 6 1202 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB 17 1203 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK 0x000000000003ffc0 1204 1205 1206 /* Description QOS_SN_1_HIGHEST_RETRY_SETTING 1207 1208 Field only valid when QoS_SN_1_info_valid is set. 1209 1210 The 'retry' bit setting of the highest MPDU sequence number 1211 QoS frame with TID QoS_SN_1_TID received in this PPDU 1212 <legal all> 1213 */ 1214 1215 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 1216 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB 18 1217 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB 18 1218 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK 0x0000000000040000 1219 1220 1221 /* Description QOS_SN_1_LOWEST 1222 1223 Field only valid when QoS_SN_1_info_valid is set. 1224 1225 Lowest and highest are defined based on a 2K window. 1226 When only 1 QoS frame of the relevant TID is received, the 1227 'highest' and 'lowest' fields will have the same values. 1228 1229 1230 The lowest MPDU sequence number for a QoS frame with TID 1231 QoS_SN_1_TID received in this PPDU 1232 <legal all> 1233 */ 1234 1235 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET 0x0000000000000038 1236 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB 19 1237 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB 30 1238 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK 0x000000007ff80000 1239 1240 1241 /* Description QOS_SN_1_LOWEST_RETRY_SETTING 1242 1243 Field only valid when QoS_SN_1_info_valid is set. 1244 1245 The 'retry' bit setting of the lowest MPDU sequence number 1246 QoS frame with TID QoS_SN_1_TID received in this PPDU 1247 <legal all> 1248 */ 1249 1250 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 1251 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB 31 1252 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB 31 1253 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK 0x0000000080000000 1254 1255 1256 /* Description QOS_SN_2_INFO_VALID 1257 1258 When set, the QoS_SN_2_... fields contain valid info. 1259 1260 This field can ONLY be set in case of a multi-TID PPDU reception. 1261 This field is set upon the very first reception of a QoS 1262 frame belonging to the second TID in the PPDU. 1263 1264 <legal all> 1265 */ 1266 1267 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET 0x0000000000000038 1268 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB 32 1269 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB 32 1270 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK 0x0000000100000000 1271 1272 1273 /* Description RESERVED_15A 1274 1275 <legal 0> 1276 */ 1277 1278 #define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET 0x0000000000000038 1279 #define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB 33 1280 #define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB 33 1281 #define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK 0x0000000200000000 1282 1283 1284 /* Description QOS_SN_2_TID 1285 1286 Field only valid when QoS_SN_2_info_valid is set. 1287 1288 The TID of the frames related to the QoS_SN_2_... fields 1289 1290 <legal all> 1291 */ 1292 1293 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET 0x0000000000000038 1294 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB 34 1295 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB 37 1296 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK 0x0000003c00000000 1297 1298 1299 /* Description QOS_SN_2_HIGHEST 1300 1301 Field only valid when QoS_SN_2_info_valid is set. 1302 1303 Lowest and highest are defined based on a 2K window. 1304 When only 1 QoS frame of the relevant TID is received, the 1305 highest and lowest fields will have the same values. 1306 1307 The highest MPDU sequence number for a QoS frame with TID 1308 QoS_SN_2_TID received in this PPDU 1309 <legal all> 1310 */ 1311 1312 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET 0x0000000000000038 1313 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB 38 1314 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB 49 1315 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK 0x0003ffc000000000 1316 1317 1318 /* Description QOS_SN_2_HIGHEST_RETRY_SETTING 1319 1320 Field only valid when QoS_SN_2_info_valid is set. 1321 1322 The 'retry' bit setting of the highest MPDU sequence number 1323 QoS frame with TID QoS_SN_2_TID received in this PPDU 1324 <legal all> 1325 */ 1326 1327 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 1328 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB 50 1329 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB 50 1330 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 1331 1332 1333 /* Description QOS_SN_2_LOWEST 1334 1335 Field only valid when QoS_SN_2_info_valid is set. 1336 1337 Lowest and highest are defined based on a 2K window. 1338 When only 1 QoS frame of the relevant TID is received, the 1339 highest and lowest fields will have the same values. 1340 1341 The lowest MPDU sequence number for a QoS frame with TID 1342 QoS_SN_2_TID received in this PPDU 1343 <legal all> 1344 */ 1345 1346 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET 0x0000000000000038 1347 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB 51 1348 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB 62 1349 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK 0x7ff8000000000000 1350 1351 1352 /* Description QOS_SN_2_LOWEST_RETRY_SETTING 1353 1354 Field only valid when QoS_SN_2_info_valid is set. 1355 1356 The 'retry' bit setting of the lowest MPDU sequence number 1357 QoS frame with TID QoS_SN_2_TID received in this PPDU 1358 <legal all> 1359 */ 1360 1361 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 1362 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB 63 1363 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB 63 1364 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 1365 1366 1367 /* Description RXPCU_PPDU_END_LAYOUT_DETAILS 1368 1369 Structure containing the relative offsets of preamble TLVs 1370 within 'RX_PPDU_END' documenting the layout within 'RX_PPDU_END' 1371 1372 */ 1373 1374 1375 /* Description RSSI_LEGACY_OFFSET 1376 1377 Offset in units of 4 bytes of 'PHYRX_RSSI_LEGACY' within 1378 'RX_PPDU_END'<legal 1, 2> 1379 */ 1380 1381 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x0000000000000040 1382 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB 0 1383 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB 1 1384 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK 0x0000000000000003 1385 1386 1387 /* Description L_SIG_A_OFFSET 1388 1389 Offset in units of 4 bytes of 'PHYRX_L_SIG_A' within 'RX_PPDU_END' 1390 Set to zero if the TLV is not included<legal 0, 44, 46> 1391 */ 1392 1393 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 1394 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB 2 1395 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB 7 1396 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK 0x00000000000000fc 1397 1398 1399 /* Description L_SIG_B_OFFSET 1400 1401 Offset in units of 4 bytes of 'PHYRX_L_SIG_A' within 'RX_PPDU_END' 1402 Set to zero if the TLV is not included<legal 0, 44, 46> 1403 */ 1404 1405 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET 0x0000000000000040 1406 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB 8 1407 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB 13 1408 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK 0x0000000000003f00 1409 1410 1411 /* Description HT_SIG_OFFSET 1412 1413 Offset of 'PHYRX_HT_SIG' within 'RX_PPDU_END' Set to zero 1414 if the TLV is not included<legal 0, 46, 50> 1415 */ 1416 1417 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET 0x0000000000000040 1418 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB 14 1419 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB 19 1420 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK 0x00000000000fc000 1421 1422 1423 /* Description VHT_SIG_A_OFFSET 1424 1425 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_A' within 'RX_PPDU_END' 1426 Set to zero if the TLV is not included<legal 0, 46, 50> 1427 */ 1428 1429 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET 0x0000000000000040 1430 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB 20 1431 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB 25 1432 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK 0x0000000003f00000 1433 1434 1435 /* Description REPEAT_L_SIG_A_OFFSET 1436 1437 Offset in units of 4 bytes of the repeat 'PHYRX_L_SIG_A' (in 1438 HE and EHT cases) within 'RX_PPDU_END' 1439 1440 Set to zero if the TLV is not included 1441 <legal 0, 46, 50> 1442 */ 1443 1444 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 1445 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26 1446 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31 1447 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0x00000000fc000000 1448 1449 1450 /* Description HE_SIG_A_SU_OFFSET 1451 1452 Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_SU' within 1453 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1454 0, 48, 54> 1455 */ 1456 1457 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x0000000000000040 1458 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB 32 1459 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB 37 1460 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK 0x0000003f00000000 1461 1462 1463 /* Description HE_SIG_A_MU_DL_OFFSET 1464 1465 Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_MU_DL' within 1466 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1467 0, 48, 54> 1468 */ 1469 1470 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x0000000000000040 1471 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 38 1472 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 43 1473 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc000000000 1474 1475 1476 /* Description HE_SIG_A_MU_UL_OFFSET 1477 1478 Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_MU_UL' within 1479 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1480 0, 48, 54> 1481 */ 1482 1483 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x0000000000000040 1484 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 44 1485 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 49 1486 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f00000000000 1487 1488 1489 /* Description GENERIC_U_SIG_OFFSET 1490 1491 Offset in units of 4 bytes of 'PHYRX_GENERIC_U_SIG' within 1492 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1493 0, 48, 54> 1494 */ 1495 1496 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x0000000000000040 1497 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB 50 1498 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB 55 1499 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc000000000000 1500 1501 1502 /* Description RSSI_HT_OFFSET 1503 1504 Offset in units of 4 bytes of 'PHYRX_RSSI_HT' within 'RX_PPDU_END' 1505 Set to zero if the TLV is not included<legal 0, 49-127> 1506 */ 1507 1508 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET 0x0000000000000040 1509 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB 56 1510 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB 62 1511 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK 0x7f00000000000000 1512 1513 1514 /* Description RESERVED_1A 1515 1516 <legal 0> 1517 */ 1518 1519 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET 0x0000000000000040 1520 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB 63 1521 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB 63 1522 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK 0x8000000000000000 1523 1524 1525 /* Description VHT_SIG_B_SU20_OFFSET 1526 1527 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU20' within 1528 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1529 0, 67, 74> 1530 */ 1531 1532 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x0000000000000048 1533 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0 1534 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6 1535 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x000000000000007f 1536 1537 1538 /* Description VHT_SIG_B_SU40_OFFSET 1539 1540 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU40' within 1541 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1542 0, 67, 74> 1543 */ 1544 1545 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x0000000000000048 1546 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7 1547 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13 1548 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x0000000000003f80 1549 1550 1551 /* Description VHT_SIG_B_SU80_OFFSET 1552 1553 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU80' within 1554 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1555 0, 67, 74> 1556 */ 1557 1558 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x0000000000000048 1559 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14 1560 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20 1561 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x00000000001fc000 1562 1563 1564 /* Description VHT_SIG_B_SU160_OFFSET 1565 1566 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU160' within 1567 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1568 0, 67, 74> 1569 */ 1570 1571 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x0000000000000048 1572 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21 1573 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27 1574 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x000000000fe00000 1575 1576 1577 /* Description RESERVED_2A 1578 1579 <legal 0> 1580 */ 1581 1582 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET 0x0000000000000048 1583 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB 28 1584 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB 31 1585 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK 0x00000000f0000000 1586 1587 1588 /* Description VHT_SIG_B_MU20_OFFSET 1589 1590 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU20' within 1591 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1592 0, 67, 74> 1593 */ 1594 1595 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000000000048 1596 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 32 1597 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 38 1598 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f00000000 1599 1600 1601 /* Description VHT_SIG_B_MU40_OFFSET 1602 1603 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU40' within 1604 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1605 0, 67, 74> 1606 */ 1607 1608 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000000000048 1609 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 39 1610 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 45 1611 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f8000000000 1612 1613 1614 /* Description VHT_SIG_B_MU80_OFFSET 1615 1616 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU80' within 1617 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1618 0, 67, 74> 1619 */ 1620 1621 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000000000048 1622 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 46 1623 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 52 1624 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc00000000000 1625 1626 1627 /* Description VHT_SIG_B_MU160_OFFSET 1628 1629 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU160' within 1630 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1631 0, 67, 74> 1632 */ 1633 1634 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000000000048 1635 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 53 1636 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 59 1637 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe0000000000000 1638 1639 1640 /* Description RESERVED_3A 1641 1642 <legal 0> 1643 */ 1644 1645 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET 0x0000000000000048 1646 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB 60 1647 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB 63 1648 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK 0xf000000000000000 1649 1650 1651 /* Description HE_SIG_B1_MU_OFFSET 1652 1653 Offset in units of 4 bytes of 'PHYRX_HE_SIG_B1_MU' within 1654 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1655 0, 51, 58> 1656 */ 1657 1658 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x0000000000000050 1659 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB 0 1660 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB 6 1661 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK 0x000000000000007f 1662 1663 1664 /* Description HE_SIG_B2_MU_OFFSET 1665 1666 Offset in units of 4 bytes of 'PHYRX_HE_SIG_B2_MU' within 1667 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1668 0, 51, 58> 1669 */ 1670 1671 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x0000000000000050 1672 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB 7 1673 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB 13 1674 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK 0x0000000000003f80 1675 1676 1677 /* Description HE_SIG_B2_OFDMA_OFFSET 1678 1679 Offset in units of 4 bytes of 'PHYRX_HE_SIG_B2_OFDMA' within 1680 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1681 0, 53, 62> 1682 */ 1683 1684 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x0000000000000050 1685 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14 1686 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20 1687 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x00000000001fc000 1688 1689 1690 /* Description FIRST_GENERIC_EHT_SIG_OFFSET 1691 1692 Offset in units of 4 bytes of the first 'PHYRX_GENERIC_EHT_SIG' 1693 within 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1694 0, 51, 58> 1695 */ 1696 1697 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x0000000000000050 1698 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 1699 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 1700 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x000000000fe00000 1701 1702 1703 /* Description MULTIPLE_GENERIC_EHT_SIG_INCLUDED 1704 1705 Set to one if more than one 'PHYRX_GENERIC_EHT_SIG' TLVs 1706 are included in 'RX_PPDU_END,' set to zero otherwise 1707 <legal all> 1708 */ 1709 1710 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x0000000000000050 1711 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 1712 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 1713 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x0000000010000000 1714 1715 1716 /* Description RESERVED_4A 1717 1718 <legal 0> 1719 */ 1720 1721 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET 0x0000000000000050 1722 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB 29 1723 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB 31 1724 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK 0x00000000e0000000 1725 1726 1727 /* Description COMMON_USER_INFO_OFFSET 1728 1729 Offset in units of 4 bytes of 'PHYRX_COMMON_USER_INFO' within 1730 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1731 0, 46, 50, 67, 70-127> 1732 */ 1733 1734 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x0000000000000050 1735 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 32 1736 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 38 1737 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f00000000 1738 1739 1740 /* Description FIRST_DEBUG_INFO_OFFSET 1741 1742 Offset in units of 4 bytes of the first 'PHYRX_DEBUG_INFO' 1743 within 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1744 all> 1745 */ 1746 1747 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x0000000000000050 1748 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 39 1749 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 46 1750 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f8000000000 1751 1752 1753 /* Description MULTIPLE_DEBUG_INFO_INCLUDED 1754 1755 Set to one if more than one 'PHYRX_DEBUG_INFO' TLVs are 1756 included in 'RX_PPDU_END,' set to zero otherwise<legal all> 1757 1758 */ 1759 1760 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x0000000000000050 1761 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 47 1762 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 47 1763 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x0000800000000000 1764 1765 1766 /* Description FIRST_OTHER_RECEIVE_INFO_OFFSET 1767 1768 Offset in units of 4 bytes of the first 'PHYRX_OTHER_RECEIVE_INFO' 1769 within 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1770 all> 1771 */ 1772 1773 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x0000000000000050 1774 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 48 1775 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 55 1776 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff000000000000 1777 1778 1779 /* Description MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED 1780 1781 Set to one if more than one 'PHYRX_OTHER_RECEIVE_INFO' TLVs 1782 are included in 'RX_PPDU_END,' set to zero otherwise<legal 1783 all> 1784 */ 1785 1786 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x0000000000000050 1787 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 56 1788 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 56 1789 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x0100000000000000 1790 1791 1792 /* Description RESERVED_5A 1793 1794 <legal 0> 1795 */ 1796 1797 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET 0x0000000000000050 1798 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB 57 1799 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB 63 1800 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK 0xfe00000000000000 1801 1802 1803 /* Description DATA_DONE_OFFSET 1804 1805 Offset in units of 4 bytes of 'PHYRX_DATA_DONE' within 'RX_PPDU_END' 1806 Set to zero if the TLV is not included<legal all> 1807 */ 1808 1809 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET 0x0000000000000058 1810 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB 0 1811 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB 7 1812 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK 0x00000000000000ff 1813 1814 1815 /* Description GENERATED_CBF_DETAILS_OFFSET 1816 1817 Offset in units of 4 bytes of 'PHYRX_GENERATED_CBF_DETAILS' 1818 within 'RX_PPDU_END'Set to zero if the TLV is not included<legal 1819 0, 70-127> 1820 */ 1821 1822 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x0000000000000058 1823 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8 1824 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15 1825 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x000000000000ff00 1826 1827 1828 /* Description PKT_END_PART1_OFFSET 1829 1830 Offset in units of 4 bytes of 'PHYRX_PKT_END_PART1' within 1831 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1832 all> 1833 */ 1834 1835 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x0000000000000058 1836 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB 16 1837 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB 23 1838 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x0000000000ff0000 1839 1840 1841 /* Description LOCATION_OFFSET 1842 1843 Offset in units of 4 bytes of 'PHYRX_LOCATION' within 'RX_PPDU_END' 1844 Set to zero if the TLV is not included<legal all> 1845 */ 1846 1847 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET 0x0000000000000058 1848 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB 24 1849 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB 31 1850 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK 0x00000000ff000000 1851 1852 1853 /* Description AZ_INTEGRITY_DATA_OFFSET 1854 1855 Offset in units of 4 bytes of 'PHYRX_11AZ_INTEGRITY_DATA' 1856 within 'RX_PPDU_END' 1857 1858 Set to zero if the TLV is not included 1859 <legal all> 1860 */ 1861 1862 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_OFFSET 0x0000000000000058 1863 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_LSB 32 1864 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_MSB 39 1865 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_MASK 0x000000ff00000000 1866 1867 1868 /* Description PKT_END_OFFSET 1869 1870 Offset in units of 4 bytes of 'PHYRX_PKT_END' within 'RX_PPDU_END' 1871 Set to zero if the TLV is not included<legal all> 1872 */ 1873 1874 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET 0x0000000000000058 1875 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB 40 1876 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB 47 1877 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK 0x0000ff0000000000 1878 1879 1880 /* Description ABORT_REQUEST_ACK_OFFSET 1881 1882 Offset in units of 4 bytes of either 'PHYRX_ABORT_REQUEST' 1883 or 'PHYRX_ABORT_ACK' within 'RX_PPDU_END' 1884 1885 Set to zero if the TLV is not included 1886 <legal all> 1887 */ 1888 1889 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000000000000058 1890 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 48 1891 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 55 1892 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff000000000000 1893 1894 1895 /* Description RESERVED_7A 1896 1897 Spare space in case the widths of the above offsets grow<legal 1898 all> 1899 */ 1900 1901 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET 0x0000000000000058 1902 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB 56 1903 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB 63 1904 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK 0xff00000000000000 1905 1906 1907 /* Description RESERVED_8A 1908 1909 Spare space in case the widths of the above offsets grow 1910 1911 <legal all> 1912 */ 1913 1914 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET 0x0000000000000060 1915 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB 0 1916 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB 31 1917 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK 0x00000000ffffffff 1918 1919 1920 /* Description RESERVED_9A 1921 1922 Spare space in case the widths of the above offsets grow 1923 1924 <legal all> 1925 */ 1926 1927 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET 0x0000000000000060 1928 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB 32 1929 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB 63 1930 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK 0xffffffff00000000 1931 1932 1933 /* Description CORRUPTED_DUE_TO_FIFO_DELAY 1934 1935 Set if Rx PCU avoided a hang due to SFM delays by writing 1936 a corrupted 'RX_PPDU_END_USER_STATS' and/or 'RX_PPDU_END.' 1937 1938 */ 1939 1940 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000068 1941 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 1942 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 1943 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000000000001 1944 1945 1946 /* Description QOS_SN_1_MORE_FRAG_STATE 1947 1948 Field only valid when QoS_SN_1_info_valid is set. 1949 1950 The 'more fragments' state of the QoS frames with TID QoS_SN_1_TID 1951 at the end of this PPDU 1952 <legal all> 1953 */ 1954 1955 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET 0x0000000000000068 1956 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB 1 1957 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB 1 1958 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK 0x0000000000000002 1959 1960 1961 /* Description QOS_SN_1_FRAG_NUM_STATE 1962 1963 Field only valid when QoS_SN_1_info_valid is set. 1964 1965 The 'fragment number' state of the QoS frames with TID QoS_SN_1_TID 1966 at the end of this PPDU 1967 <legal all> 1968 */ 1969 1970 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET 0x0000000000000068 1971 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB 2 1972 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB 5 1973 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK 0x000000000000003c 1974 1975 1976 /* Description QOS_SN_2_MORE_FRAG_STATE 1977 1978 Field only valid when QoS_SN_2_info_valid is set. 1979 1980 The 'more fragments' state of the QoS frames with TID QoS_SN_2_TID 1981 at the end of this PPDU 1982 <legal all> 1983 */ 1984 1985 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET 0x0000000000000068 1986 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB 6 1987 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB 6 1988 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK 0x0000000000000040 1989 1990 1991 /* Description QOS_SN_2_FRAG_NUM_STATE 1992 1993 Field only valid when QoS_SN_2_info_valid is set. 1994 1995 The 'fragment number' state of the QoS frames with TID QoS_SN_2_TID 1996 at the end of this PPDU 1997 <legal all> 1998 */ 1999 2000 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET 0x0000000000000068 2001 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB 7 2002 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB 10 2003 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK 0x0000000000000780 2004 2005 2006 /* Description RESERVED_26A 2007 2008 <legal 0> 2009 */ 2010 2011 #define RXPCU_PPDU_END_INFO_RESERVED_26A_OFFSET 0x0000000000000068 2012 #define RXPCU_PPDU_END_INFO_RESERVED_26A_LSB 11 2013 #define RXPCU_PPDU_END_INFO_RESERVED_26A_MSB 31 2014 #define RXPCU_PPDU_END_INFO_RESERVED_26A_MASK 0x00000000fffff800 2015 2016 2017 /* Description RX_PPDU_END_MARKER 2018 2019 Field used by SW to double check that their structure alignment 2020 is in sync with what HW has done. 2021 <legal 0xAABBCCDD> 2022 */ 2023 2024 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET 0x0000000000000068 2025 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB 32 2026 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB 63 2027 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK 0xffffffff00000000 2028 2029 2030 2031 #endif // RXPCU_PPDU_END_INFO 2032