1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_ 27 #define _RXPCU_PPDU_END_LAYOUT_INFO_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10 32 33 34 struct rxpcu_ppdu_end_layout_info { 35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 36 uint32_t rssi_legacy_offset : 2, // [1:0] 37 l_sig_a_offset : 6, // [7:2] 38 l_sig_b_offset : 6, // [13:8] 39 ht_sig_offset : 6, // [19:14] 40 vht_sig_a_offset : 6, // [25:20] 41 repeat_l_sig_a_offset : 6; // [31:26] 42 uint32_t he_sig_a_su_offset : 6, // [5:0] 43 he_sig_a_mu_dl_offset : 6, // [11:6] 44 he_sig_a_mu_ul_offset : 6, // [17:12] 45 generic_u_sig_offset : 6, // [23:18] 46 rssi_ht_offset : 7, // [30:24] 47 reserved_1a : 1; // [31:31] 48 uint32_t vht_sig_b_su20_offset : 7, // [6:0] 49 vht_sig_b_su40_offset : 7, // [13:7] 50 vht_sig_b_su80_offset : 7, // [20:14] 51 vht_sig_b_su160_offset : 7, // [27:21] 52 reserved_2a : 4; // [31:28] 53 uint32_t vht_sig_b_mu20_offset : 7, // [6:0] 54 vht_sig_b_mu40_offset : 7, // [13:7] 55 vht_sig_b_mu80_offset : 7, // [20:14] 56 vht_sig_b_mu160_offset : 7, // [27:21] 57 reserved_3a : 4; // [31:28] 58 uint32_t he_sig_b1_mu_offset : 7, // [6:0] 59 he_sig_b2_mu_offset : 7, // [13:7] 60 he_sig_b2_ofdma_offset : 7, // [20:14] 61 first_generic_eht_sig_offset : 7, // [27:21] 62 multiple_generic_eht_sig_included : 1, // [28:28] 63 reserved_4a : 3; // [31:29] 64 uint32_t common_user_info_offset : 7, // [6:0] 65 first_debug_info_offset : 8, // [14:7] 66 multiple_debug_info_included : 1, // [15:15] 67 first_other_receive_info_offset : 8, // [23:16] 68 multiple_other_receive_info_included : 1, // [24:24] 69 reserved_5a : 7; // [31:25] 70 uint32_t data_done_offset : 8, // [7:0] 71 generated_cbf_details_offset : 8, // [15:8] 72 pkt_end_part1_offset : 8, // [23:16] 73 location_offset : 8; // [31:24] 74 uint32_t az_integrity_data_offset : 8, // [7:0] 75 pkt_end_offset : 8, // [15:8] 76 abort_request_ack_offset : 8, // [23:16] 77 reserved_7a : 8; // [31:24] 78 uint32_t reserved_8a : 32; // [31:0] 79 uint32_t reserved_9a : 32; // [31:0] 80 #else 81 uint32_t repeat_l_sig_a_offset : 6, // [31:26] 82 vht_sig_a_offset : 6, // [25:20] 83 ht_sig_offset : 6, // [19:14] 84 l_sig_b_offset : 6, // [13:8] 85 l_sig_a_offset : 6, // [7:2] 86 rssi_legacy_offset : 2; // [1:0] 87 uint32_t reserved_1a : 1, // [31:31] 88 rssi_ht_offset : 7, // [30:24] 89 generic_u_sig_offset : 6, // [23:18] 90 he_sig_a_mu_ul_offset : 6, // [17:12] 91 he_sig_a_mu_dl_offset : 6, // [11:6] 92 he_sig_a_su_offset : 6; // [5:0] 93 uint32_t reserved_2a : 4, // [31:28] 94 vht_sig_b_su160_offset : 7, // [27:21] 95 vht_sig_b_su80_offset : 7, // [20:14] 96 vht_sig_b_su40_offset : 7, // [13:7] 97 vht_sig_b_su20_offset : 7; // [6:0] 98 uint32_t reserved_3a : 4, // [31:28] 99 vht_sig_b_mu160_offset : 7, // [27:21] 100 vht_sig_b_mu80_offset : 7, // [20:14] 101 vht_sig_b_mu40_offset : 7, // [13:7] 102 vht_sig_b_mu20_offset : 7; // [6:0] 103 uint32_t reserved_4a : 3, // [31:29] 104 multiple_generic_eht_sig_included : 1, // [28:28] 105 first_generic_eht_sig_offset : 7, // [27:21] 106 he_sig_b2_ofdma_offset : 7, // [20:14] 107 he_sig_b2_mu_offset : 7, // [13:7] 108 he_sig_b1_mu_offset : 7; // [6:0] 109 uint32_t reserved_5a : 7, // [31:25] 110 multiple_other_receive_info_included : 1, // [24:24] 111 first_other_receive_info_offset : 8, // [23:16] 112 multiple_debug_info_included : 1, // [15:15] 113 first_debug_info_offset : 8, // [14:7] 114 common_user_info_offset : 7; // [6:0] 115 uint32_t location_offset : 8, // [31:24] 116 pkt_end_part1_offset : 8, // [23:16] 117 generated_cbf_details_offset : 8, // [15:8] 118 data_done_offset : 8; // [7:0] 119 uint32_t reserved_7a : 8, // [31:24] 120 abort_request_ack_offset : 8, // [23:16] 121 pkt_end_offset : 8, // [15:8] 122 az_integrity_data_offset : 8; // [7:0] 123 uint32_t reserved_8a : 32; // [31:0] 124 uint32_t reserved_9a : 32; // [31:0] 125 #endif 126 }; 127 128 129 /* Description RSSI_LEGACY_OFFSET 130 131 Offset in units of 4 bytes of 'PHYRX_RSSI_LEGACY' within 132 'RX_PPDU_END'<legal 1, 2> 133 */ 134 135 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET 0x00000000 136 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB 0 137 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB 1 138 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK 0x00000003 139 140 141 /* Description L_SIG_A_OFFSET 142 143 Offset in units of 4 bytes of 'PHYRX_L_SIG_A' within 'RX_PPDU_END' 144 Set to zero if the TLV is not included<legal 0, 44, 46> 145 */ 146 147 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET 0x00000000 148 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB 2 149 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB 7 150 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK 0x000000fc 151 152 153 /* Description L_SIG_B_OFFSET 154 155 Offset in units of 4 bytes of 'PHYRX_L_SIG_A' within 'RX_PPDU_END' 156 Set to zero if the TLV is not included<legal 0, 44, 46> 157 */ 158 159 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET 0x00000000 160 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB 8 161 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB 13 162 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK 0x00003f00 163 164 165 /* Description HT_SIG_OFFSET 166 167 Offset of 'PHYRX_HT_SIG' within 'RX_PPDU_END' Set to zero 168 if the TLV is not included<legal 0, 46, 50> 169 */ 170 171 #define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET 0x00000000 172 #define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB 14 173 #define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB 19 174 #define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK 0x000fc000 175 176 177 /* Description VHT_SIG_A_OFFSET 178 179 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_A' within 'RX_PPDU_END' 180 Set to zero if the TLV is not included<legal 0, 46, 50> 181 */ 182 183 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET 0x00000000 184 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB 20 185 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB 25 186 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK 0x03f00000 187 188 189 /* Description REPEAT_L_SIG_A_OFFSET 190 191 Offset in units of 4 bytes of the repeat 'PHYRX_L_SIG_A' (in 192 HE and EHT cases) within 'RX_PPDU_END' 193 194 Set to zero if the TLV is not included 195 <legal 0, 46, 50> 196 */ 197 198 #define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000000 199 #define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB 26 200 #define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB 31 201 #define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000 202 203 204 /* Description HE_SIG_A_SU_OFFSET 205 206 Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_SU' within 207 'RX_PPDU_END' Set to zero if the TLV is not included<legal 208 0, 48, 54> 209 */ 210 211 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET 0x00000004 212 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB 0 213 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB 5 214 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK 0x0000003f 215 216 217 /* Description HE_SIG_A_MU_DL_OFFSET 218 219 Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_MU_DL' within 220 'RX_PPDU_END' Set to zero if the TLV is not included<legal 221 0, 48, 54> 222 */ 223 224 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000004 225 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB 6 226 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB 11 227 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0 228 229 230 /* Description HE_SIG_A_MU_UL_OFFSET 231 232 Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_MU_UL' within 233 'RX_PPDU_END' Set to zero if the TLV is not included<legal 234 0, 48, 54> 235 */ 236 237 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000004 238 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB 12 239 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB 17 240 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000 241 242 243 /* Description GENERIC_U_SIG_OFFSET 244 245 Offset in units of 4 bytes of 'PHYRX_GENERIC_U_SIG' within 246 'RX_PPDU_END' Set to zero if the TLV is not included<legal 247 0, 48, 54> 248 */ 249 250 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET 0x00000004 251 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB 18 252 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB 23 253 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000 254 255 256 /* Description RSSI_HT_OFFSET 257 258 Offset in units of 4 bytes of 'PHYRX_RSSI_HT' within 'RX_PPDU_END' 259 Set to zero if the TLV is not included<legal 0, 49-127> 260 */ 261 262 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET 0x00000004 263 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB 24 264 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB 30 265 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK 0x7f000000 266 267 268 /* Description RESERVED_1A 269 270 <legal 0> 271 */ 272 273 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET 0x00000004 274 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB 31 275 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB 31 276 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK 0x80000000 277 278 279 /* Description VHT_SIG_B_SU20_OFFSET 280 281 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU20' within 282 'RX_PPDU_END' Set to zero if the TLV is not included<legal 283 0, 67, 74> 284 */ 285 286 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000008 287 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB 0 288 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB 6 289 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f 290 291 292 /* Description VHT_SIG_B_SU40_OFFSET 293 294 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU40' within 295 'RX_PPDU_END' Set to zero if the TLV is not included<legal 296 0, 67, 74> 297 */ 298 299 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000008 300 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB 7 301 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB 13 302 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80 303 304 305 /* Description VHT_SIG_B_SU80_OFFSET 306 307 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU80' within 308 'RX_PPDU_END' Set to zero if the TLV is not included<legal 309 0, 67, 74> 310 */ 311 312 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000008 313 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB 14 314 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB 20 315 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000 316 317 318 /* Description VHT_SIG_B_SU160_OFFSET 319 320 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU160' within 321 'RX_PPDU_END' Set to zero if the TLV is not included<legal 322 0, 67, 74> 323 */ 324 325 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000008 326 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB 21 327 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB 27 328 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000 329 330 331 /* Description RESERVED_2A 332 333 <legal 0> 334 */ 335 336 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET 0x00000008 337 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB 28 338 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB 31 339 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK 0xf0000000 340 341 342 /* Description VHT_SIG_B_MU20_OFFSET 343 344 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU20' within 345 'RX_PPDU_END' Set to zero if the TLV is not included<legal 346 0, 67, 74> 347 */ 348 349 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000c 350 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB 0 351 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB 6 352 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f 353 354 355 /* Description VHT_SIG_B_MU40_OFFSET 356 357 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU40' within 358 'RX_PPDU_END' Set to zero if the TLV is not included<legal 359 0, 67, 74> 360 */ 361 362 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000c 363 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB 7 364 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB 13 365 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80 366 367 368 /* Description VHT_SIG_B_MU80_OFFSET 369 370 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU80' within 371 'RX_PPDU_END' Set to zero if the TLV is not included<legal 372 0, 67, 74> 373 */ 374 375 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000c 376 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB 14 377 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB 20 378 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000 379 380 381 /* Description VHT_SIG_B_MU160_OFFSET 382 383 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU160' within 384 'RX_PPDU_END' Set to zero if the TLV is not included<legal 385 0, 67, 74> 386 */ 387 388 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000c 389 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB 21 390 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB 27 391 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000 392 393 394 /* Description RESERVED_3A 395 396 <legal 0> 397 */ 398 399 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET 0x0000000c 400 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB 28 401 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB 31 402 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK 0xf0000000 403 404 405 /* Description HE_SIG_B1_MU_OFFSET 406 407 Offset in units of 4 bytes of 'PHYRX_HE_SIG_B1_MU' within 408 'RX_PPDU_END' Set to zero if the TLV is not included<legal 409 0, 51, 58> 410 */ 411 412 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000010 413 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB 0 414 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB 6 415 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f 416 417 418 /* Description HE_SIG_B2_MU_OFFSET 419 420 Offset in units of 4 bytes of 'PHYRX_HE_SIG_B2_MU' within 421 'RX_PPDU_END' Set to zero if the TLV is not included<legal 422 0, 51, 58> 423 */ 424 425 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000010 426 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB 7 427 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB 13 428 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80 429 430 431 /* Description HE_SIG_B2_OFDMA_OFFSET 432 433 Offset in units of 4 bytes of 'PHYRX_HE_SIG_B2_OFDMA' within 434 'RX_PPDU_END' Set to zero if the TLV is not included<legal 435 0, 53, 62> 436 */ 437 438 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000010 439 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB 14 440 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB 20 441 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000 442 443 444 /* Description FIRST_GENERIC_EHT_SIG_OFFSET 445 446 Offset in units of 4 bytes of the first 'PHYRX_GENERIC_EHT_SIG' 447 within 'RX_PPDU_END' Set to zero if the TLV is not included<legal 448 0, 51, 58> 449 */ 450 451 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000010 452 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 453 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 454 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000 455 456 457 /* Description MULTIPLE_GENERIC_EHT_SIG_INCLUDED 458 459 Set to one if more than one 'PHYRX_GENERIC_EHT_SIG' TLVs 460 are included in 'RX_PPDU_END,' set to zero otherwise 461 <legal all> 462 */ 463 464 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000010 465 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 466 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 467 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000 468 469 470 /* Description RESERVED_4A 471 472 <legal 0> 473 */ 474 475 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET 0x00000010 476 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB 29 477 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB 31 478 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK 0xe0000000 479 480 481 /* Description COMMON_USER_INFO_OFFSET 482 483 Offset in units of 4 bytes of 'PHYRX_COMMON_USER_INFO' within 484 'RX_PPDU_END' Set to zero if the TLV is not included<legal 485 0, 46, 50, 67, 70-127> 486 */ 487 488 #define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET 0x00000014 489 #define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB 0 490 #define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB 6 491 #define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK 0x0000007f 492 493 494 /* Description FIRST_DEBUG_INFO_OFFSET 495 496 Offset in units of 4 bytes of the first 'PHYRX_DEBUG_INFO' 497 within 'RX_PPDU_END' Set to zero if the TLV is not included<legal 498 all> 499 */ 500 501 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000014 502 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB 7 503 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB 14 504 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80 505 506 507 /* Description MULTIPLE_DEBUG_INFO_INCLUDED 508 509 Set to one if more than one 'PHYRX_DEBUG_INFO' TLVs are 510 included in 'RX_PPDU_END,' set to zero otherwise<legal all> 511 512 */ 513 514 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000014 515 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15 516 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15 517 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000 518 519 520 /* Description FIRST_OTHER_RECEIVE_INFO_OFFSET 521 522 Offset in units of 4 bytes of the first 'PHYRX_OTHER_RECEIVE_INFO' 523 within 'RX_PPDU_END' Set to zero if the TLV is not included<legal 524 all> 525 */ 526 527 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000014 528 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16 529 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23 530 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000 531 532 533 /* Description MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED 534 535 Set to one if more than one 'PHYRX_OTHER_RECEIVE_INFO' TLVs 536 are included in 'RX_PPDU_END,' set to zero otherwise<legal 537 all> 538 */ 539 540 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000014 541 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24 542 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24 543 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000 544 545 546 /* Description RESERVED_5A 547 548 <legal 0> 549 */ 550 551 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET 0x00000014 552 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB 25 553 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB 31 554 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK 0xfe000000 555 556 557 /* Description DATA_DONE_OFFSET 558 559 Offset in units of 4 bytes of 'PHYRX_DATA_DONE' within 'RX_PPDU_END' 560 Set to zero if the TLV is not included<legal all> 561 */ 562 563 #define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET 0x00000018 564 #define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB 0 565 #define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB 7 566 #define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK 0x000000ff 567 568 569 /* Description GENERATED_CBF_DETAILS_OFFSET 570 571 Offset in units of 4 bytes of 'PHYRX_GENERATED_CBF_DETAILS' 572 within 'RX_PPDU_END'Set to zero if the TLV is not included<legal 573 0, 70-127> 574 */ 575 576 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000018 577 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB 8 578 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB 15 579 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00 580 581 582 /* Description PKT_END_PART1_OFFSET 583 584 Offset in units of 4 bytes of 'PHYRX_PKT_END_PART1' within 585 'RX_PPDU_END' Set to zero if the TLV is not included<legal 586 all> 587 */ 588 589 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET 0x00000018 590 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB 16 591 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB 23 592 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK 0x00ff0000 593 594 595 /* Description LOCATION_OFFSET 596 597 Offset in units of 4 bytes of 'PHYRX_LOCATION' within 'RX_PPDU_END' 598 Set to zero if the TLV is not included<legal all> 599 */ 600 601 #define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET 0x00000018 602 #define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB 24 603 #define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB 31 604 #define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK 0xff000000 605 606 607 /* Description AZ_INTEGRITY_DATA_OFFSET 608 609 Offset in units of 4 bytes of 'PHYRX_11AZ_INTEGRITY_DATA' 610 within 'RX_PPDU_END' 611 612 Set to zero if the TLV is not included 613 <legal all> 614 */ 615 616 #define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_OFFSET 0x0000001c 617 #define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_LSB 0 618 #define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_MSB 7 619 #define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_MASK 0x000000ff 620 621 622 /* Description PKT_END_OFFSET 623 624 Offset in units of 4 bytes of 'PHYRX_PKT_END' within 'RX_PPDU_END' 625 Set to zero if the TLV is not included<legal all> 626 */ 627 628 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET 0x0000001c 629 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB 8 630 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB 15 631 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK 0x0000ff00 632 633 634 /* Description ABORT_REQUEST_ACK_OFFSET 635 636 Offset in units of 4 bytes of either 'PHYRX_ABORT_REQUEST' 637 or 'PHYRX_ABORT_ACK' within 'RX_PPDU_END' 638 639 Set to zero if the TLV is not included 640 <legal all> 641 */ 642 643 #define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000001c 644 #define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB 16 645 #define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB 23 646 #define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000 647 648 649 /* Description RESERVED_7A 650 651 Spare space in case the widths of the above offsets grow<legal 652 all> 653 */ 654 655 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET 0x0000001c 656 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB 24 657 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB 31 658 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK 0xff000000 659 660 661 /* Description RESERVED_8A 662 663 Spare space in case the widths of the above offsets grow 664 665 <legal all> 666 */ 667 668 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET 0x00000020 669 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB 0 670 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB 31 671 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK 0xffffffff 672 673 674 /* Description RESERVED_9A 675 676 Spare space in case the widths of the above offsets grow 677 678 <legal all> 679 */ 680 681 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET 0x00000024 682 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB 0 683 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB 31 684 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK 0xffffffff 685 686 687 688 #endif // RXPCU_PPDU_END_LAYOUT_INFO 689