xref: /wlan-driver/fw-api/hw/qca5332/sw_monitor_ring.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 
2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 
19 
20 
21 
22 
23 
24 
25 
26 #ifndef _SW_MONITOR_RING_H_
27 #define _SW_MONITOR_RING_H_
28 #if !defined(__ASSEMBLER__)
29 #endif
30 
31 #include "buffer_addr_info.h"
32 #include "rx_mpdu_details.h"
33 #define NUM_OF_DWORDS_SW_MONITOR_RING 8
34 
35 
36 struct sw_monitor_ring {
37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
38              struct   rx_mpdu_details                                           reo_level_mpdu_frame_info;
39              struct   buffer_addr_info                                          status_buff_addr_info;
40              uint32_t rxdma_push_reason                                       :  2, // [1:0]
41                       rxdma_error_code                                        :  5, // [6:2]
42                       mpdu_fragment_number                                    :  4, // [10:7]
43                       frameless_bar                                           :  1, // [11:11]
44                       status_buf_count                                        :  4, // [15:12]
45                       end_of_ppdu                                             :  1, // [16:16]
46                       reserved_6a                                             : 15; // [31:17]
47              uint32_t phy_ppdu_id                                             : 16, // [15:0]
48                       reserved_7a                                             :  4, // [19:16]
49                       ring_id                                                 :  8, // [27:20]
50                       looping_count                                           :  4; // [31:28]
51 #else
52              struct   rx_mpdu_details                                           reo_level_mpdu_frame_info;
53              struct   buffer_addr_info                                          status_buff_addr_info;
54              uint32_t reserved_6a                                             : 15, // [31:17]
55                       end_of_ppdu                                             :  1, // [16:16]
56                       status_buf_count                                        :  4, // [15:12]
57                       frameless_bar                                           :  1, // [11:11]
58                       mpdu_fragment_number                                    :  4, // [10:7]
59                       rxdma_error_code                                        :  5, // [6:2]
60                       rxdma_push_reason                                       :  2; // [1:0]
61              uint32_t looping_count                                           :  4, // [31:28]
62                       ring_id                                                 :  8, // [27:20]
63                       reserved_7a                                             :  4, // [19:16]
64                       phy_ppdu_id                                             : 16; // [15:0]
65 #endif
66 };
67 
68 
69 /* Description		REO_LEVEL_MPDU_FRAME_INFO
70 
71 			Consumer: SW
72 			Producer: RXDMA
73 
74 			Details related to the MPDU being pushed to SW, valid only
75 			 if end_of_ppdu is set to 0
76 */
77 
78 
79 /* Description		MSDU_LINK_DESC_ADDR_INFO
80 
81 			Consumer: REO/SW/FW
82 			Producer: RXDMA
83 
84 			Details of the physical address of the MSDU link descriptor
85 			 that contains pointers to MSDUs related to this MPDU
86 */
87 
88 
89 /* Description		BUFFER_ADDR_31_0
90 
91 			Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
92 			 descriptor OR Link Descriptor
93 
94 			In case of 'NULL' pointer, this field is set to 0
95 			<legal all>
96 */
97 
98 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
99 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
100 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
101 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
102 
103 
104 /* Description		BUFFER_ADDR_39_32
105 
106 			Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
107 			 descriptor OR Link Descriptor
108 
109 			In case of 'NULL' pointer, this field is set to 0
110 			<legal all>
111 */
112 
113 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
114 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
115 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
116 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
117 
118 
119 /* Description		RETURN_BUFFER_MANAGER
120 
121 			Consumer: WBM
122 			Producer: SW/FW
123 
124 			In case of 'NULL' pointer, this field is set to 0
125 
126 			Indicates to which buffer manager the buffer OR MSDU_EXTENSION
127 			 descriptor OR link descriptor that is being pointed to
128 			shall be returned after the frame has been processed. It
129 			 is used by WBM for routing purposes.
130 
131 			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
132 			 to the WMB buffer idle list
133 			<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
134 			 to the WBM idle link descriptor idle list, where the chip
135 			 0 WBM is chosen in case of a multi-chip config
136 			<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
137 			 to the chip 1 WBM idle link descriptor idle list
138 			<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
139 			 to the chip 2 WBM idle link descriptor idle list
140 			<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
141 			returned to chip 3 WBM idle link descriptor idle list
142 			<enum 4 FW_BM> This buffer shall be returned to the FW
143 			<enum 5 SW0_BM> This buffer shall be returned to the SW,
144 			ring 0
145 			<enum 6 SW1_BM> This buffer shall be returned to the SW,
146 			ring 1
147 			<enum 7 SW2_BM> This buffer shall be returned to the SW,
148 			ring 2
149 			<enum 8 SW3_BM> This buffer shall be returned to the SW,
150 			ring 3
151 			<enum 9 SW4_BM> This buffer shall be returned to the SW,
152 			ring 4
153 			<enum 10 SW5_BM> This buffer shall be returned to the SW,
154 			ring 5
155 			<enum 11 SW6_BM> This buffer shall be returned to the SW,
156 			ring 6
157 
158 			<legal 0-12>
159 */
160 
161 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
162 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
163 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
164 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
165 
166 
167 /* Description		SW_BUFFER_COOKIE
168 
169 			Cookie field exclusively used by SW.
170 
171 			In case of 'NULL' pointer, this field is set to 0
172 
173 			HW ignores the contents, accept that it passes the programmed
174 			 value on to other descriptors together with the physical
175 			 address
176 
177 			Field can be used by SW to for example associate the buffers
178 			 physical address with the virtual address
179 			The bit definitions as used by SW are within SW HLD specification
180 
181 
182 			NOTE1:
183 			The three most significant bits can have a special meaning
184 			 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
185 			and field transmit_bw_restriction is set
186 
187 			In case of NON punctured transmission:
188 			Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
189 			Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
190 			Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
191 			Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
192 			Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
193 			Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
194 			Sw_buffer_cookie[19:18] = 2'b11: reserved
195 
196 			In case of punctured transmission:
197 			Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
198 			Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
199 			Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
200 			Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
201 			Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
202 			Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
203 			Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
204 			Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
205 			Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
206 			Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
207 			Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
208 			Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
209 			Sw_buffer_cookie[19:18] = 2'b11: reserved
210 
211 			Note: a punctured transmission is indicated by the presence
212 			 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
213 
214 			<legal all>
215 */
216 
217 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
218 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
219 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
220 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
221 
222 
223 /* Description		RX_MPDU_DESC_INFO_DETAILS
224 
225 			Consumer: REO/SW/FW
226 			Producer: RXDMA
227 
228 			General information related to the MPDU that should be passed
229 			 on from REO entrance ring to the REO destination ring
230 */
231 
232 
233 /* Description		MSDU_COUNT
234 
235 			Consumer: REO/SW/FW
236 			Producer: RXDMA
237 
238 			The number of MSDUs within the MPDU
239 			<legal all>
240 */
241 
242 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
243 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
244 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7
245 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
246 
247 
248 /* Description		FRAGMENT_FLAG
249 
250 			Consumer: REO/SW/FW
251 			Producer: RXDMA
252 
253 			When set, this MPDU is a fragment and REO should forward
254 			 this fragment MPDU to the REO destination ring without
255 			any reorder checks, pn checks or bitmap update. This implies
256 			 that REO is forwarding the pointer to the MSDU link descriptor.
257 			The destination ring is coming from a programmable register
258 			 setting in REO
259 
260 			<legal all>
261 */
262 
263 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
264 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8
265 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8
266 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100
267 
268 
269 /* Description		MPDU_RETRY_BIT
270 
271 			Consumer: REO/SW/FW
272 			Producer: RXDMA
273 
274 			The retry bit setting from the MPDU header of the received
275 			 frame
276 			<legal all>
277 */
278 
279 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
280 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9
281 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9
282 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200
283 
284 
285 /* Description		AMPDU_FLAG
286 
287 			Consumer: REO/SW/FW
288 			Producer: RXDMA
289 
290 			When set, the MPDU was received as part of an A-MPDU.
291 			<legal all>
292 */
293 
294 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
295 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10
296 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10
297 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400
298 
299 
300 /* Description		BAR_FRAME
301 
302 			Consumer: REO/SW/FW
303 			Producer: RXDMA
304 
305 			When set, the received frame is a BAR frame. After processing,
306 			this frame shall be pushed to SW or deleted.
307 			<legal all>
308 */
309 
310 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
311 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11
312 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11
313 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800
314 
315 
316 /* Description		PN_FIELDS_CONTAIN_VALID_INFO
317 
318 			Consumer: REO/SW/FW
319 			Producer: RXDMA
320 
321 			Copied here by RXDMA from RX_MPDU_END
322 			When not set, REO will Not perform a PN sequence number
323 			check
324 */
325 
326 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
327 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
328 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
329 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
330 
331 
332 /* Description		RAW_MPDU
333 
334 			Field only valid when first_msdu_in_mpdu_flag is set.
335 
336 			When set, the contents in the MSDU buffer contains a 'RAW'
337 			MPDU. This 'RAW' MPDU might be spread out over multiple
338 			MSDU buffers.
339 			<legal all>
340 */
341 
342 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
343 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13
344 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13
345 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000
346 
347 
348 /* Description		MORE_FRAGMENT_FLAG
349 
350 			The More Fragment bit setting from the MPDU header of the
351 			 received frame
352 
353 			<legal all>
354 */
355 
356 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
357 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
358 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14
359 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
360 
361 
362 /* Description		SRC_INFO
363 
364 			Source (virtual) device/interface info. associated with
365 			this peer
366 
367 			This field gets passed on by REO to PPE in the EDMA descriptor
368 			 ('REO_TO_PPE_RING').
369 
370 			Hamilton v1 used this for 'vdev_id' instead.
371 			<legal all>
372 */
373 
374 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008
375 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15
376 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26
377 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000
378 
379 
380 /* Description		MPDU_QOS_CONTROL_VALID
381 
382 			When set, the MPDU has a QoS control field.
383 
384 			In case of ndp or phy_err, this field will never be set.
385 
386 			<legal all>
387 */
388 
389 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
390 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
391 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
392 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
393 
394 
395 /* Description		TID
396 
397 			Field only valid when mpdu_qos_control_valid is set
398 
399 			The TID field in the QoS control field
400 			<legal all>
401 */
402 
403 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008
404 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28
405 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31
406 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000
407 
408 
409 /* Description		PEER_META_DATA
410 
411 			Meta data that SW has programmed in the Peer table entry
412 			 of the transmitting STA.
413 			<legal all>
414 */
415 
416 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
417 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
418 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31
419 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
420 
421 
422 /* Description		STATUS_BUFF_ADDR_INFO
423 
424 			Consumer: SW
425 			Producer: RXDMA
426 
427 			Details of the physical address of the first status buffer
428 			 used for the PPDU (either the PPDU that included the MPDU
429 			 being pushed to SW if end_of_ppdu = 0, or the PPDU whose
430 			 end is indicated through end_of_ppdu = 1)
431 */
432 
433 
434 /* Description		BUFFER_ADDR_31_0
435 
436 			Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
437 			 descriptor OR Link Descriptor
438 
439 			In case of 'NULL' pointer, this field is set to 0
440 			<legal all>
441 */
442 
443 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET               0x00000010
444 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_LSB                  0
445 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_MSB                  31
446 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_MASK                 0xffffffff
447 
448 
449 /* Description		BUFFER_ADDR_39_32
450 
451 			Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
452 			 descriptor OR Link Descriptor
453 
454 			In case of 'NULL' pointer, this field is set to 0
455 			<legal all>
456 */
457 
458 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET              0x00000014
459 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_LSB                 0
460 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_MSB                 7
461 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_MASK                0x000000ff
462 
463 
464 /* Description		RETURN_BUFFER_MANAGER
465 
466 			Consumer: WBM
467 			Producer: SW/FW
468 
469 			In case of 'NULL' pointer, this field is set to 0
470 
471 			Indicates to which buffer manager the buffer OR MSDU_EXTENSION
472 			 descriptor OR link descriptor that is being pointed to
473 			shall be returned after the frame has been processed. It
474 			 is used by WBM for routing purposes.
475 
476 			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
477 			 to the WMB buffer idle list
478 			<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
479 			 to the WBM idle link descriptor idle list, where the chip
480 			 0 WBM is chosen in case of a multi-chip config
481 			<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
482 			 to the chip 1 WBM idle link descriptor idle list
483 			<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
484 			 to the chip 2 WBM idle link descriptor idle list
485 			<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
486 			returned to chip 3 WBM idle link descriptor idle list
487 			<enum 4 FW_BM> This buffer shall be returned to the FW
488 			<enum 5 SW0_BM> This buffer shall be returned to the SW,
489 			ring 0
490 			<enum 6 SW1_BM> This buffer shall be returned to the SW,
491 			ring 1
492 			<enum 7 SW2_BM> This buffer shall be returned to the SW,
493 			ring 2
494 			<enum 8 SW3_BM> This buffer shall be returned to the SW,
495 			ring 3
496 			<enum 9 SW4_BM> This buffer shall be returned to the SW,
497 			ring 4
498 			<enum 10 SW5_BM> This buffer shall be returned to the SW,
499 			ring 5
500 			<enum 11 SW6_BM> This buffer shall be returned to the SW,
501 			ring 6
502 
503 			<legal 0-12>
504 */
505 
506 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET          0x00000014
507 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB             8
508 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB             11
509 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK            0x00000f00
510 
511 
512 /* Description		SW_BUFFER_COOKIE
513 
514 			Cookie field exclusively used by SW.
515 
516 			In case of 'NULL' pointer, this field is set to 0
517 
518 			HW ignores the contents, accept that it passes the programmed
519 			 value on to other descriptors together with the physical
520 			 address
521 
522 			Field can be used by SW to for example associate the buffers
523 			 physical address with the virtual address
524 			The bit definitions as used by SW are within SW HLD specification
525 
526 
527 			NOTE1:
528 			The three most significant bits can have a special meaning
529 			 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
530 			and field transmit_bw_restriction is set
531 
532 			In case of NON punctured transmission:
533 			Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
534 			Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
535 			Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
536 			Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
537 			Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
538 			Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
539 			Sw_buffer_cookie[19:18] = 2'b11: reserved
540 
541 			In case of punctured transmission:
542 			Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
543 			Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
544 			Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
545 			Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
546 			Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
547 			Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
548 			Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
549 			Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
550 			Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
551 			Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
552 			Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
553 			Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
554 			Sw_buffer_cookie[19:18] = 2'b11: reserved
555 
556 			Note: a punctured transmission is indicated by the presence
557 			 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
558 
559 			<legal all>
560 */
561 
562 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET               0x00000014
563 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_LSB                  12
564 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_MSB                  31
565 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_MASK                 0xfffff000
566 
567 
568 /* Description		RXDMA_PUSH_REASON
569 
570 			Indicates why RXDMA pushed the frame to this ring
571 
572 			<enum 0 rxdma_error_detected> RXDMA detected an error an
573 			 pushed this frame to this queue
574 			<enum 1 rxdma_routing_instruction> RXDMA pushed the frame
575 			 to this queue per received routing instructions. No error
576 			 within RXDMA was detected
577 			<enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a
578 			 result the MSDU link descriptor might not have the "last_msdu_in_mpdu_flag"
579 			set, but instead WBM might just see a NULL pointer in the
580 			 MSDU link descriptor. This is to be considered a normal
581 			 condition for this scenario.
582 
583 			<legal 0 - 2>
584 */
585 
586 #define SW_MONITOR_RING_RXDMA_PUSH_REASON_OFFSET                                    0x00000018
587 #define SW_MONITOR_RING_RXDMA_PUSH_REASON_LSB                                       0
588 #define SW_MONITOR_RING_RXDMA_PUSH_REASON_MSB                                       1
589 #define SW_MONITOR_RING_RXDMA_PUSH_REASON_MASK                                      0x00000003
590 
591 
592 /* Description		RXDMA_ERROR_CODE
593 
594 			Field only valid when rxdma_push_reason is set to 'rxdma_error_detected.'
595 
596 
597 			<enum 0 rxdma_overflow_err>MPDU frame is not complete due
598 			 to a FIFO overflow error in RXPCU.
599 			<enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
600 			 due to receiving incomplete MPDU from the PHY
601 			<enum 2 rxdma_fcs_err>FCS check on the MPDU frame failed
602 
603 			<enum 3 rxdma_decrypt_err>CRYPTO reported a decryption error
604 			 or CRYPTO received an encrypted frame, but did not get
605 			a valid corresponding key id in the peer entry.
606 			<enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC error
607 
608 			<enum 5 rxdma_unecrypted_err>CRYPTO reported an unencrypted
609 			 frame error when encrypted was expected
610 			<enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU length
611 			 error
612 			<enum 7 rxdma_msdu_limit_err>RX OLE reported that max number
613 			 of MSDUs allowed in an MPDU got exceeded
614 			<enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing error
615 
616 			<enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
617 			parsing error
618 			<enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
619 			during SA search
620 			<enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
621 			during DA search
622 			<enum 12 rxdma_flow_timeout_err>RX OLE reported a timeout
623 			 during flow search
624 			<enum 13 rxdma_flush_request>RXDMA received a flush request
625 
626 			<enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU
627 			 present as well as a fragmented MPDU. A-MSDU defragmentation
628 			 is not supported in Lithium SW so this is treated as an
629 			 error.
630 			<enum 15 rxdma_multicast_echo_err>RX OLE reported a multicast
631 			 echo
632 			<enum 16 rxdma_amsdu_addr_mismatch_err>RX OLE reported an
633 			 A-MSDU with either 'from DS = 0' with an SA mismatching
634 			 TA or 'to DS = 0' with a DA mismatching RA.
635 			<enum 17 rxdma_unauthorized_wds_err>RX PCU reported that
636 			 Rx peer entry did not indicate 'authorized_to_send_WDS'
637 			and also indicated 'from DS = to DS = 1.'
638 			<enum 18 rxdma_groupcast_amsdu_or_wds_err>RX PCU reported
639 			 a broadcast or multicast RA as well as either A-MSDU present
640 			 or 'from DS = to DS = 1.'
641 */
642 
643 #define SW_MONITOR_RING_RXDMA_ERROR_CODE_OFFSET                                     0x00000018
644 #define SW_MONITOR_RING_RXDMA_ERROR_CODE_LSB                                        2
645 #define SW_MONITOR_RING_RXDMA_ERROR_CODE_MSB                                        6
646 #define SW_MONITOR_RING_RXDMA_ERROR_CODE_MASK                                       0x0000007c
647 
648 
649 /* Description		MPDU_FRAGMENT_NUMBER
650 
651 			Field only valid when Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details.Fragment_flag
652 			 is set and end_of_ppdu is set to 0.
653 
654 			The fragment number from the 802.11 header.
655 
656 			Note that the sequence number is embedded in the field:
657 			Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. Mpdu_sequence_number
658 
659 
660 			<legal all>
661 */
662 
663 #define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_OFFSET                                 0x00000018
664 #define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_LSB                                    7
665 #define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_MSB                                    10
666 #define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_MASK                                   0x00000780
667 
668 
669 /* Description		FRAMELESS_BAR
670 
671 			When set, this SW monitor ring struct contains BAR info
672 			from a multi TID BAR frame. The original multi TID BAR frame
673 			 itself contained all the REO info for the first TID, but
674 			 all the subsequent TID info and their linkage to the REO
675 			 descriptors is passed down as 'frameless' BAR info.
676 
677 			The only fields valid in this descriptor when this bit is
678 			 within the
679 			Reo_level_mpdu_frame_info:
680 			   Within Rx_mpdu_desc_info_details:
681 			Mpdu_Sequence_number
682 			BAR_frame
683 			Peer_meta_data
684 			All other fields shall be set to 0.
685 
686 			<legal all>
687 */
688 
689 #define SW_MONITOR_RING_FRAMELESS_BAR_OFFSET                                        0x00000018
690 #define SW_MONITOR_RING_FRAMELESS_BAR_LSB                                           11
691 #define SW_MONITOR_RING_FRAMELESS_BAR_MSB                                           11
692 #define SW_MONITOR_RING_FRAMELESS_BAR_MASK                                          0x00000800
693 
694 
695 /* Description		STATUS_BUF_COUNT
696 
697 			A count of status buffers used so far for the PPDU (either
698 			 the PPDU that included the MPDU being pushed to SW if end_of_ppdu
699 			 = 0, or the PPDU whose end is indicated through end_of_ppdu
700 			 = 1)
701 */
702 
703 #define SW_MONITOR_RING_STATUS_BUF_COUNT_OFFSET                                     0x00000018
704 #define SW_MONITOR_RING_STATUS_BUF_COUNT_LSB                                        12
705 #define SW_MONITOR_RING_STATUS_BUF_COUNT_MSB                                        15
706 #define SW_MONITOR_RING_STATUS_BUF_COUNT_MASK                                       0x0000f000
707 
708 
709 /* Description		END_OF_PPDU
710 
711 			Pine RXDMA can be configured to generate a separate 'SW_MONITOR_RING'
712 			descriptor at the end of a PPDU (either through an 'RX_PPDU_END'
713 			TLV or through an 'RX_FLUSH') to demarcate PPDUs.
714 
715 			For such a descriptor, this bit is set to 1 and fields Reo_level_mpdu_frame_info,
716 			mpdu_fragment_number and Frameless_bar are all set to 0.
717 
718 
719 			Otherwise this bit is set to 0.
720 */
721 
722 #define SW_MONITOR_RING_END_OF_PPDU_OFFSET                                          0x00000018
723 #define SW_MONITOR_RING_END_OF_PPDU_LSB                                             16
724 #define SW_MONITOR_RING_END_OF_PPDU_MSB                                             16
725 #define SW_MONITOR_RING_END_OF_PPDU_MASK                                            0x00010000
726 
727 
728 /* Description		RESERVED_6A
729 
730 			<legal 0>
731 */
732 
733 #define SW_MONITOR_RING_RESERVED_6A_OFFSET                                          0x00000018
734 #define SW_MONITOR_RING_RESERVED_6A_LSB                                             17
735 #define SW_MONITOR_RING_RESERVED_6A_MSB                                             31
736 #define SW_MONITOR_RING_RESERVED_6A_MASK                                            0xfffe0000
737 
738 
739 /* Description		PHY_PPDU_ID
740 
741 			A PPDU counter value that PHY increments for every PPDU
742 			received
743 			The counter value wraps around. Pine RXDMA can be configured
744 			 to copy this from the RX_PPDU_START TLV for every output
745 			 descriptor.
746 
747 			<legal all>
748 */
749 
750 #define SW_MONITOR_RING_PHY_PPDU_ID_OFFSET                                          0x0000001c
751 #define SW_MONITOR_RING_PHY_PPDU_ID_LSB                                             0
752 #define SW_MONITOR_RING_PHY_PPDU_ID_MSB                                             15
753 #define SW_MONITOR_RING_PHY_PPDU_ID_MASK                                            0x0000ffff
754 
755 
756 /* Description		RESERVED_7A
757 
758 			<legal 0>
759 */
760 
761 #define SW_MONITOR_RING_RESERVED_7A_OFFSET                                          0x0000001c
762 #define SW_MONITOR_RING_RESERVED_7A_LSB                                             16
763 #define SW_MONITOR_RING_RESERVED_7A_MSB                                             19
764 #define SW_MONITOR_RING_RESERVED_7A_MASK                                            0x000f0000
765 
766 
767 /* Description		RING_ID
768 
769 			Consumer: SW/REO/DEBUG
770 			Producer: SRNG (of RXDMA)
771 
772 			For debugging.
773 			This field is filled in by the SRNG module.
774 			It help to identify the ring that is being looked <legal
775 			 all>
776 */
777 
778 #define SW_MONITOR_RING_RING_ID_OFFSET                                              0x0000001c
779 #define SW_MONITOR_RING_RING_ID_LSB                                                 20
780 #define SW_MONITOR_RING_RING_ID_MSB                                                 27
781 #define SW_MONITOR_RING_RING_ID_MASK                                                0x0ff00000
782 
783 
784 /* Description		LOOPING_COUNT
785 
786 			Consumer: SW/REO/DEBUG
787 			Producer: SRNG (of RXDMA)
788 
789 			For debugging.
790 			This field is filled in by the SRNG module.
791 
792 			A count value that indicates the number of times the producer
793 			 of entries into this Ring has looped around the ring.
794 			At initialization time, this value is set to 0. On the first
795 			 loop, this value is set to 1. After the max value is reached
796 			 allowed by the number of bits for this field, the count
797 			 value continues with 0 again.
798 
799 			In case SW is the consumer of the ring entries, it can use
800 			 this field to figure out up to where the producer of entries
801 			 has created new entries. This eliminates the need to check
802 			 where the "head pointer' of the ring is located once the
803 			 SW starts processing an interrupt indicating that new entries
804 			 have been put into this ring...
805 
806 			Also note that SW if it wants only needs to look at the
807 			LSB bit of this count value.
808 			<legal all>
809 */
810 
811 #define SW_MONITOR_RING_LOOPING_COUNT_OFFSET                                        0x0000001c
812 #define SW_MONITOR_RING_LOOPING_COUNT_LSB                                           28
813 #define SW_MONITOR_RING_LOOPING_COUNT_MSB                                           31
814 #define SW_MONITOR_RING_LOOPING_COUNT_MASK                                          0xf0000000
815 
816 
817 
818 #endif   // SW_MONITOR_RING
819