1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _TCL_STATUS_RING_H_ 27 #define _TCL_STATUS_RING_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_TCL_STATUS_RING 8 32 33 34 struct tcl_status_ring { 35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 36 uint32_t gse_ctrl : 4, // [3:0] 37 ase_fse_sel : 1, // [4:4] 38 cache_op_res : 2, // [6:5] 39 index_search_en : 1, // [7:7] 40 msdu_cnt_n : 24; // [31:8] 41 uint32_t msdu_byte_cnt_n : 32; // [31:0] 42 uint32_t msdu_timestmp_n : 32; // [31:0] 43 uint32_t cmd_meta_data_31_0 : 32; // [31:0] 44 uint32_t cmd_meta_data_63_32 : 32; // [31:0] 45 uint32_t hash_indx_val : 20, // [19:0] 46 cache_set_num : 4, // [23:20] 47 reserved_5a : 8; // [31:24] 48 uint32_t reserved_6a : 32; // [31:0] 49 uint32_t reserved_7a : 20, // [19:0] 50 ring_id : 8, // [27:20] 51 looping_count : 4; // [31:28] 52 #else 53 uint32_t msdu_cnt_n : 24, // [31:8] 54 index_search_en : 1, // [7:7] 55 cache_op_res : 2, // [6:5] 56 ase_fse_sel : 1, // [4:4] 57 gse_ctrl : 4; // [3:0] 58 uint32_t msdu_byte_cnt_n : 32; // [31:0] 59 uint32_t msdu_timestmp_n : 32; // [31:0] 60 uint32_t cmd_meta_data_31_0 : 32; // [31:0] 61 uint32_t cmd_meta_data_63_32 : 32; // [31:0] 62 uint32_t reserved_5a : 8, // [31:24] 63 cache_set_num : 4, // [23:20] 64 hash_indx_val : 20; // [19:0] 65 uint32_t reserved_6a : 32; // [31:0] 66 uint32_t looping_count : 4, // [31:28] 67 ring_id : 8, // [27:20] 68 reserved_7a : 20; // [19:0] 69 #endif 70 }; 71 72 73 /* Description GSE_CTRL 74 75 GSE control operations. This includes cache operations and 76 table entry statistics read/clear operation. 77 <enum 0 rd_stat> Report or Read statistics 78 <enum 1 srch_dis> Search disable. Report only Hash 79 <enum 2 Wr_bk_single> Write Back single entry 80 <enum 3 wr_bk_all> Write Back entire cache entry 81 <enum 4 inval_single> Invalidate single cache entry 82 <enum 5 inval_all> Invalidate entire cache 83 <enum 6 wr_bk_inval_single> Write back and Invalidate single 84 entry in cache 85 <enum 7 wr_bk_inval_all> write back and invalidate entire 86 cache 87 <enum 8 clr_stat_single> Clear statistics for single entry 88 89 <legal 0-8> 90 Rest of the values reserved. 91 For all single entry control operations (write back, Invalidate 92 or both)Statistics will be reported 93 */ 94 95 #define TCL_STATUS_RING_GSE_CTRL_OFFSET 0x00000000 96 #define TCL_STATUS_RING_GSE_CTRL_LSB 0 97 #define TCL_STATUS_RING_GSE_CTRL_MSB 3 98 #define TCL_STATUS_RING_GSE_CTRL_MASK 0x0000000f 99 100 101 /* Description ASE_FSE_SEL 102 103 Search Engine for which operation is done. 104 1'b0: Address Search Engine Result 105 1'b1: Flow Search Engine result 106 */ 107 108 #define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET 0x00000000 109 #define TCL_STATUS_RING_ASE_FSE_SEL_LSB 4 110 #define TCL_STATUS_RING_ASE_FSE_SEL_MSB 4 111 #define TCL_STATUS_RING_ASE_FSE_SEL_MASK 0x00000010 112 113 114 /* Description CACHE_OP_RES 115 116 Cache operation result. Following are results of cache operation. 117 118 <enum 0 op_done> Operation successful 119 <enum 1 not_fnd> Entry not found in Table 120 <enum 2 timeout_er> Timeout Error 121 <legal 0-2> 122 */ 123 124 #define TCL_STATUS_RING_CACHE_OP_RES_OFFSET 0x00000000 125 #define TCL_STATUS_RING_CACHE_OP_RES_LSB 5 126 #define TCL_STATUS_RING_CACHE_OP_RES_MSB 6 127 #define TCL_STATUS_RING_CACHE_OP_RES_MASK 0x00000060 128 129 130 /* Description INDEX_SEARCH_EN 131 132 When this bit is set to 1 control_buffer_addr[19:0] will 133 be considered as index of the AST or Flow table and GSE 134 commands will be executed accordingly on the entry pointed 135 by the index. 136 This feature is disabled by setting this bit to 0. 137 <enum 0 index_based_cmd_disable> 138 <enum 1 index_based_cmd_enable> 139 140 <legal all> 141 */ 142 143 #define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET 0x00000000 144 #define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB 7 145 #define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB 7 146 #define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK 0x00000080 147 148 149 /* Description MSDU_CNT_N 150 151 MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and 152 4'b1000 153 */ 154 155 #define TCL_STATUS_RING_MSDU_CNT_N_OFFSET 0x00000000 156 #define TCL_STATUS_RING_MSDU_CNT_N_LSB 8 157 #define TCL_STATUS_RING_MSDU_CNT_N_MSB 31 158 #define TCL_STATUS_RING_MSDU_CNT_N_MASK 0xffffff00 159 160 161 /* Description MSDU_BYTE_CNT_N 162 163 MSDU byte count for entry 1. Valid when GSE_CTRL is 4'b0111 164 and 4'b1000 165 */ 166 167 #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET 0x00000004 168 #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB 0 169 #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB 31 170 #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK 0xffffffff 171 172 173 /* Description MSDU_TIMESTMP_N 174 175 MSDU timestamp for entry 1. Valid when GSE_CTRL is 4'b0111 176 and 4'b1000 177 */ 178 179 #define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET 0x00000008 180 #define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB 0 181 #define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB 31 182 #define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK 0xffffffff 183 184 185 /* Description CMD_META_DATA_31_0 186 187 Meta data from input ring 188 <legal all> 189 */ 190 191 #define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET 0x0000000c 192 #define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB 0 193 #define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB 31 194 #define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK 0xffffffff 195 196 197 /* Description CMD_META_DATA_63_32 198 199 Meta data from input ring 200 <legal all> 201 */ 202 203 #define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET 0x00000010 204 #define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB 0 205 #define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB 31 206 #define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK 0xffffffff 207 208 209 /* Description HASH_INDX_VAL 210 211 Index of entry in the table in case of search pass (or) 212 213 Hash value of the entry in table in case of search failed 214 or search disable. 215 <legal all> 216 */ 217 218 #define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET 0x00000014 219 #define TCL_STATUS_RING_HASH_INDX_VAL_LSB 0 220 #define TCL_STATUS_RING_HASH_INDX_VAL_MSB 19 221 #define TCL_STATUS_RING_HASH_INDX_VAL_MASK 0x000fffff 222 223 224 /* Description CACHE_SET_NUM 225 226 Cache set number copied from TCL_GSE_CMD 227 */ 228 229 #define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET 0x00000014 230 #define TCL_STATUS_RING_CACHE_SET_NUM_LSB 20 231 #define TCL_STATUS_RING_CACHE_SET_NUM_MSB 23 232 #define TCL_STATUS_RING_CACHE_SET_NUM_MASK 0x00f00000 233 234 235 /* Description RESERVED_5A 236 237 <legal 0> 238 */ 239 240 #define TCL_STATUS_RING_RESERVED_5A_OFFSET 0x00000014 241 #define TCL_STATUS_RING_RESERVED_5A_LSB 24 242 #define TCL_STATUS_RING_RESERVED_5A_MSB 31 243 #define TCL_STATUS_RING_RESERVED_5A_MASK 0xff000000 244 245 246 /* Description RESERVED_6A 247 248 <legal 0> 249 */ 250 251 #define TCL_STATUS_RING_RESERVED_6A_OFFSET 0x00000018 252 #define TCL_STATUS_RING_RESERVED_6A_LSB 0 253 #define TCL_STATUS_RING_RESERVED_6A_MSB 31 254 #define TCL_STATUS_RING_RESERVED_6A_MASK 0xffffffff 255 256 257 /* Description RESERVED_7A 258 259 <legal 0> 260 */ 261 262 #define TCL_STATUS_RING_RESERVED_7A_OFFSET 0x0000001c 263 #define TCL_STATUS_RING_RESERVED_7A_LSB 0 264 #define TCL_STATUS_RING_RESERVED_7A_MSB 19 265 #define TCL_STATUS_RING_RESERVED_7A_MASK 0x000fffff 266 267 268 /* Description RING_ID 269 270 The buffer pointer ring ID. 271 272 Helps with debugging when dumping ring contents. 273 <legal all> 274 */ 275 276 #define TCL_STATUS_RING_RING_ID_OFFSET 0x0000001c 277 #define TCL_STATUS_RING_RING_ID_LSB 20 278 #define TCL_STATUS_RING_RING_ID_MSB 27 279 #define TCL_STATUS_RING_RING_ID_MASK 0x0ff00000 280 281 282 /* Description LOOPING_COUNT 283 284 A count value that indicates the number of times the producer 285 of entries into the Ring has looped around the ring. 286 At initialization time, this value is set to 0. On the first 287 loop, this value is set to 1. After the max value is reached 288 allowed by the number of bits for this field, the count 289 value continues with 0 again. 290 291 In case SW is the consumer of the ring entries, it can use 292 this field to figure out up to where the producer of entries 293 has created new entries. This eliminates the need to check 294 where the "head pointer' of the ring is located once the 295 SW starts processing an interrupt indicating that new entries 296 have been put into this ring... 297 298 Also note that SW if it wants only needs to look at the 299 LSB bit of this count value. 300 <legal all> 301 */ 302 303 #define TCL_STATUS_RING_LOOPING_COUNT_OFFSET 0x0000001c 304 #define TCL_STATUS_RING_LOOPING_COUNT_LSB 28 305 #define TCL_STATUS_RING_LOOPING_COUNT_MSB 31 306 #define TCL_STATUS_RING_LOOPING_COUNT_MASK 0xf0000000 307 308 309 310 #endif // TCL_STATUS_RING 311