xref: /wlan-driver/fw-api/hw/qca5332/tx_fes_setup.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 
2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 
19 
20 
21 
22 
23 
24 
25 
26 #ifndef _TX_FES_SETUP_H_
27 #define _TX_FES_SETUP_H_
28 #if !defined(__ASSEMBLER__)
29 #endif
30 
31 #define NUM_OF_DWORDS_TX_FES_SETUP 10
32 
33 #define NUM_OF_QWORDS_TX_FES_SETUP 5
34 
35 
36 struct tx_fes_setup {
37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
38              uint32_t schedule_id                                             : 32; // [31:0]
39              uint32_t fes_in_11ax_trigger_response_config                     :  1, // [0:0]
40                       bo_based_tid_aggregation_limit                          :  4, // [4:1]
41                       ranging                                                 :  1, // [5:5]
42                       expect_i2r_lmr                                          :  1, // [6:6]
43                       transmit_start_reason                                   :  3, // [9:7]
44                       use_alt_power_sr                                        :  1, // [10:10]
45                       static_2_pwr_mode_status                                :  1, // [11:11]
46                       obss_srg_opport_transmit_status                         :  1, // [12:12]
47                       srp_based_transmit_status                               :  1, // [13:13]
48                       obss_pd_based_transmit_status                           :  1, // [14:14]
49                       puncture_from_all_allowed_modes                         :  1, // [15:15]
50                       schedule_cmd_ring_id                                    :  5, // [20:16]
51                       fes_control_mode                                        :  2, // [22:21]
52                       number_of_users                                         :  6, // [28:23]
53                       mu_type                                                 :  1, // [29:29]
54                       ofdma_triggered_response                                :  1, // [30:30]
55                       response_to_response_cmd                                :  1; // [31:31]
56              uint32_t schedule_try                                            :  4, // [3:0]
57                       ndp_frame                                               :  2, // [5:4]
58                       txbf                                                    :  1, // [6:6]
59                       allow_txop_exceed_in_1st_pkt                            :  1, // [7:7]
60                       ignore_bw_available                                     :  1, // [8:8]
61                       ignore_tbtt                                             :  1, // [9:9]
62                       static_bandwidth                                        :  3, // [12:10]
63                       set_txop_duration_all_ones                              :  1, // [13:13]
64                       transmission_contains_mu_rts                            :  1, // [14:14]
65                       bw_restricted_frames_embedded                           :  1, // [15:15]
66                       ast_index                                               : 16; // [31:16]
67              uint32_t cv_id                                                   :  8, // [7:0]
68                       trigger_resp_txpdu_ppdu_boundary                        :  2, // [9:8]
69                       rxpcu_setup_complete_present                            :  1, // [10:10]
70                       rbo_must_have_data_user_limit                           :  4, // [14:11]
71                       mu_ndp                                                  :  1, // [15:15]
72                       bf_type                                                 :  2, // [17:16]
73                       cbf_nc_index_mask                                       :  1, // [18:18]
74                       cbf_nc_index                                            :  3, // [21:19]
75                       cbf_nr_index_mask                                       :  1, // [22:22]
76                       cbf_nr_index                                            :  3, // [25:23]
77                       secure_ranging_ista                                     :  1, // [26:26]
78                       ndpa                                                    :  1, // [27:27]
79                       wait_sifs                                               :  2, // [29:28]
80                       cbf_feedback_type_mask                                  :  1, // [30:30]
81                       cbf_feedback_type                                       :  1; // [31:31]
82              uint32_t cbf_sounding_token                                      :  6, // [5:0]
83                       cbf_sounding_token_mask                                 :  1, // [6:6]
84                       cbf_bw_mask                                             :  1, // [7:7]
85                       cbf_bw                                                  :  3, // [10:8]
86                       use_static_bw                                           :  1, // [11:11]
87                       coex_nack_count                                         :  5, // [16:12]
88                       sch_tx_burst_ongoing                                    :  1, // [17:17]
89                       gen_tqm_update_mpdu_count_tlv                           :  1, // [18:18]
90                       transmit_vif                                            :  4, // [22:19]
91                       optimal_bw_retry_count                                  :  4, // [26:23]
92                       fes_continuation_ratio_threshold                        :  5; // [31:27]
93              uint32_t transmit_cca_bitmap                                     : 32; // [31:0]
94              uint32_t tb_ranging                                              :  1, // [0:0]
95                       ranging_trigger_subtype                                 :  4, // [4:1]
96                       min_cts2self_count                                      :  4, // [8:5]
97                       max_cts2self_count                                      :  4, // [12:9]
98                       wifi_radar_enable                                       :  1, // [13:13]
99                       reserved_6a                                             : 18; // [31:14]
100              uint32_t monitor_override_sta_31_0                               : 32; // [31:0]
101              uint32_t monitor_override_sta_36_32                              :  5, // [4:0]
102                       reserved_8a                                             : 27; // [31:5]
103              uint32_t fw2sw_info                                              : 32; // [31:0]
104 #else
105              uint32_t schedule_id                                             : 32; // [31:0]
106              uint32_t response_to_response_cmd                                :  1, // [31:31]
107                       ofdma_triggered_response                                :  1, // [30:30]
108                       mu_type                                                 :  1, // [29:29]
109                       number_of_users                                         :  6, // [28:23]
110                       fes_control_mode                                        :  2, // [22:21]
111                       schedule_cmd_ring_id                                    :  5, // [20:16]
112                       puncture_from_all_allowed_modes                         :  1, // [15:15]
113                       obss_pd_based_transmit_status                           :  1, // [14:14]
114                       srp_based_transmit_status                               :  1, // [13:13]
115                       obss_srg_opport_transmit_status                         :  1, // [12:12]
116                       static_2_pwr_mode_status                                :  1, // [11:11]
117                       use_alt_power_sr                                        :  1, // [10:10]
118                       transmit_start_reason                                   :  3, // [9:7]
119                       expect_i2r_lmr                                          :  1, // [6:6]
120                       ranging                                                 :  1, // [5:5]
121                       bo_based_tid_aggregation_limit                          :  4, // [4:1]
122                       fes_in_11ax_trigger_response_config                     :  1; // [0:0]
123              uint32_t ast_index                                               : 16, // [31:16]
124                       bw_restricted_frames_embedded                           :  1, // [15:15]
125                       transmission_contains_mu_rts                            :  1, // [14:14]
126                       set_txop_duration_all_ones                              :  1, // [13:13]
127                       static_bandwidth                                        :  3, // [12:10]
128                       ignore_tbtt                                             :  1, // [9:9]
129                       ignore_bw_available                                     :  1, // [8:8]
130                       allow_txop_exceed_in_1st_pkt                            :  1, // [7:7]
131                       txbf                                                    :  1, // [6:6]
132                       ndp_frame                                               :  2, // [5:4]
133                       schedule_try                                            :  4; // [3:0]
134              uint32_t cbf_feedback_type                                       :  1, // [31:31]
135                       cbf_feedback_type_mask                                  :  1, // [30:30]
136                       wait_sifs                                               :  2, // [29:28]
137                       ndpa                                                    :  1, // [27:27]
138                       secure_ranging_ista                                     :  1, // [26:26]
139                       cbf_nr_index                                            :  3, // [25:23]
140                       cbf_nr_index_mask                                       :  1, // [22:22]
141                       cbf_nc_index                                            :  3, // [21:19]
142                       cbf_nc_index_mask                                       :  1, // [18:18]
143                       bf_type                                                 :  2, // [17:16]
144                       mu_ndp                                                  :  1, // [15:15]
145                       rbo_must_have_data_user_limit                           :  4, // [14:11]
146                       rxpcu_setup_complete_present                            :  1, // [10:10]
147                       trigger_resp_txpdu_ppdu_boundary                        :  2, // [9:8]
148                       cv_id                                                   :  8; // [7:0]
149              uint32_t fes_continuation_ratio_threshold                        :  5, // [31:27]
150                       optimal_bw_retry_count                                  :  4, // [26:23]
151                       transmit_vif                                            :  4, // [22:19]
152                       gen_tqm_update_mpdu_count_tlv                           :  1, // [18:18]
153                       sch_tx_burst_ongoing                                    :  1, // [17:17]
154                       coex_nack_count                                         :  5, // [16:12]
155                       use_static_bw                                           :  1, // [11:11]
156                       cbf_bw                                                  :  3, // [10:8]
157                       cbf_bw_mask                                             :  1, // [7:7]
158                       cbf_sounding_token_mask                                 :  1, // [6:6]
159                       cbf_sounding_token                                      :  6; // [5:0]
160              uint32_t transmit_cca_bitmap                                     : 32; // [31:0]
161              uint32_t reserved_6a                                             : 18, // [31:14]
162                       wifi_radar_enable                                       :  1, // [13:13]
163                       max_cts2self_count                                      :  4, // [12:9]
164                       min_cts2self_count                                      :  4, // [8:5]
165                       ranging_trigger_subtype                                 :  4, // [4:1]
166                       tb_ranging                                              :  1; // [0:0]
167              uint32_t monitor_override_sta_31_0                               : 32; // [31:0]
168              uint32_t reserved_8a                                             : 27, // [31:5]
169                       monitor_override_sta_36_32                              :  5; // [4:0]
170              uint32_t fw2sw_info                                              : 32; // [31:0]
171 #endif
172 };
173 
174 
175 /* Description		SCHEDULE_ID
176 
177 			Consumer: PDG/TXDMA/TXOLE/TXCRYPTO/TXPCU
178 			Producer: SCH
179 
180 			This field is overwritten by the scheduler module and it's
181 			 value is coming from the"schedule_id" field in the  Scheduler
182 			 command.
183 
184 			Configured by scheduler in HW transmit mode
185 			A field that HW copies over into the scheduling status report,
186 			so that SW can determine to which scheduler command the
187 			status report belongs.
188 			This schedule ID is also reported in the PPDU status.
189 
190 			<legal all>
191 */
192 
193 #define TX_FES_SETUP_SCHEDULE_ID_OFFSET                                             0x0000000000000000
194 #define TX_FES_SETUP_SCHEDULE_ID_LSB                                                0
195 #define TX_FES_SETUP_SCHEDULE_ID_MSB                                                31
196 #define TX_FES_SETUP_SCHEDULE_ID_MASK                                               0x00000000ffffffff
197 
198 
199 /* Description		FES_IN_11AX_TRIGGER_RESPONSE_CONFIG
200 
201 			Consumer: PDG/TXPCU
202 			Producer: SW
203 			When set, this scheduler command has some additional settings
204 			 that PDG and TXPCU need to take into account, depending
205 			 on if the transmission has been iniated as a backoff expiration
206 			 or as the result of an 11ax trigger reception.
207 
208 			0: not in special trigger response config
209 			1: command is special trigger response config.
210 
211 			When set to 1, there are some programming limitations: There
212 			 can only be 1 group, up to 8 users, SW shall have specified
213 			 the AC for each user, and AC order per user is from BE
214 			to VO
215 			(see PDG_USER_SETUP, fields Triggered_mpdu_AC_category)
216 
217 			<legal all>
218 */
219 
220 #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET                     0x0000000000000000
221 #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB                        32
222 #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB                        32
223 #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK                       0x0000000100000000
224 
225 
226 /* Description		BO_BASED_TID_AGGREGATION_LIMIT
227 
228 			Consumer: PDG
229 			Producer: SW
230 
231 			Field only valid when Ofdma_triggered_response is NOT set
232 			 (=> implies transmission started due to backoff expiration)
233 
234 
235 			Field only valid for SU and "MU_SU" transmissions.
236 
237 			The requirements for what to transmit depend on what the
238 			 reason is that this transmission started. If it is 11ax
239 			 trigger based, the trigger frame will specify all the constrains
240 			 like max TID count, prefered AC, etc.
241 			However if this command starts executing due to backoff
242 			expiration, the requirements could be different from those
243 			 that might have come from the trigger frame.
244 			This field specifies what the constaints are when the transmission
245 			 is Backoff initiated.
246 
247 			If zero, this feature is disabled.
248 			If non-zero, this indicates the number of users within a
249 			 group that can be aggregated by a STA in a multi-TID A-MPDU.
250 			This can also be used to block the series of QoS-null MPDUs
251 			 when an RBO+Trig queue transmits using RBO.
252 
253 			Based on this number, PDG will mask of user numbers >= this
254 			 count
255 			<legal all>
256 */
257 
258 #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET                          0x0000000000000000
259 #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB                             33
260 #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB                             36
261 #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK                            0x0000001e00000000
262 
263 
264 /* Description		RANGING
265 
266 			Consumer: TXPCU
267 			Producer: SW
268 
269 			Set to 1 in case the frame queued is:
270 			a .11az ranging NDPA,
271 			a .11az ranging NDP, or
272 			an ISTA2RSTA LMR.
273 			Set to 0 for all other cases.
274 */
275 
276 #define TX_FES_SETUP_RANGING_OFFSET                                                 0x0000000000000000
277 #define TX_FES_SETUP_RANGING_LSB                                                    37
278 #define TX_FES_SETUP_RANGING_MSB                                                    37
279 #define TX_FES_SETUP_RANGING_MASK                                                   0x0000002000000000
280 
281 
282 /* Description		EXPECT_I2R_LMR
283 
284 			Consumer: TXPCU
285 			Producer: SW
286 
287 			Set to 1 in case the frame queued is  a .11az randing NDPA/NDP
288 			 and if the ISTA2RSTA LMR frame is also queued after SIFS.
289 
290 
291 			Set to 0 otherwise.
292 */
293 
294 #define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET                                          0x0000000000000000
295 #define TX_FES_SETUP_EXPECT_I2R_LMR_LSB                                             38
296 #define TX_FES_SETUP_EXPECT_I2R_LMR_MSB                                             38
297 #define TX_FES_SETUP_EXPECT_I2R_LMR_MASK                                            0x0000004000000000
298 
299 
300 /* Description		TRANSMIT_START_REASON
301 
302 			Indicates what the SCH start reason reason was for initiating
303 			 this transmission.
304 
305 			<enum 0 BO_based_transmit_start> The transmission of this
306 			 PPDU got initiated by the scheduler due to Backoff expiration
307 
308 			<enum 1 Trigger_based_transmit_start> The transmission of
309 			 this PPDU got initiated by the scheduler due to reception
310 			 (by the SCH) of the TLV RECEIVED_TRIGGER_INFO that RXPCU
311 			 generated. Note that this can be an OFDMA trigger frame
312 			 based transmission as well as some legacy trigger (PS-POLL,
313 			Qboost, U-APSD, etc.)  based transmission
314 			<enum 2 Sifs_continuation_in_ongoing_burst> This transmission
315 			 of this PPDU got initiated as part of SIFS continuation.
316 			An earlier PPDU was transmitted due to RBO expiration. Next
317 			 command is also expected to be transmitted in SIFS burst.
318 
319 			<enum 3 Sifs_continuation_last_command> This transmission
320 			 of this PPDU got initiated as part of SIFS continuation
321 			 and this is the last command in the burst. An earlier PPDU
322 			 was transmitted due to RBO expiration.
323 			<enum 4 NTBR_response_start> DO NOT USE
324 			<legal 0-4>
325 */
326 
327 #define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET                                   0x0000000000000000
328 #define TX_FES_SETUP_TRANSMIT_START_REASON_LSB                                      39
329 #define TX_FES_SETUP_TRANSMIT_START_REASON_MSB                                      41
330 #define TX_FES_SETUP_TRANSMIT_START_REASON_MASK                                     0x0000038000000000
331 
332 
333 /* Description		USE_ALT_POWER_SR
334 
335 			0: Primary/default power1: Alternate power
336 			<legal all>
337 */
338 
339 #define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET                                        0x0000000000000000
340 #define TX_FES_SETUP_USE_ALT_POWER_SR_LSB                                           42
341 #define TX_FES_SETUP_USE_ALT_POWER_SR_MSB                                           42
342 #define TX_FES_SETUP_USE_ALT_POWER_SR_MASK                                          0x0000040000000000
343 
344 
345 /* Description		STATIC_2_PWR_MODE_STATUS
346 
347 			0: Static 2 power mode disabled1: Static 2 power mode enabled
348 
349 			<legal all>
350 */
351 
352 #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET                                0x0000000000000000
353 #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB                                   43
354 #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB                                   43
355 #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK                                  0x0000080000000000
356 
357 
358 /* Description		OBSS_SRG_OPPORT_TRANSMIT_STATUS
359 
360 			0: Transmit based on SRG OBSS_PD opportunity initiated1:
361 			Transmit based on non-SRG OBSS_PD opportunity initiated
362 			<legal all>
363 */
364 
365 #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET                         0x0000000000000000
366 #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB                            44
367 #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB                            44
368 #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK                           0x0000100000000000
369 
370 
371 /* Description		SRP_BASED_TRANSMIT_STATUS
372 
373 			0: non-SRP based transmit initiated1: SRP based transmit
374 			 initiated
375 			<legal all>
376 */
377 
378 #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET                               0x0000000000000000
379 #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB                                  45
380 #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB                                  45
381 #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK                                 0x0000200000000000
382 
383 
384 /* Description		OBSS_PD_BASED_TRANSMIT_STATUS
385 
386 			0: non-OBSS_PD based transmit initiated1: obss_pd based
387 			transmit initiated
388 			<legal all>
389 */
390 
391 #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET                           0x0000000000000000
392 #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB                              46
393 #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB                              46
394 #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK                             0x0000400000000000
395 
396 
397 /* Description		PUNCTURE_FROM_ALL_ALLOWED_MODES
398 
399 			Enables new scheme 2 puncturing in Beryllium:
400 			TXPCU registers determine which puncture patterns (up to
401 			 37) are enabled for the transmission.
402 			'TX_PUNCTURE_SETUP' is unused.
403 			<legal all>
404 */
405 
406 #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET                         0x0000000000000000
407 #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB                            47
408 #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB                            47
409 #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK                           0x0000800000000000
410 
411 
412 /* Description		SCHEDULE_CMD_RING_ID
413 
414 			Consumer: PDG/TXDMA/TXOLE/TXCRYPTO/TXPCU
415 			Producer: SCH
416 
417 			This field is overwritten by the scheduler module and its
418 			 value is based on the scheduler ring where the command
419 			is initiated.
420 
421 			The schedule command ring  that originated this transmission
422 
423 			<enum 0 sch_cmd_ring_number0>
424 			<enum 1 sch_cmd_ring_number1>
425 			<enum 2 sch_cmd_ring_number2>
426 			<enum 3 sch_cmd_ring_number3>
427 			<enum 4 sch_cmd_ring_number4>
428 			<enum 5 sch_cmd_ring_number5>
429 			<enum 6 sch_cmd_ring_number6>
430 			<enum 7 sch_cmd_ring_number7>
431 			<enum 8 sch_cmd_ring_number8>
432 			<enum 9 sch_cmd_ring_number9>
433 			<enum 10 sch_cmd_ring_number10>
434 			<enum 11 sch_cmd_ring_number11>
435 			<enum 12 sch_cmd_ring_number12>
436 			<enum 13 sch_cmd_ring_number13>
437 			<enum 14 sch_cmd_ring_number14>
438 			<enum 15 sch_cmd_ring_number15>
439 			<enum 16 sch_cmd_ring_number16>
440 			<enum 17 sch_cmd_ring_number17>
441 			<enum 18 sch_cmd_ring_number18>
442 			<enum 19 sch_cmd_ring_number19>
443 			<enum 20 sch_cmd_ring_number20>
444 
445 			<legal 0-20>
446 */
447 
448 #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET                                    0x0000000000000000
449 #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB                                       48
450 #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB                                       52
451 #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK                                      0x001f000000000000
452 
453 
454 /* Description		FES_CONTROL_MODE
455 
456 			Consumer: PDG/TXDMA/TXOLE/TXCRYPTO/TXPCU
457 			Producer: SCH
458 
459 			This field is overwritten by the scheduler module and it's
460 			 value is coming from the "FES_control_mode" field in the
461 			  Scheduler command.
462 
463 			<enum 0  SW_transmit_mode>  No HW generated TLVs
464 			<enum 1 PDG_transmit_mode> PDG  is activated to generate
465 			 TLVs
466 
467 			Note: Final Bandwidth selection is always performed by TX
468 			 PCU.
469 			<legal 0-1>
470 */
471 
472 #define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET                                        0x0000000000000000
473 #define TX_FES_SETUP_FES_CONTROL_MODE_LSB                                           53
474 #define TX_FES_SETUP_FES_CONTROL_MODE_MSB                                           54
475 #define TX_FES_SETUP_FES_CONTROL_MODE_MASK                                          0x0060000000000000
476 
477 
478 /* Description		NUMBER_OF_USERS
479 
480 			Consumer: PDG/TXDMA/TXOLE/TXCRYPTO/TXPCU
481 			Producer: SCH
482 
483 			The number of users in this transmission. Can be MU-MIMO
484 			 or OFDMA in case the number is > 1
485 			<legal 1-63>
486 */
487 
488 #define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET                                         0x0000000000000000
489 #define TX_FES_SETUP_NUMBER_OF_USERS_LSB                                            55
490 #define TX_FES_SETUP_NUMBER_OF_USERS_MSB                                            60
491 #define TX_FES_SETUP_NUMBER_OF_USERS_MASK                                           0x1f80000000000000
492 
493 
494 /* Description		MU_TYPE
495 
496 			In case the Number_of_users > 1, the transmission could
497 			be MU or OFDMA.
498 			This field indicates which one it is.
499 
500 			0: MU-MIMO
501 			1: OFDMA
502 
503 
504 			In case the number_of_user == 1, and PDG_FES_SETUP.mu_su_transmission
505 			 is set, this field indicates:0: SU transmitted in MU MIMO
506 			 format in compressed mode;1: SU transmitted in MU-OFDMA
507 			 format in uncompressed mode
508 
509 			Note: Within OFDMA classification, it could be that within
510 			 one or more RUs there will be MIMO transmission...This
511 			is still considered as an 'OFDMA' class of MU transmission.
512 
513 
514 			<legal all>
515 */
516 
517 #define TX_FES_SETUP_MU_TYPE_OFFSET                                                 0x0000000000000000
518 #define TX_FES_SETUP_MU_TYPE_LSB                                                    61
519 #define TX_FES_SETUP_MU_TYPE_MSB                                                    61
520 #define TX_FES_SETUP_MU_TYPE_MASK                                                   0x2000000000000000
521 
522 
523 /* Description		OFDMA_TRIGGERED_RESPONSE
524 
525 			Consumer: TXPCU/PDG
526 			Producer: SCH/SW
527 
528 			SW should always set this bit to 0
529 			SCH will always overwrite this field and set it to the appropriate
530 			 value for the upcoming transmission.
531 
532 			When set (by SCH), this FES is initiated as a result of
533 			receiving an OFDMA transmit trigger. PDG already has received
534 			 all transmit info from RXPCU. PDG can ignore most of the
535 			 transmit initialization info.
536 
537 			<legal all>
538 */
539 
540 #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET                                0x0000000000000000
541 #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB                                   62
542 #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB                                   62
543 #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK                                  0x4000000000000000
544 
545 
546 /* Description		RESPONSE_TO_RESPONSE_CMD
547 
548 			When set, this scheduler command contains the transmission
549 			 control for the response_to_response transmission
550 			<legal all>
551 */
552 
553 #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET                                0x0000000000000000
554 #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB                                   63
555 #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB                                   63
556 #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK                                  0x8000000000000000
557 
558 
559 /* Description		SCHEDULE_TRY
560 
561 			Consumer: TXPCU
562 			Producer: SCH
563 
564 			This field is overwritten by the scheduler module and it's
565 			 value is coming from an internal counter in the scheduler
566 			 that keeps track of how many times a scheduling command
567 			 has been tried.
568 
569 			This count indicates how many times the FES did not successfully
570 			 complete as the ACK/BA frame did not get received.
571 			<legal all>
572 */
573 
574 #define TX_FES_SETUP_SCHEDULE_TRY_OFFSET                                            0x0000000000000008
575 #define TX_FES_SETUP_SCHEDULE_TRY_LSB                                               0
576 #define TX_FES_SETUP_SCHEDULE_TRY_MSB                                               3
577 #define TX_FES_SETUP_SCHEDULE_TRY_MASK                                              0x000000000000000f
578 
579 
580 /* Description		NDP_FRAME
581 
582 			Consumer: PDG/TXPCU
583 			Producer: SCH
584 
585 			When set, the scheduling command contains an NDP frame.
586 			This can only be done using the SW transmit mode.
587 
588 			<enum 0 no_ndp>No NDP transmission
589 			<enum 1 beamforming_ndp>Beamforming NDP
590 			<enum 2 he_ranging_ndp>11az NDP (HE Ranging NDP)
591 			<enum 3 he_feedback_ndp>Short TB (HE Feedback NDP)
592 */
593 
594 #define TX_FES_SETUP_NDP_FRAME_OFFSET                                               0x0000000000000008
595 #define TX_FES_SETUP_NDP_FRAME_LSB                                                  4
596 #define TX_FES_SETUP_NDP_FRAME_MSB                                                  5
597 #define TX_FES_SETUP_NDP_FRAME_MASK                                                 0x0000000000000030
598 
599 
600 /* Description		TXBF
601 
602 			Consumer: PDG/TXPCU
603 			Producer: SCH
604 
605 			If set, this bit indicates that this is a TX beamformed
606 			SU transaction or MU transaction
607 
608 
609 			In case of a beamformed transmission, note that in the PCU_PPDU_SETUP_INIT
610 			 TLV, SW can narrow down for which of the BW the beamforming
611 			 shall take place. For example, SW can decide that BW is
612 			 only desired for 40MHz BW, but not for 20...
613 			If for any of the allowed BW, beamforming is desired, this
614 			 field should be set, and the 'bf_type' shall be properly
615 			 programmed.
616 
617 			TXPCU controls with bit 'beamforming' in the MACTX_PRE_PHY_DESC
618 			 if the final actual transmission shall be beamformed.
619 */
620 
621 #define TX_FES_SETUP_TXBF_OFFSET                                                    0x0000000000000008
622 #define TX_FES_SETUP_TXBF_LSB                                                       6
623 #define TX_FES_SETUP_TXBF_MSB                                                       6
624 #define TX_FES_SETUP_TXBF_MASK                                                      0x0000000000000040
625 
626 
627 /* Description		ALLOW_TXOP_EXCEED_IN_1ST_PKT
628 
629 			Consumer: PDG
630 			Producer: SCH
631 
632 			Field only valid for SU transmissions.
633 
634 			When set, a single MPDU transmission after RBO is allowed
635 			 to exceed TXOP. In this setting, this field has priority
636 			 over the setting of the duration_field_boundary. Reason
637 			 for this is that if Coex issues on the receiver STA start
638 			 preventing the transmission of frames on this device, it
639 			 can lead to a death spiral. With some luck, this frame
640 			although maybe too long, might still be received.
641 
642 			When 0, single MPDU after RBO is not allowed to exceed TXOP.
643 
644 			<legal all>
645 */
646 
647 #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET                            0x0000000000000008
648 #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB                               7
649 #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB                               7
650 #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK                              0x0000000000000080
651 
652 
653 /* Description		IGNORE_BW_AVAILABLE
654 
655 			Consumer: TXPCU
656 			Producer: SCH
657 
658 			If set, TXPCU ignores 'BW available signals' from the scheduler
659 			 and transmit using the single BW that SW has programmed
660 			 the transmission to go out in. This bit should be set for
661 			 SIFS response frame to PS-Poll/uAPSD/QBoost and note that
662 			 for this mode, SW is only allowed to program a single transmit
663 			 BW.
664 			Also note that this bit can not be set in combination with
665 			 preamble puncturing.
666 			<legal all>
667 */
668 
669 #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET                                     0x0000000000000008
670 #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB                                        8
671 #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB                                        8
672 #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK                                       0x0000000000000100
673 
674 
675 /* Description		IGNORE_TBTT
676 
677 			Consumer: PDG
678 			Producer: SCH
679 
680 			If set, PDG ignores remaining TBTTs in PPDU time calculation.
681 
682 			<legal all>
683 */
684 
685 #define TX_FES_SETUP_IGNORE_TBTT_OFFSET                                             0x0000000000000008
686 #define TX_FES_SETUP_IGNORE_TBTT_LSB                                                9
687 #define TX_FES_SETUP_IGNORE_TBTT_MSB                                                9
688 #define TX_FES_SETUP_IGNORE_TBTT_MASK                                               0x0000000000000200
689 
690 
691 /* Description		STATIC_BANDWIDTH
692 
693 			Consumer: PDG/TXPCU
694 			Producer: SCH
695 
696 			Field is reserved when use_static_bw is clear.
697 
698 			<enum 0 20_mhz>20 Mhz BW
699 			<enum 1 40_mhz>40 Mhz BW
700 			<enum 2 80_mhz>80 Mhz BW
701 			<enum 3 160_mhz>160 Mhz BW
702 			<enum 4 320_mhz>320 Mhz BW
703 			<enum 5 240_mhz>240 Mhz BW
704 */
705 
706 #define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET                                        0x0000000000000008
707 #define TX_FES_SETUP_STATIC_BANDWIDTH_LSB                                           10
708 #define TX_FES_SETUP_STATIC_BANDWIDTH_MSB                                           12
709 #define TX_FES_SETUP_STATIC_BANDWIDTH_MASK                                          0x0000000000001c00
710 
711 
712 /* Description		SET_TXOP_DURATION_ALL_ONES
713 
714 			Consumer: PDG
715 			Producer: SCH
716 
717 			When set, SW embedded a PS_POLL frame in this transmission
718 			 or the frame in this transmission is for a BSS with BSS
719 			 Color disabled, e.g. due to BSS color collision.
720 			PDG sets the TXOP_DURATION of the transmit PPDU to all 1s.
721 
722 			<legal all>
723 */
724 
725 #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET                              0x0000000000000008
726 #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB                                 13
727 #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB                                 13
728 #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK                                0x0000000000002000
729 
730 
731 /* Description		TRANSMISSION_CONTAINS_MU_RTS
732 
733 			Consumer: PDG
734 			Producer: SCH
735 
736 			When set, SW embedded a MU-RTS trigger frame in this transmission.
737 
738 			TXPCU will have to do something special for this with the
739 			 CTS response timeout (whose value comes from a MU-CTS timeout
740 			 register)
741 
742 			<legal all>
743 */
744 
745 #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET                            0x0000000000000008
746 #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB                               14
747 #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB                               14
748 #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK                              0x0000000000004000
749 
750 
751 /* Description		BW_RESTRICTED_FRAMES_EMBEDDED
752 
753 			Consumer: TXPCU
754 			Producer: SW
755 
756 			This bit should be set by SW when the transmission includes
757 			 bandwidth restricted frames. As a result of this bit being
758 			 set, TXPCU will hold of indicating that buffer space is
759 			 available to TXDMA till the BW decision is done. This allows
760 			 TXPCU to drop the BW restricted frames at SFM input.
761 
762 			<legal all>
763 */
764 
765 #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET                           0x0000000000000008
766 #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB                              15
767 #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB                              15
768 #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK                             0x0000000000008000
769 
770 
771 /* Description		AST_INDEX
772 
773 			Consumer: RXPCU
774 			Producer: SCH
775 
776 			Used for implicit BF sounding capture on receive Ack/BA.
777 			 The RXPCU needs to tag the receive sounding with ast_index
778 			 so FW will know which STA is associated with Ack/BA sounding.
779 
780 
781 			<legal all>
782 */
783 
784 #define TX_FES_SETUP_AST_INDEX_OFFSET                                               0x0000000000000008
785 #define TX_FES_SETUP_AST_INDEX_LSB                                                  16
786 #define TX_FES_SETUP_AST_INDEX_MSB                                                  31
787 #define TX_FES_SETUP_AST_INDEX_MASK                                                 0x00000000ffff0000
788 
789 
790 /* Description		CV_ID
791 
792 			Consumer: TXPCU
793 			Producer: SCH
794 
795 			This field is only valid when expect_cbf is set.
796 
797 			A unique ID corresponding to the CV data expected from the
798 			 CBF frame.
799 
800 			TXPCU copies this field over to the TX_FES_STATUS TLV
801 			<legal all>
802 */
803 
804 #define TX_FES_SETUP_CV_ID_OFFSET                                                   0x0000000000000008
805 #define TX_FES_SETUP_CV_ID_LSB                                                      32
806 #define TX_FES_SETUP_CV_ID_MSB                                                      39
807 #define TX_FES_SETUP_CV_ID_MASK                                                     0x000000ff00000000
808 
809 
810 /* Description		TRIGGER_RESP_TXPDU_PPDU_BOUNDARY
811 
812 			This field indicates to TXPCU how far into the 11ax trigger
813 			 response transmission, TXPCU should still accept Trigger
814 			 response related configuration info from the SCHEDULER (and
815 			 PDG) to be processed.
816 
817 			The field indicates a percentage of the total  byte count
818 			 to be given to the PHY, up to which point TXPCU will still
819 			 accept all the setup related TLVS to arrive. After that,
820 			TXPCU will ignore any remaining setup TLVs to come in and
821 			 not initiate any MPDU based transfers to the PHY anymore.
822 			This is to help avoid corner cases.
823 			If any setup TLVs did arrive after this point, TXPCU will
824 			 keep on continuing giving NULL data to the PHY, but once
825 			 PHYTX_PKT_END is received, TXPCU shall issue a FLUSH request
826 			 to the SCH, with flush code: TXPCU_TRIG_RESPONSE_INFO_TOO_LATE
827 
828 			TXPCU should not abort the transmission halfway, as that
829 			 can cause problems for the MU UL receiver...
830 
831 			<enum 0 txpcu_trig_response_boundary_75> TXPCU will not
832 			initiate SCH based MPDU transfers after 75% of the PPDU
833 			octed count has already been given to the PHY.
834 
835 			<enum 1 txpcu_trig_response_boundary_50> TXPCU will not
836 			initiate SCH based MPDU transfers after 50% of the PPDU
837 			octed count has already been given to the PHY.
838 
839 			<enum 2 txpcu_trig_response_boundary_25> TXPCU will not
840 			initiate SCH based MPDU transfers after 75% of the PPDU
841 			octed count has already been given to the PHY.
842 
843 			Note that if TXPCU receives a TX_FES_SETUP with "11ax trigger
844 			 response transmission" set, and it had already finished
845 			 sending a response , it should generate a flush with code:
846 			TXPCU_TRIG_RESPONSE_MODE_CORRUPTION
847 
848 			<legal 0-2>
849 */
850 
851 #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET                        0x0000000000000008
852 #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB                           40
853 #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB                           41
854 #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK                          0x0000030000000000
855 
856 
857 /* Description		RXPCU_SETUP_COMPLETE_PRESENT
858 
859 			To notify current TXFES use new mode and delay "RXPCU_*_SETUP"
860 			for HWSCH/TXPCU/RXPCU module
861 			<legal all>
862 */
863 
864 #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET                            0x0000000000000008
865 #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB                               42
866 #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB                               42
867 #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK                              0x0000040000000000
868 
869 
870 /* Description		RBO_MUST_HAVE_DATA_USER_LIMIT
871 
872 			Consumer: PDG
873 			Producer: SW
874 
875 			Field only valid when Ofdma_triggered_response is NOT set
876 			 (=> implies transmission started due to backoff expiration)
877 
878 
879 			Field only valid for SU and "MU_SU" transmissions.
880 
881 			The requirements for what to transmit depend on what the
882 			 reason is that this transmission started. If it is 11ax
883 			 trigger based, the trigger frame will specify all the constrains
884 			 like max TID count, prefered AC, etc.
885 			However if this command starts executing due to backoff
886 			expiration, the requirements could be different from those
887 			 that might have come from the trigger frame.
888 			This field specifies what the constaints are when the transmission
889 			 is Backoff initiated.
890 
891 			When set to 0, this feature is disabled
892 			When set to 1, user 0 must have data otherwise PDG should
893 			 flush the transmission
894 			When set to 2, user 0 AND/OR user 1 must have data otherwise
895 			 PDG should flush the transmission
896 			When set to 3, user 0 AND/OR user 1 AND/OR user 2 must have
897 			 data otherwise PDG should flush the transmission
898 			...
899 			<legal all>
900 */
901 
902 #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET                           0x0000000000000008
903 #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB                              43
904 #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB                              46
905 #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK                             0x0000780000000000
906 
907 
908 /* Description		MU_NDP
909 
910 			Field only valid when ndp_frame is set.
911 
912 			If set indicates that this packet is an NDP used for MU
913 			channel estimation.  This bit will be used by the TPC to
914 			 signal that the analog gain settings can be updated. The
915 			 analog gain settings will not change for subsequent MU
916 			data packets.
917 			<legal all>
918 */
919 
920 #define TX_FES_SETUP_MU_NDP_OFFSET                                                  0x0000000000000008
921 #define TX_FES_SETUP_MU_NDP_LSB                                                     47
922 #define TX_FES_SETUP_MU_NDP_MSB                                                     47
923 #define TX_FES_SETUP_MU_NDP_MASK                                                    0x0000800000000000
924 
925 
926 /* Description		BF_TYPE
927 
928 			Consumer: PDG/TXPCU
929 			Producer: SCH
930 
931 			Field is ONLY valid when 'txbf' is set...
932 
933 			Defines the type of beamforming that is required using this
934 			 transmission.
935 			Note that in the PCU_PPDU_SETUP_INIT TLV, SW can narrow
936 			down for which BW the beamforming shall take place. For
937 			example, SW can decide that BW is only desired for 40MHz
938 			 BW, but not for 20...
939 			If for any of the allowed BW, beamforming is desired, this
940 			 field should indicate which type of BF.
941 
942 			<enum 0    NO_BF>
943 			<enum 1    LEGACY_BF>
944 			<enum 2    SU_BF>
945 			<enum 3    MU_BF>
946 			 <legal all>
947 */
948 
949 #define TX_FES_SETUP_BF_TYPE_OFFSET                                                 0x0000000000000008
950 #define TX_FES_SETUP_BF_TYPE_LSB                                                    48
951 #define TX_FES_SETUP_BF_TYPE_MSB                                                    49
952 #define TX_FES_SETUP_BF_TYPE_MASK                                                   0x0003000000000000
953 
954 
955 /* Description		CBF_NC_INDEX_MASK
956 
957 			Consumer: TXPCU
958 			Producer: SCH
959 
960 			When set, TXPCU shall confirm that the received cbf_nc_index
961 			 is equal to the expected one, indicated by field: cbf_nc_index
962 
963 
964 			This field is only allowed to be set in case of a single
965 			 SU CBF reception.
966 
967 			<legal all>
968 */
969 
970 #define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET                                       0x0000000000000008
971 #define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB                                          50
972 #define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB                                          50
973 #define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK                                         0x0004000000000000
974 
975 
976 /* Description		CBF_NC_INDEX
977 
978 			Consumer: TXPCU
979 			Producer: SCH
980 
981 			Field only valid when cbf_nc_index_mask is set
982 
983 			Expected Nc_index of received CBF frame after sending NDP
984 			 or BR-Poll.
985 
986 			<enum 0 nc_1>
987 			<enum 1 nc_2>
988 			<enum 2 nc_3>
989 			<enum 3 nc_4>
990 			<enum 4 nc_5>
991 			<enum 5 nc_6>
992 			<enum 6 nc_7>
993 			<enum 7 nc_8>
994 			<legal 0-7>
995 */
996 
997 #define TX_FES_SETUP_CBF_NC_INDEX_OFFSET                                            0x0000000000000008
998 #define TX_FES_SETUP_CBF_NC_INDEX_LSB                                               51
999 #define TX_FES_SETUP_CBF_NC_INDEX_MSB                                               53
1000 #define TX_FES_SETUP_CBF_NC_INDEX_MASK                                              0x0038000000000000
1001 
1002 
1003 /* Description		CBF_NR_INDEX_MASK
1004 
1005 			Consumer: TXPCU
1006 			Producer: SCH
1007 
1008 			When set, TXPCU shall confirm that the received cbf_nr_index
1009 			 is equal to the expected one, indicated in the field: cbf_nr_index
1010 
1011 
1012 			This field is only allowed to be set in case of a single
1013 			 SU CBF reception.
1014 			<legal all>
1015 */
1016 
1017 #define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET                                       0x0000000000000008
1018 #define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB                                          54
1019 #define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB                                          54
1020 #define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK                                         0x0040000000000000
1021 
1022 
1023 /* Description		CBF_NR_INDEX
1024 
1025 			Expected Nr_index of received CBF frame after sending NDP
1026 			 or BR-Poll. This field is compared only if cbf_nr_index_mask
1027 			 is set to 1.
1028 			<enum 0 nr_1>
1029 			<enum 1 nr_2>
1030 			<enum 2 nr_3>
1031 			<enum 3 nr_4>
1032 			<enum 4 nr_5>
1033 			<enum 5 nr_6>
1034 			<enum 6 nr_7>
1035 			<enum 7 nr_8>
1036 			<legal 0-7>
1037 */
1038 
1039 #define TX_FES_SETUP_CBF_NR_INDEX_OFFSET                                            0x0000000000000008
1040 #define TX_FES_SETUP_CBF_NR_INDEX_LSB                                               55
1041 #define TX_FES_SETUP_CBF_NR_INDEX_MSB                                               57
1042 #define TX_FES_SETUP_CBF_NR_INDEX_MASK                                              0x0380000000000000
1043 
1044 
1045 /* Description		SECURE_RANGING_ISTA
1046 
1047 			Consumer: Crypto
1048 			Producer: SW
1049 
1050 			If set to 1, Crypto will use the 'TX_PEER_ENTRY' for encryption
1051 			 but not for the 'TX_DATA' from TXOLE interface but will
1052 			 wait for 'LMR_{MPDU_START, DATA, MPDU_END}' TLVs from TXPCU
1053 			 to encrypt the ISTA2RSTA LMR.
1054 
1055 			If set to 0, Crypto will encrypt 'TX_DATA' as for any non-.11az-ranging
1056 			 frame.
1057 */
1058 
1059 #define TX_FES_SETUP_SECURE_RANGING_ISTA_OFFSET                                     0x0000000000000008
1060 #define TX_FES_SETUP_SECURE_RANGING_ISTA_LSB                                        58
1061 #define TX_FES_SETUP_SECURE_RANGING_ISTA_MSB                                        58
1062 #define TX_FES_SETUP_SECURE_RANGING_ISTA_MASK                                       0x0400000000000000
1063 
1064 
1065 /* Description		NDPA
1066 
1067 			When set, this packet is an NDP announcement.
1068 */
1069 
1070 #define TX_FES_SETUP_NDPA_OFFSET                                                    0x0000000000000008
1071 #define TX_FES_SETUP_NDPA_LSB                                                       59
1072 #define TX_FES_SETUP_NDPA_MSB                                                       59
1073 #define TX_FES_SETUP_NDPA_MASK                                                      0x0800000000000000
1074 
1075 
1076 /* Description		WAIT_SIFS
1077 
1078 			Consumer: TXPCU
1079 			Producer: SCH
1080 
1081 			This field is passed over to the tx_phy_desc by the PDG
1082 			module. If set, the AMPI will hold this tx_phy_desc TLV
1083 			from the TX PCU until SIFS has elapsed and then forward
1084 			the tx_phy_desc to the PHY.  The PHY should ignore this
1085 			bit.  This bit is used to make sure that transmit SIFS response
1086 			 to a receive frame is cycle accurate and consistent to
1087 			enable accurate RTT measurement.
1088 
1089 			<enum 0 NO_SIFS_TIMING> Transmission shall start with the
1090 			 normal delay in PHY after receiving this notification
1091 			<enum 1 SIFS_TIMING_DESIRED> Transmission shall be made
1092 			at the SIFS boundary. If shall never start before SIFS boundary,
1093 			but if it a little later, it is not ideal and should be
1094 			flagged, but transmission shall not be aborted.
1095 			<enum 2 SIFS_TIMING_MANDATED> Transmission shall be made
1096 			 at exactly SIFS boundary. If this notification is received
1097 			 by the PHY after SIFS boundary already passed, the PHY
1098 			shall abort the transmission
1099 			<legal 0-2>
1100 */
1101 
1102 #define TX_FES_SETUP_WAIT_SIFS_OFFSET                                               0x0000000000000008
1103 #define TX_FES_SETUP_WAIT_SIFS_LSB                                                  60
1104 #define TX_FES_SETUP_WAIT_SIFS_MSB                                                  61
1105 #define TX_FES_SETUP_WAIT_SIFS_MASK                                                 0x3000000000000000
1106 
1107 
1108 /* Description		CBF_FEEDBACK_TYPE_MASK
1109 
1110 			Consumer: TXPCU
1111 			Producer: SCH
1112 
1113 			When set, TXPCU shall confirm that the cbf_feedback_type
1114 			 is equal to the expected one, indicated in the field: cbf_feedback_type
1115 
1116 
1117 			This field is only allowed to be set in case of a single
1118 			 SU CBF reception.
1119 			<legal all>
1120 */
1121 
1122 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET                                  0x0000000000000008
1123 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB                                     62
1124 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB                                     62
1125 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK                                    0x4000000000000000
1126 
1127 
1128 /* Description		CBF_FEEDBACK_TYPE
1129 
1130 			Consumer: TXPCU
1131 			Producer: SCH
1132 
1133 			Expected feedback type of received CBF frame after sending
1134 			 NDP or BR-Poll. This field is compared only if cbf_feedback_type_mask
1135 			 is set to 1.
1136 			<enum 0     SU>
1137 			<enum 1     MU>
1138 			<legal all>
1139 */
1140 
1141 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET                                       0x0000000000000008
1142 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB                                          63
1143 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB                                          63
1144 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK                                         0x8000000000000000
1145 
1146 
1147 /* Description		CBF_SOUNDING_TOKEN
1148 
1149 			Consumer: TXPCU
1150 			Producer: SCH
1151 
1152 			Expected sounding token of received CBF frame after sending
1153 			 NDP or BR-Poll. This field is compared only if cbf_sounding_token_mask
1154 			 is set to 1.
1155 			<legal all>
1156 */
1157 
1158 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET                                      0x0000000000000010
1159 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB                                         0
1160 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB                                         5
1161 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK                                        0x000000000000003f
1162 
1163 
1164 /* Description		CBF_SOUNDING_TOKEN_MASK
1165 
1166 			Consumer: TXPCU
1167 			Producer: SCH
1168 
1169 			When set, TXPCU shall confirm that the cbf_sounding_token
1170 			 is equal to the expected one, indicated in the field: cbf_sounding_token
1171 
1172 
1173 			This field is only allowed to be set in case of a single
1174 			 SU CBF reception.
1175 			<legal all>
1176 */
1177 
1178 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET                                 0x0000000000000010
1179 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB                                    6
1180 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB                                    6
1181 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK                                   0x0000000000000040
1182 
1183 
1184 /* Description		CBF_BW_MASK
1185 
1186 			Consumer: TXPCU
1187 			Producer: SCH
1188 
1189 			When set, TXPCU shall confirm that the cbf_bw_mask is equal
1190 			 to the expected one, indicated in the field: cbf_bw
1191 
1192 			This field is only allowed to be set in case of a single
1193 			 SU CBF reception.
1194 			<legal all>
1195 */
1196 
1197 #define TX_FES_SETUP_CBF_BW_MASK_OFFSET                                             0x0000000000000010
1198 #define TX_FES_SETUP_CBF_BW_MASK_LSB                                                7
1199 #define TX_FES_SETUP_CBF_BW_MASK_MSB                                                7
1200 #define TX_FES_SETUP_CBF_BW_MASK_MASK                                               0x0000000000000080
1201 
1202 
1203 /* Description		CBF_BW
1204 
1205 			Consumer: TXPCU
1206 			Producer: SCH
1207 
1208 			Expected channel width of received CBF frame after sending
1209 			 NDP or BR-Poll. This field is compared only if cbf_bw_mask
1210 			 is set to 1.
1211 
1212 			<enum 0 20_mhz>20 Mhz BW
1213 			<enum 1 40_mhz>40 Mhz BW
1214 			<enum 2 80_mhz>80 Mhz BW
1215 			<enum 3 160_mhz>160 Mhz BW
1216 			<enum 4 320_mhz>320 Mhz BW
1217 			<enum 5 240_mhz>240 Mhz BW
1218 */
1219 
1220 #define TX_FES_SETUP_CBF_BW_OFFSET                                                  0x0000000000000010
1221 #define TX_FES_SETUP_CBF_BW_LSB                                                     8
1222 #define TX_FES_SETUP_CBF_BW_MSB                                                     10
1223 #define TX_FES_SETUP_CBF_BW_MASK                                                    0x0000000000000700
1224 
1225 
1226 /* Description		USE_STATIC_BW
1227 
1228 			Consumer: TXPCU
1229 			Producer: SCH
1230 
1231 			Part of TX_BF_PARAMS: This field is used to indicate to
1232 			the SVD that the b/w that will be defined in the TX_PHY_DESC
1233 			 for the upcoming TXBF packet will be the same as the static
1234 			 bandwidth, i.e. the bandwidth that was in operation during
1235 			 sounding for the clients in question
1236 			<legal all>
1237 */
1238 
1239 #define TX_FES_SETUP_USE_STATIC_BW_OFFSET                                           0x0000000000000010
1240 #define TX_FES_SETUP_USE_STATIC_BW_LSB                                              11
1241 #define TX_FES_SETUP_USE_STATIC_BW_MSB                                              11
1242 #define TX_FES_SETUP_USE_STATIC_BW_MASK                                             0x0000000000000800
1243 
1244 
1245 /* Description		COEX_NACK_COUNT
1246 
1247 			Consumer: TXPCU
1248 			Producer: SCH
1249 
1250 			The number of times PDG informed the SCHeduler module that
1251 			 for this scheduling command, the WLAN transmission can
1252 			not be initialized due to getting a NACK response from the
1253 			 Coex engine, or PDG not being able to fit a transmission
1254 			 within the timing constraints given by Coex.
1255 
1256 			Note that SCH will (re)set this count to 0 at the start
1257 			of reading a new SCH command.
1258 			This count is maintained on a per ring basis by the SCHeduler
1259 
1260 
1261 			<legal all>
1262 */
1263 
1264 #define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET                                         0x0000000000000010
1265 #define TX_FES_SETUP_COEX_NACK_COUNT_LSB                                            12
1266 #define TX_FES_SETUP_COEX_NACK_COUNT_MSB                                            16
1267 #define TX_FES_SETUP_COEX_NACK_COUNT_MASK                                           0x000000000001f000
1268 
1269 
1270 /* Description		SCH_TX_BURST_ONGOING
1271 
1272 			Consumer: PDG/TXPCU
1273 			Producer: SCH
1274 
1275 			This field is overwritten by the scheduler module and it's
1276 			 value is coming from the" sifs_burst_continuation" field
1277 			 in the  Scheduler command.
1278 
1279 			0: No action
1280 			1: The next scheduling command needs to start at SIFS time
1281 			 after finishing the frame transmissions in this command.
1282 			This allows for SIFS based bursting
1283 			<legal all>
1284 */
1285 
1286 #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET                                    0x0000000000000010
1287 #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB                                       17
1288 #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB                                       17
1289 #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK                                      0x0000000000020000
1290 
1291 
1292 /* Description		GEN_TQM_UPDATE_MPDU_COUNT_TLV
1293 
1294 			Consumer: TXPCU
1295 			Producer: SW
1296 
1297 			NOTE: When PDG is configured to do transmissions in SW mode,
1298 			this bit shall NEVER be set.
1299 
1300 			When set, TXPCU shall generate the TQM_UPDATE_TX_MPDU_COUNT
1301 			 TLV immediately after PPDU transmission has finished (and
1302 			 before any response frame might have been received)
1303 
1304 			When set, SW shall also generate the RXPCU_USER_SETUP TLVs
1305 			 as this is where TXPCU will get the MPDU_queue addresses.
1306 
1307 			<legal all>
1308 */
1309 
1310 #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET                           0x0000000000000010
1311 #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB                              18
1312 #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB                              18
1313 #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK                             0x0000000000040000
1314 
1315 
1316 /* Description		TRANSMIT_VIF
1317 
1318 			Consumer: TXOLE
1319 			Producer: SW
1320 
1321 			The VIF for this transmission. Used in MCC mode to control/overwrite
1322 			 the PM bit settings. Based on this VIF value, TXOLE gets
1323 			 the pm bit control instructions from the pm_state_overwrite_per_vif
1324 			 register
1325 
1326 			<legal all>
1327 */
1328 
1329 #define TX_FES_SETUP_TRANSMIT_VIF_OFFSET                                            0x0000000000000010
1330 #define TX_FES_SETUP_TRANSMIT_VIF_LSB                                               19
1331 #define TX_FES_SETUP_TRANSMIT_VIF_MSB                                               22
1332 #define TX_FES_SETUP_TRANSMIT_VIF_MASK                                              0x0000000000780000
1333 
1334 
1335 /* Description		OPTIMAL_BW_RETRY_COUNT
1336 
1337 			Consumer: TXPCU
1338 			Producer: SCH
1339 
1340 			This field is overwritten by the scheduler module and it's
1341 			 value is coming from an internal counter in the scheduler
1342 			 that keeps track of how many times this scheduling command
1343 			 has been flushed by TXPCU as a result of most desired BW
1344 			 not being available (=> flush code: TXPCU_FLREQ_RETRY_FOR_OPTIMAL_BW)
1345 
1346 
1347 			For the first transmission, this count is always set to
1348 			0.
1349 			<legal all>
1350 */
1351 
1352 #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET                                  0x0000000000000010
1353 #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB                                     23
1354 #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB                                     26
1355 #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK                                    0x0000000007800000
1356 
1357 
1358 /* Description		FES_CONTINUATION_RATIO_THRESHOLD
1359 
1360 			Field evaluated by TXPCU only.
1361 
1362 			This Feature is not supported in Napier and Hastings.
1363 
1364 			Field can be used in both SU and MU transmissions, but might
1365 			 be most useful in MU transmissions.
1366 
1367 			TXPCU keeps track of how many MPDU data words are transmited
1368 			 as well as how many Null delimiters are transmitted. In
1369 			 case of an MU and/or multi TID transmission, these two
1370 			counters are the aggregates over all the users.
1371 
1372 			At the end of the FES, TXPCU determines the ratio between
1373 			 the actual MPDU data words and Null delimiters. If this
1374 			 ratio is LESS then the ratio indicated here, TXPCU should
1375 			 indicate "Transmit_data_null_ratio_not_met" in the TX_FES_STATUS_END
1376 
1377 
1378 			<enum 0 No_Data_Null_ratio_requirement> TXPCU does not need
1379 			 to do any evaluation on the ratio between actual data transmitted
1380 			 and NULL delimiters inserted.
1381 			<enum 1 Data_Null_ratio_16_1> At the end of the FES, TXPCU
1382 			 shall confirm that the DATA:NULL delimiter ratio was at
1383 			 least 16:1. If not met, TXPCU should terminate FES.
1384 			<enum 2 Data_Null_ratio_8_1> At the end of the FES, TXPCU
1385 			 shall confirm that the DATA:NULL delimiter ratio was at
1386 			 least 8:1. If not met, TXPCU should terminate FES.
1387 			<enum 3 Data_Null_ratio_4_1> At the end of the FES, TXPCU
1388 			 shall confirm that the DATA:NULL delimiter ratio was at
1389 			 least 4:1. If not met, TXPCU should terminate FES.
1390 			<enum 4 Data_Null_ratio_2_1> At the end of the FES, TXPCU
1391 			 shall confirm that the DATA:NULL delimiter ratio was at
1392 			 least 2:1. If not met, TXPCU should terminate FES.
1393 			<enum 5 Data_Null_ratio_1_1> At the end of the FES, TXPCU
1394 			 shall confirm that the DATA:NULL delimiter ratio was at
1395 			 least 1:1. If not met, TXPCU should terminate FES.
1396 			<enum 6 Data_Null_ratio_1_2> At the end of the FES, TXPCU
1397 			 shall confirm that the DATA:NULL delimiter ratio was at
1398 			 least 1:2. If not met, TXPCU should terminate FES.
1399 			<enum 7 Data_Null_ratio_1_4> At the end of the FES, TXPCU
1400 			 shall confirm that the DATA:NULL delimiter ratio was at
1401 			 least 1:4. If not met, TXPCU should terminate FES.
1402 			<enum 8 Data_Null_ratio_1_8> At the end of the FES, TXPCU
1403 			 shall confirm that the DATA:NULL delimiter ratio was at
1404 			 least 1:8. If not met, TXPCU should terminate FES.
1405 			<enum 9 Data_Null_ratio_1_16> At the end of the FES, TXPCU
1406 			 shall confirm that the DATA:NULL delimiter ratio was at
1407 			 least 1:16. If not met, TXPCU should terminate FES.
1408 
1409 			<legal 0-9>
1410 */
1411 
1412 #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET                        0x0000000000000010
1413 #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB                           27
1414 #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB                           31
1415 #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK                          0x00000000f8000000
1416 
1417 
1418 /* Description		TRANSMIT_CCA_BITMAP
1419 
1420 			The CCA signals that shall be evaluated by TXPCU to determine
1421 			 the BW/puncture pattern available for transmission.
1422 
1423 			0: CCA signal not needed. Ignore the CCA setting
1424 			1: CCA signals shall be evaluated
1425 
1426 			Bit [1:0]     => cca20_0 related signals
1427 			Bit [3:2]   => cca20_1 related signals
1428 			...
1429 			Bit [31:30] => cca20_15 related signals
1430 
1431 			Within the 2 bits, the order is always:
1432 			Bit0: ED
1433 			Bit1: GI
1434 
1435 			NOTE: HW Sch takes care of MUXing ED1/ED2 with ED0 and MUXing
1436 			 GI1 with GI0. Hence this field should be set to 0x55555555
1437 			 for chips not supporting GI-correlation and 0xFFFFFFFF
1438 			for chips that support, usually.
1439 			<legal all>
1440 */
1441 
1442 #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET                                     0x0000000000000010
1443 #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB                                        32
1444 #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB                                        63
1445 #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK                                       0xffffffff00000000
1446 
1447 
1448 /* Description		TB_RANGING
1449 
1450 			Indicates that this frame is generated for a TB ranging
1451 			sequence
1452 			<legal all>
1453 */
1454 
1455 #define TX_FES_SETUP_TB_RANGING_OFFSET                                              0x0000000000000018
1456 #define TX_FES_SETUP_TB_RANGING_LSB                                                 0
1457 #define TX_FES_SETUP_TB_RANGING_MSB                                                 0
1458 #define TX_FES_SETUP_TB_RANGING_MASK                                                0x0000000000000001
1459 
1460 
1461 /* Description		RANGING_TRIGGER_SUBTYPE
1462 
1463 			Field only valid if TB_Ranging is set
1464 
1465 			Indicates the Trigger subtype for the current ranging TF
1466 
1467 
1468 			<enum 0 TF_Poll>
1469 			<enum 1 TF_Sound>
1470 			<enum 2 TF_Secure_Sound>
1471 			<enum 3 TF_Report>
1472 
1473 			<legal 0-3>
1474 */
1475 
1476 #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_OFFSET                                 0x0000000000000018
1477 #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_LSB                                    1
1478 #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MSB                                    4
1479 #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MASK                                   0x000000000000001e
1480 
1481 
1482 /* Description		MIN_CTS2SELF_COUNT
1483 
1484 			Field only valid when max_cts2self_count is non-zero
1485 
1486 			This is the minimum number of CTS2SELF frames that PDG should
1487 			 transmit before the actual data transmission.
1488 */
1489 
1490 #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET                                      0x0000000000000018
1491 #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB                                         5
1492 #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB                                         8
1493 #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK                                        0x00000000000001e0
1494 
1495 
1496 /* Description		MAX_CTS2SELF_COUNT
1497 
1498 			Field only valid when non-zero
1499 
1500 			This is the maximum number of CTS2SELF frames that PDG is
1501 			 allowed to transmit before the actual data transmission.
1502 			PDG will only use these additional frames if MPDU info from
1503 			 TQM or CV-correlation info from microcode is delayed.
1504 */
1505 
1506 #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET                                      0x0000000000000018
1507 #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB                                         9
1508 #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB                                         12
1509 #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK                                        0x0000000000001e00
1510 
1511 
1512 /* Description		WIFI_RADAR_ENABLE
1513 
1514 			When set to 1, the packet is intended to be used by PHY
1515 			for WiFi radar (by sensing the reflected WiFi signal).
1516 			<legal all>
1517 */
1518 
1519 #define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET                                       0x0000000000000018
1520 #define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB                                          13
1521 #define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB                                          13
1522 #define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK                                         0x0000000000002000
1523 
1524 
1525 /* Description		RESERVED_6A
1526 
1527 			Bit 14: cqi_feedback:
1528 			Consumer: TXPCU
1529 			Producer: SCH
1530 
1531 			MSB of the expected feedback type of received CBF frame
1532 			after sending NDP or BR-Poll in case of HE/EHT sounding.
1533 			See field cbf_feedback_type above for the LSB. This field
1534 			 is compared only if cbf_feedback_type_mask is set to 1.
1535 
1536 			0: compressed beamforming feedback
1537 			1: CQI feedback
1538 
1539 			<legal 0-1>
1540 */
1541 
1542 #define TX_FES_SETUP_RESERVED_6A_OFFSET                                             0x0000000000000018
1543 #define TX_FES_SETUP_RESERVED_6A_LSB                                                14
1544 #define TX_FES_SETUP_RESERVED_6A_MSB                                                31
1545 #define TX_FES_SETUP_RESERVED_6A_MASK                                               0x00000000ffffc000
1546 
1547 
1548 /* Description		MONITOR_OVERRIDE_STA_31_0
1549 
1550 			Used by TXMON
1551 
1552 			LSB 32 bits of a 37-bit user bitmap with 1s denoting the
1553 			 'tlv_usr' values that correspond to'Monitor override client's
1554 
1555 
1556 			When enabled in TXMON, it will discard the user-TLVs of
1557 			the users not selected by the bitmap. FW should program
1558 			this setting in line with the 'Monitor_override_sta' setting
1559 			 in the 'ADDR_SEARCH_ENTRY' corresponding to each of the
1560 			 clients.
1561 
1562 			<legal all>
1563 */
1564 
1565 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET                               0x0000000000000018
1566 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB                                  32
1567 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB                                  63
1568 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK                                 0xffffffff00000000
1569 
1570 
1571 /* Description		MONITOR_OVERRIDE_STA_36_32
1572 
1573 			Used by TXMON
1574 
1575 			MSB 5 bits of a 37-bit user bitmap with 1s denoting the 'tlv_usr'
1576 			values that correspond to 'Monitor override client's
1577 
1578 			See 'Monitor_override_sta_31_0.'
1579 
1580 			Hamilton v1 did not include this (and any subsequent) word.
1581 
1582 			<legal all>
1583 */
1584 
1585 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET                              0x0000000000000020
1586 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB                                 0
1587 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB                                 4
1588 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK                                0x000000000000001f
1589 
1590 
1591 /* Description		RESERVED_8A
1592 
1593 			<legal 0>
1594 */
1595 
1596 #define TX_FES_SETUP_RESERVED_8A_OFFSET                                             0x0000000000000020
1597 #define TX_FES_SETUP_RESERVED_8A_LSB                                                5
1598 #define TX_FES_SETUP_RESERVED_8A_MSB                                                31
1599 #define TX_FES_SETUP_RESERVED_8A_MASK                                               0x00000000ffffffe0
1600 
1601 
1602 /* Description		FW2SW_INFO
1603 
1604 			This field is provided by FW, to be logged via TXMON to
1605 			host SW. It is transparent to HW.
1606 
1607 			<legal all>
1608 */
1609 
1610 #define TX_FES_SETUP_FW2SW_INFO_OFFSET                                              0x0000000000000020
1611 #define TX_FES_SETUP_FW2SW_INFO_LSB                                                 32
1612 #define TX_FES_SETUP_FW2SW_INFO_MSB                                                 63
1613 #define TX_FES_SETUP_FW2SW_INFO_MASK                                                0xffffffff00000000
1614 
1615 
1616 
1617 #endif   // TX_FES_SETUP
1618