1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _TX_FES_STATUS_1K_BA_H_ 27 #define _TX_FES_STATUS_1K_BA_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34 32 33 #define NUM_OF_QWORDS_TX_FES_STATUS_1K_BA 17 34 35 36 struct tx_fes_status_1k_ba { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t ack_ba_status_type : 1, // [0:0] 39 ba_type : 1, // [1:1] 40 ba_tid : 4, // [5:2] 41 unexpected_ack_or_ba : 1, // [6:6] 42 response_timeout : 1, // [7:7] 43 ack_frame_rssi : 8, // [15:8] 44 ssn : 12, // [27:16] 45 reserved_0b : 4; // [31:28] 46 uint32_t sw_peer_id : 16, // [15:0] 47 reserved_1a : 16; // [31:16] 48 uint32_t ba_bitmap_31_0 : 32; // [31:0] 49 uint32_t ba_bitmap_63_32 : 32; // [31:0] 50 uint32_t ba_bitmap_95_64 : 32; // [31:0] 51 uint32_t ba_bitmap_127_96 : 32; // [31:0] 52 uint32_t ba_bitmap_159_128 : 32; // [31:0] 53 uint32_t ba_bitmap_191_160 : 32; // [31:0] 54 uint32_t ba_bitmap_223_192 : 32; // [31:0] 55 uint32_t ba_bitmap_255_224 : 32; // [31:0] 56 uint32_t ba_bitmap_287_256 : 32; // [31:0] 57 uint32_t ba_bitmap_319_288 : 32; // [31:0] 58 uint32_t ba_bitmap_351_320 : 32; // [31:0] 59 uint32_t ba_bitmap_383_352 : 32; // [31:0] 60 uint32_t ba_bitmap_415_384 : 32; // [31:0] 61 uint32_t ba_bitmap_447_416 : 32; // [31:0] 62 uint32_t ba_bitmap_479_448 : 32; // [31:0] 63 uint32_t ba_bitmap_511_480 : 32; // [31:0] 64 uint32_t ba_bitmap_543_512 : 32; // [31:0] 65 uint32_t ba_bitmap_575_544 : 32; // [31:0] 66 uint32_t ba_bitmap_607_576 : 32; // [31:0] 67 uint32_t ba_bitmap_639_608 : 32; // [31:0] 68 uint32_t ba_bitmap_671_640 : 32; // [31:0] 69 uint32_t ba_bitmap_703_672 : 32; // [31:0] 70 uint32_t ba_bitmap_735_704 : 32; // [31:0] 71 uint32_t ba_bitmap_767_736 : 32; // [31:0] 72 uint32_t ba_bitmap_799_768 : 32; // [31:0] 73 uint32_t ba_bitmap_831_800 : 32; // [31:0] 74 uint32_t ba_bitmap_863_832 : 32; // [31:0] 75 uint32_t ba_bitmap_895_864 : 32; // [31:0] 76 uint32_t ba_bitmap_927_896 : 32; // [31:0] 77 uint32_t ba_bitmap_959_928 : 32; // [31:0] 78 uint32_t ba_bitmap_991_960 : 32; // [31:0] 79 uint32_t ba_bitmap_1023_992 : 32; // [31:0] 80 #else 81 uint32_t reserved_0b : 4, // [31:28] 82 ssn : 12, // [27:16] 83 ack_frame_rssi : 8, // [15:8] 84 response_timeout : 1, // [7:7] 85 unexpected_ack_or_ba : 1, // [6:6] 86 ba_tid : 4, // [5:2] 87 ba_type : 1, // [1:1] 88 ack_ba_status_type : 1; // [0:0] 89 uint32_t reserved_1a : 16, // [31:16] 90 sw_peer_id : 16; // [15:0] 91 uint32_t ba_bitmap_31_0 : 32; // [31:0] 92 uint32_t ba_bitmap_63_32 : 32; // [31:0] 93 uint32_t ba_bitmap_95_64 : 32; // [31:0] 94 uint32_t ba_bitmap_127_96 : 32; // [31:0] 95 uint32_t ba_bitmap_159_128 : 32; // [31:0] 96 uint32_t ba_bitmap_191_160 : 32; // [31:0] 97 uint32_t ba_bitmap_223_192 : 32; // [31:0] 98 uint32_t ba_bitmap_255_224 : 32; // [31:0] 99 uint32_t ba_bitmap_287_256 : 32; // [31:0] 100 uint32_t ba_bitmap_319_288 : 32; // [31:0] 101 uint32_t ba_bitmap_351_320 : 32; // [31:0] 102 uint32_t ba_bitmap_383_352 : 32; // [31:0] 103 uint32_t ba_bitmap_415_384 : 32; // [31:0] 104 uint32_t ba_bitmap_447_416 : 32; // [31:0] 105 uint32_t ba_bitmap_479_448 : 32; // [31:0] 106 uint32_t ba_bitmap_511_480 : 32; // [31:0] 107 uint32_t ba_bitmap_543_512 : 32; // [31:0] 108 uint32_t ba_bitmap_575_544 : 32; // [31:0] 109 uint32_t ba_bitmap_607_576 : 32; // [31:0] 110 uint32_t ba_bitmap_639_608 : 32; // [31:0] 111 uint32_t ba_bitmap_671_640 : 32; // [31:0] 112 uint32_t ba_bitmap_703_672 : 32; // [31:0] 113 uint32_t ba_bitmap_735_704 : 32; // [31:0] 114 uint32_t ba_bitmap_767_736 : 32; // [31:0] 115 uint32_t ba_bitmap_799_768 : 32; // [31:0] 116 uint32_t ba_bitmap_831_800 : 32; // [31:0] 117 uint32_t ba_bitmap_863_832 : 32; // [31:0] 118 uint32_t ba_bitmap_895_864 : 32; // [31:0] 119 uint32_t ba_bitmap_927_896 : 32; // [31:0] 120 uint32_t ba_bitmap_959_928 : 32; // [31:0] 121 uint32_t ba_bitmap_991_960 : 32; // [31:0] 122 uint32_t ba_bitmap_1023_992 : 32; // [31:0] 123 #endif 124 }; 125 126 127 /* Description ACK_BA_STATUS_TYPE 128 129 Consumer: SW 130 Producer: RXPCU 131 132 <enum 1 1K_BA_type> This TLV represents an BA reception. 133 134 <legal 1> 135 */ 136 137 #define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 138 #define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB 0 139 #define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB 0 140 #define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 141 142 143 /* Description BA_TYPE 144 145 <enum 1 1K_BA_TYPE_bitmap> 146 <legal 1> 147 */ 148 149 #define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET 0x0000000000000000 150 #define TX_FES_STATUS_1K_BA_BA_TYPE_LSB 1 151 #define TX_FES_STATUS_1K_BA_BA_TYPE_MSB 1 152 #define TX_FES_STATUS_1K_BA_BA_TYPE_MASK 0x0000000000000002 153 154 155 /* Description BA_TID 156 157 The TID field copied from the BA frame 158 <legal all> 159 */ 160 161 #define TX_FES_STATUS_1K_BA_BA_TID_OFFSET 0x0000000000000000 162 #define TX_FES_STATUS_1K_BA_BA_TID_LSB 2 163 #define TX_FES_STATUS_1K_BA_BA_TID_MSB 5 164 #define TX_FES_STATUS_1K_BA_BA_TID_MASK 0x000000000000003c 165 166 167 /* Description UNEXPECTED_ACK_OR_BA 168 169 Set when RXPCU received a BA for which there was no " RXPCU_USER_SETUP_EXT 170 TLV' received. 171 This can happen when a BA for unexpected TID is received. 172 173 174 This message enables SW to still pass this BA information 175 on to the right TQM queue. 176 <legal all> 177 */ 178 179 #define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 180 #define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB 6 181 #define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB 6 182 #define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 183 184 185 /* Description RESPONSE_TIMEOUT 186 187 When set, there was delay in RXPCU (likely due to AST fetch 188 delay) that resulted in TXPCU not being able to send the 189 RX_RESPONSE_REQUIRED_INFO TLV within a certain timeout 190 from the falling edge of the frame. This status TLV is still 191 generated but RXPCU will NOT have generated the RX_RESPONSE_REQUIRED 192 TLV. 193 <legal all> 194 */ 195 196 #define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 197 #define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB 7 198 #define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB 7 199 #define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 200 201 202 /* Description ACK_FRAME_RSSI 203 204 RSSI of the received ACK, BA or M-BA frame. 205 206 <legal all> 207 */ 208 209 #define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 210 #define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB 8 211 #define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB 15 212 #define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 213 214 215 /* Description SSN 216 217 Consumer: TQM/FW 218 Producer: SW/RXPCU 219 220 Field only valid in case of the Ack_ba_status_type indicating: 221 BA_type 222 223 The starting Sequence number of the (B)ACK bitmap <legal 224 all> 225 */ 226 227 #define TX_FES_STATUS_1K_BA_SSN_OFFSET 0x0000000000000000 228 #define TX_FES_STATUS_1K_BA_SSN_LSB 16 229 #define TX_FES_STATUS_1K_BA_SSN_MSB 27 230 #define TX_FES_STATUS_1K_BA_SSN_MASK 0x000000000fff0000 231 232 233 /* Description RESERVED_0B 234 235 <legal 0> 236 */ 237 238 #define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET 0x0000000000000000 239 #define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB 28 240 #define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB 31 241 #define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK 0x00000000f0000000 242 243 244 /* Description SW_PEER_ID 245 246 The sw_peer_id for which the bitmap is requested. 247 248 SW could use this info to link this TLV back to the right 249 TQM queue (if needed) 250 <legal all> 251 */ 252 253 #define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET 0x0000000000000000 254 #define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB 32 255 #define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB 47 256 #define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK 0x0000ffff00000000 257 258 259 /* Description RESERVED_1A 260 261 <legal 0> 262 */ 263 264 #define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET 0x0000000000000000 265 #define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB 48 266 #define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB 63 267 #define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK 0xffff000000000000 268 269 270 /* Description BA_BITMAP_31_0 271 272 Consumer: TQM/FW 273 Producer: SW/RXPCU 274 275 Ba_bitmap_31_0 276 <legal all> 277 */ 278 279 #define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 280 #define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB 0 281 #define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB 31 282 #define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff 283 284 285 /* Description BA_BITMAP_63_32 286 287 Consumer: TQM/FW 288 Producer: SW/RXPCU 289 290 Ba_bitmap_63_32 291 <legal all> 292 */ 293 294 #define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 295 #define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB 32 296 #define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB 63 297 #define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 298 299 300 /* Description BA_BITMAP_95_64 301 302 Consumer: TQM/FW 303 Producer: SW/RXPCU 304 305 Ba_bitmap_95_64 306 <legal all> 307 */ 308 309 #define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 310 #define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB 0 311 #define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB 31 312 #define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff 313 314 315 /* Description BA_BITMAP_127_96 316 317 Consumer: TQM/FW 318 Producer: SW/RXPCU 319 320 Ba_bitmap_127_96 321 <legal all> 322 */ 323 324 #define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 325 #define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB 32 326 #define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB 63 327 #define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 328 329 330 /* Description BA_BITMAP_159_128 331 332 Consumer: TQM/FW 333 Producer: SW/RXPCU 334 335 Ba_bitmap_159_128 336 <legal all> 337 */ 338 339 #define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 340 #define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB 0 341 #define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB 31 342 #define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff 343 344 345 /* Description BA_BITMAP_191_160 346 347 Consumer: TQM/FW 348 Producer: SW/RXPCU 349 350 Ba_bitmap_191_160 351 <legal all> 352 */ 353 354 #define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 355 #define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB 32 356 #define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB 63 357 #define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 358 359 360 /* Description BA_BITMAP_223_192 361 362 Consumer: TQM/FW 363 Producer: SW/RXPCU 364 365 Ba_bitmap_223_192 366 <legal all> 367 */ 368 369 #define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 370 #define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB 0 371 #define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB 31 372 #define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff 373 374 375 /* Description BA_BITMAP_255_224 376 377 Consumer: TQM/FW 378 Producer: SW/RXPCU 379 380 Ba_bitmap_255_224 381 <legal all> 382 */ 383 384 #define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 385 #define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB 32 386 #define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB 63 387 #define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 388 389 390 /* Description BA_BITMAP_287_256 391 392 Ba_bitmap_287_256 393 <legal all> 394 */ 395 396 #define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET 0x0000000000000028 397 #define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB 0 398 #define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB 31 399 #define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK 0x00000000ffffffff 400 401 402 /* Description BA_BITMAP_319_288 403 404 Ba_bitmap_319_288 405 <legal all> 406 */ 407 408 #define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET 0x0000000000000028 409 #define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB 32 410 #define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB 63 411 #define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK 0xffffffff00000000 412 413 414 /* Description BA_BITMAP_351_320 415 416 Ba_bitmap_351_320 417 <legal all> 418 */ 419 420 #define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET 0x0000000000000030 421 #define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB 0 422 #define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB 31 423 #define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK 0x00000000ffffffff 424 425 426 /* Description BA_BITMAP_383_352 427 428 Ba_bitmap_383_352 429 <legal all> 430 */ 431 432 #define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET 0x0000000000000030 433 #define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB 32 434 #define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB 63 435 #define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK 0xffffffff00000000 436 437 438 /* Description BA_BITMAP_415_384 439 440 Ba_bitmap_415_384 441 <legal all> 442 */ 443 444 #define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET 0x0000000000000038 445 #define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB 0 446 #define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB 31 447 #define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK 0x00000000ffffffff 448 449 450 /* Description BA_BITMAP_447_416 451 452 Ba_bitmap_447_416 453 <legal all> 454 */ 455 456 #define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET 0x0000000000000038 457 #define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB 32 458 #define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB 63 459 #define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK 0xffffffff00000000 460 461 462 /* Description BA_BITMAP_479_448 463 464 Ba_bitmap_479_448 465 <legal all> 466 */ 467 468 #define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET 0x0000000000000040 469 #define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB 0 470 #define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB 31 471 #define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK 0x00000000ffffffff 472 473 474 /* Description BA_BITMAP_511_480 475 476 Ba_bitmap_511_480 477 <legal all> 478 */ 479 480 #define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET 0x0000000000000040 481 #define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB 32 482 #define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB 63 483 #define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK 0xffffffff00000000 484 485 486 /* Description BA_BITMAP_543_512 487 488 Ba_bitmap_543_512 489 <legal all> 490 */ 491 492 #define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET 0x0000000000000048 493 #define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB 0 494 #define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB 31 495 #define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK 0x00000000ffffffff 496 497 498 /* Description BA_BITMAP_575_544 499 500 Ba_bitmap_575_544 501 <legal all> 502 */ 503 504 #define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET 0x0000000000000048 505 #define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB 32 506 #define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB 63 507 #define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK 0xffffffff00000000 508 509 510 /* Description BA_BITMAP_607_576 511 512 Ba_bitmap_607_576 513 <legal all> 514 */ 515 516 #define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET 0x0000000000000050 517 #define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB 0 518 #define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB 31 519 #define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK 0x00000000ffffffff 520 521 522 /* Description BA_BITMAP_639_608 523 524 Ba_bitmap_639_608 525 <legal all> 526 */ 527 528 #define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET 0x0000000000000050 529 #define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB 32 530 #define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB 63 531 #define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK 0xffffffff00000000 532 533 534 /* Description BA_BITMAP_671_640 535 536 Ba_bitmap_671_640 537 <legal all> 538 */ 539 540 #define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET 0x0000000000000058 541 #define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB 0 542 #define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB 31 543 #define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK 0x00000000ffffffff 544 545 546 /* Description BA_BITMAP_703_672 547 548 Ba_bitmap_703_672 549 <legal all> 550 */ 551 552 #define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET 0x0000000000000058 553 #define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB 32 554 #define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB 63 555 #define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK 0xffffffff00000000 556 557 558 /* Description BA_BITMAP_735_704 559 560 Ba_bitmap_735_704 561 <legal all> 562 */ 563 564 #define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET 0x0000000000000060 565 #define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB 0 566 #define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB 31 567 #define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK 0x00000000ffffffff 568 569 570 /* Description BA_BITMAP_767_736 571 572 Ba_bitmap_767_736 573 <legal all> 574 */ 575 576 #define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET 0x0000000000000060 577 #define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB 32 578 #define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB 63 579 #define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK 0xffffffff00000000 580 581 582 /* Description BA_BITMAP_799_768 583 584 Ba_bitmap_799_768 585 <legal all> 586 */ 587 588 #define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET 0x0000000000000068 589 #define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB 0 590 #define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB 31 591 #define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK 0x00000000ffffffff 592 593 594 /* Description BA_BITMAP_831_800 595 596 Ba_bitmap_831_800 597 <legal all> 598 */ 599 600 #define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET 0x0000000000000068 601 #define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB 32 602 #define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB 63 603 #define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK 0xffffffff00000000 604 605 606 /* Description BA_BITMAP_863_832 607 608 Ba_bitmap_863_832 609 <legal all> 610 */ 611 612 #define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET 0x0000000000000070 613 #define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB 0 614 #define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB 31 615 #define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK 0x00000000ffffffff 616 617 618 /* Description BA_BITMAP_895_864 619 620 Ba_bitmap_895_864 621 <legal all> 622 */ 623 624 #define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET 0x0000000000000070 625 #define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB 32 626 #define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB 63 627 #define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK 0xffffffff00000000 628 629 630 /* Description BA_BITMAP_927_896 631 632 Ba_bitmap_927_896 633 <legal all> 634 */ 635 636 #define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET 0x0000000000000078 637 #define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB 0 638 #define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB 31 639 #define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK 0x00000000ffffffff 640 641 642 /* Description BA_BITMAP_959_928 643 644 Ba_bitmap_959_928 645 <legal all> 646 */ 647 648 #define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET 0x0000000000000078 649 #define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB 32 650 #define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB 63 651 #define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK 0xffffffff00000000 652 653 654 /* Description BA_BITMAP_991_960 655 656 Ba_bitmap_991_960 657 <legal all> 658 */ 659 660 #define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET 0x0000000000000080 661 #define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB 0 662 #define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB 31 663 #define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK 0x00000000ffffffff 664 665 666 /* Description BA_BITMAP_1023_992 667 668 Ba_bitmap_1023_992 669 <legal all> 670 */ 671 672 #define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET 0x0000000000000080 673 #define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB 32 674 #define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB 63 675 #define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK 0xffffffff00000000 676 677 678 679 #endif // TX_FES_STATUS_1K_BA 680