1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _TX_FES_STATUS_END_H_ 27 #define _TX_FES_STATUS_END_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "phytx_abort_request_info.h" 32 #define NUM_OF_DWORDS_TX_FES_STATUS_END 22 33 34 #define NUM_OF_QWORDS_TX_FES_STATUS_END 11 35 36 37 struct tx_fes_status_end { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 uint32_t prot_coex_bt_tx_while_wlan_tx : 1, // [0:0] 40 prot_coex_bt_tx_while_wlan_rx : 1, // [1:1] 41 prot_coex_wan_tx_while_wlan_tx : 1, // [2:2] 42 prot_coex_wan_tx_while_wlan_rx : 1, // [3:3] 43 prot_coex_wlan_tx_while_wlan_tx : 1, // [4:4] 44 prot_coex_wlan_tx_while_wlan_rx : 1, // [5:5] 45 coex_bt_tx_while_wlan_tx : 1, // [6:6] 46 coex_bt_tx_while_wlan_rx : 1, // [7:7] 47 coex_wan_tx_while_wlan_tx : 1, // [8:8] 48 coex_wan_tx_while_wlan_rx : 1, // [9:9] 49 coex_wlan_tx_while_wlan_tx : 1, // [10:10] 50 coex_wlan_tx_while_wlan_rx : 1, // [11:11] 51 global_data_underflow_warning : 1, // [12:12] 52 global_fes_transmit_result : 4, // [16:13] 53 cbf_bw_received_valid : 1, // [17:17] 54 cbf_bw_received : 3, // [20:18] 55 actual_received_ack_type : 4, // [24:21] 56 sta_response_count : 6, // [30:25] 57 dpdtrain_done : 1; // [31:31] 58 struct phytx_abort_request_info phytx_abort_request_info_details; 59 uint16_t reserved_after_struct16 : 4, // [19:16] 60 brp_info_valid : 1, // [20:20] 61 reserved_1a : 6, // [26:21] 62 phytx_pkt_end_info_valid : 1, // [27:27] 63 phytx_abort_request_info_valid : 1, // [28:28] 64 fes_in_11ax_trigger_response_config : 1, // [29:29] 65 null_delim_inserted_before_mpdus : 1, // [30:30] 66 only_null_delim_sent : 1; // [31:31] 67 uint32_t start_of_frame_timestamp_15_0 : 16, // [15:0] 68 start_of_frame_timestamp_31_16 : 16; // [31:16] 69 uint32_t end_of_frame_timestamp_15_0 : 16, // [15:0] 70 end_of_frame_timestamp_31_16 : 16; // [31:16] 71 uint32_t terminate_ranging_sequence : 1, // [0:0] 72 reserved_4a : 7, // [7:1] 73 timing_status : 2, // [9:8] 74 response_type : 5, // [14:10] 75 r2r_end_status_to_follow : 1, // [15:15] 76 transmit_delay : 16; // [31:16] 77 uint32_t tx_group_delay : 12, // [11:0] 78 reserved_5a : 4, // [15:12] 79 tpc_dbg_info_cmn_15_0 : 16; // [31:16] 80 uint32_t tpc_dbg_info_cmn_31_16 : 16, // [15:0] 81 tpc_dbg_info_47_32 : 16; // [31:16] 82 uint32_t tpc_dbg_info_chn1_15_0 : 16, // [15:0] 83 tpc_dbg_info_chn1_31_16 : 16; // [31:16] 84 uint32_t tpc_dbg_info_chn1_47_32 : 16, // [15:0] 85 tpc_dbg_info_chn1_63_48 : 16; // [31:16] 86 uint32_t tpc_dbg_info_chn1_79_64 : 16, // [15:0] 87 tpc_dbg_info_chn2_15_0 : 16; // [31:16] 88 uint32_t tpc_dbg_info_chn2_31_16 : 16, // [15:0] 89 tpc_dbg_info_chn2_47_32 : 16; // [31:16] 90 uint32_t tpc_dbg_info_chn2_63_48 : 16, // [15:0] 91 tpc_dbg_info_chn2_79_64 : 16; // [31:16] 92 uint32_t phytx_tx_end_sw_info_15_0 : 16, // [15:0] 93 phytx_tx_end_sw_info_31_16 : 16; // [31:16] 94 uint32_t phytx_tx_end_sw_info_47_32 : 16, // [15:0] 95 phytx_tx_end_sw_info_63_48 : 16; // [31:16] 96 uint32_t beamform_masked_user_bitmap_15_0 : 16, // [15:0] 97 beamform_masked_user_bitmap_31_16 : 16; // [31:16] 98 uint32_t cbf_segment_request_mask : 8, // [7:0] 99 cbf_segment_sent_mask : 8, // [15:8] 100 highest_achieved_data_null_ratio : 5, // [20:16] 101 use_alt_power_sr : 1, // [21:21] 102 static_2_pwr_mode_status : 1, // [22:22] 103 obss_srg_opport_transmit_status : 1, // [23:23] 104 srp_based_transmit_status : 1, // [24:24] 105 obss_pd_based_transmit_status : 1, // [25:25] 106 beamform_masked_user_bitmap_36_32 : 5, // [30:26] 107 pdg_mpdu_ready : 1; // [31:31] 108 uint32_t pdg_mpdu_count : 16, // [15:0] 109 pdg_est_mpdu_tx_count : 16; // [31:16] 110 uint32_t pdg_overview_length : 24, // [23:0] 111 txop_duration : 7, // [30:24] 112 pdg_dropped_mpdu_warning : 1; // [31:31] 113 uint32_t packet_extension_a_factor : 2, // [1:0] 114 packet_extension_pe_disambiguity : 1, // [2:2] 115 packet_extension : 3, // [5:3] 116 fec_type : 1, // [6:6] 117 stbc : 1, // [7:7] 118 num_data_symbols : 16, // [23:8] 119 ru_size : 4, // [27:24] 120 reserved_17a : 4; // [31:28] 121 uint32_t num_ltf_symbols : 3, // [2:0] 122 ltf_size : 2, // [4:3] 123 cp_setting : 2, // [6:5] 124 reserved_18a : 5, // [11:7] 125 dcm : 1, // [12:12] 126 ldpc_extra_symbol : 1, // [13:13] 127 force_extra_symbol : 1, // [14:14] 128 reserved_18b : 1, // [15:15] 129 tx_pwr_shared : 8, // [23:16] 130 tx_pwr_unshared : 8; // [31:24] 131 uint32_t ranging_active_user_map : 16, // [15:0] 132 ranging_sent_dummy_tx : 1, // [16:16] 133 ranging_ftm_frame_sent : 1, // [17:17] 134 reserved_20a : 6, // [23:18] 135 cv_corr_status : 8; // [31:24] 136 uint32_t current_tx_duration : 16, // [15:0] 137 reserved_21a : 16; // [31:16] 138 #else 139 uint32_t dpdtrain_done : 1, // [31:31] 140 sta_response_count : 6, // [30:25] 141 actual_received_ack_type : 4, // [24:21] 142 cbf_bw_received : 3, // [20:18] 143 cbf_bw_received_valid : 1, // [17:17] 144 global_fes_transmit_result : 4, // [16:13] 145 global_data_underflow_warning : 1, // [12:12] 146 coex_wlan_tx_while_wlan_rx : 1, // [11:11] 147 coex_wlan_tx_while_wlan_tx : 1, // [10:10] 148 coex_wan_tx_while_wlan_rx : 1, // [9:9] 149 coex_wan_tx_while_wlan_tx : 1, // [8:8] 150 coex_bt_tx_while_wlan_rx : 1, // [7:7] 151 coex_bt_tx_while_wlan_tx : 1, // [6:6] 152 prot_coex_wlan_tx_while_wlan_rx : 1, // [5:5] 153 prot_coex_wlan_tx_while_wlan_tx : 1, // [4:4] 154 prot_coex_wan_tx_while_wlan_rx : 1, // [3:3] 155 prot_coex_wan_tx_while_wlan_tx : 1, // [2:2] 156 prot_coex_bt_tx_while_wlan_rx : 1, // [1:1] 157 prot_coex_bt_tx_while_wlan_tx : 1; // [0:0] 158 uint32_t only_null_delim_sent : 1, // [31:31] 159 null_delim_inserted_before_mpdus : 1, // [30:30] 160 fes_in_11ax_trigger_response_config : 1, // [29:29] 161 phytx_abort_request_info_valid : 1, // [28:28] 162 phytx_pkt_end_info_valid : 1, // [27:27] 163 reserved_1a : 6, // [26:21] 164 brp_info_valid : 1, // [20:20] 165 reserved_after_struct16 : 4; // [19:16] 166 struct phytx_abort_request_info phytx_abort_request_info_details; 167 uint32_t start_of_frame_timestamp_31_16 : 16, // [31:16] 168 start_of_frame_timestamp_15_0 : 16; // [15:0] 169 uint32_t end_of_frame_timestamp_31_16 : 16, // [31:16] 170 end_of_frame_timestamp_15_0 : 16; // [15:0] 171 uint32_t transmit_delay : 16, // [31:16] 172 r2r_end_status_to_follow : 1, // [15:15] 173 response_type : 5, // [14:10] 174 timing_status : 2, // [9:8] 175 reserved_4a : 7, // [7:1] 176 terminate_ranging_sequence : 1; // [0:0] 177 uint32_t tpc_dbg_info_cmn_15_0 : 16, // [31:16] 178 reserved_5a : 4, // [15:12] 179 tx_group_delay : 12; // [11:0] 180 uint32_t tpc_dbg_info_47_32 : 16, // [31:16] 181 tpc_dbg_info_cmn_31_16 : 16; // [15:0] 182 uint32_t tpc_dbg_info_chn1_31_16 : 16, // [31:16] 183 tpc_dbg_info_chn1_15_0 : 16; // [15:0] 184 uint32_t tpc_dbg_info_chn1_63_48 : 16, // [31:16] 185 tpc_dbg_info_chn1_47_32 : 16; // [15:0] 186 uint32_t tpc_dbg_info_chn2_15_0 : 16, // [31:16] 187 tpc_dbg_info_chn1_79_64 : 16; // [15:0] 188 uint32_t tpc_dbg_info_chn2_47_32 : 16, // [31:16] 189 tpc_dbg_info_chn2_31_16 : 16; // [15:0] 190 uint32_t tpc_dbg_info_chn2_79_64 : 16, // [31:16] 191 tpc_dbg_info_chn2_63_48 : 16; // [15:0] 192 uint32_t phytx_tx_end_sw_info_31_16 : 16, // [31:16] 193 phytx_tx_end_sw_info_15_0 : 16; // [15:0] 194 uint32_t phytx_tx_end_sw_info_63_48 : 16, // [31:16] 195 phytx_tx_end_sw_info_47_32 : 16; // [15:0] 196 uint32_t beamform_masked_user_bitmap_31_16 : 16, // [31:16] 197 beamform_masked_user_bitmap_15_0 : 16; // [15:0] 198 uint32_t pdg_mpdu_ready : 1, // [31:31] 199 beamform_masked_user_bitmap_36_32 : 5, // [30:26] 200 obss_pd_based_transmit_status : 1, // [25:25] 201 srp_based_transmit_status : 1, // [24:24] 202 obss_srg_opport_transmit_status : 1, // [23:23] 203 static_2_pwr_mode_status : 1, // [22:22] 204 use_alt_power_sr : 1, // [21:21] 205 highest_achieved_data_null_ratio : 5, // [20:16] 206 cbf_segment_sent_mask : 8, // [15:8] 207 cbf_segment_request_mask : 8; // [7:0] 208 uint32_t pdg_est_mpdu_tx_count : 16, // [31:16] 209 pdg_mpdu_count : 16; // [15:0] 210 uint32_t pdg_dropped_mpdu_warning : 1, // [31:31] 211 txop_duration : 7, // [30:24] 212 pdg_overview_length : 24; // [23:0] 213 uint32_t reserved_17a : 4, // [31:28] 214 ru_size : 4, // [27:24] 215 num_data_symbols : 16, // [23:8] 216 stbc : 1, // [7:7] 217 fec_type : 1, // [6:6] 218 packet_extension : 3, // [5:3] 219 packet_extension_pe_disambiguity : 1, // [2:2] 220 packet_extension_a_factor : 2; // [1:0] 221 uint32_t tx_pwr_unshared : 8, // [31:24] 222 tx_pwr_shared : 8, // [23:16] 223 reserved_18b : 1, // [15:15] 224 force_extra_symbol : 1, // [14:14] 225 ldpc_extra_symbol : 1, // [13:13] 226 dcm : 1, // [12:12] 227 reserved_18a : 5, // [11:7] 228 cp_setting : 2, // [6:5] 229 ltf_size : 2, // [4:3] 230 num_ltf_symbols : 3; // [2:0] 231 uint32_t cv_corr_status : 8, // [31:24] 232 reserved_20a : 6, // [23:18] 233 ranging_ftm_frame_sent : 1, // [17:17] 234 ranging_sent_dummy_tx : 1, // [16:16] 235 ranging_active_user_map : 16; // [15:0] 236 uint32_t reserved_21a : 16, // [31:16] 237 current_tx_duration : 16; // [15:0] 238 #endif 239 }; 240 241 242 /* Description PROT_COEX_BT_TX_WHILE_WLAN_TX 243 244 When set, a BT tx coex event started while wlan was in the 245 middle of TX a transmission. 246 247 Field set when coex_status_broadcast TLV received with bt 248 tx activity set and during WLAN tx 249 <legal all> 250 */ 251 252 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 253 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 254 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 255 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000001 256 257 258 /* Description PROT_COEX_BT_TX_WHILE_WLAN_RX 259 260 When set, a BT tx coex event started while wlan was in the 261 middle of TX a transmission. 262 263 Field set when coex broadcast TLV received with bt tx activity 264 set and during WLAN rx 265 <legal all> 266 */ 267 268 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 269 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_LSB 1 270 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MSB 1 271 #define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x0000000000000002 272 273 274 /* Description PROT_COEX_WAN_TX_WHILE_WLAN_TX 275 276 When set, a WAN tx coex event started while wlan was in 277 the middle of TX a transmission. 278 279 Field set when coex_status_broadcast TLV received with WAN 280 tx activity set and during WLAN tx 281 <legal all> 282 */ 283 284 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 285 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_LSB 2 286 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MSB 2 287 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000004 288 289 290 /* Description PROT_COEX_WAN_TX_WHILE_WLAN_RX 291 292 When set, a WAN tx coex event started while wlan was in 293 the middle of TX a transmission. 294 295 Field set when coex broadcast TLV received with WAN tx activity 296 set and during WLAN rx 297 <legal all> 298 */ 299 300 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 301 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_LSB 3 302 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MSB 3 303 #define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000008 304 305 306 /* Description PROT_COEX_WLAN_TX_WHILE_WLAN_TX 307 308 When set, a WLAN tx coex event started while wlan was in 309 the middle of TX a transmission. 310 311 Field set when coex_status_broadcast TLV received with WLAN 312 tx activity set and during WLAN tx 313 <legal all> 314 */ 315 316 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 317 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 4 318 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 4 319 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000010 320 321 322 /* Description PROT_COEX_WLAN_TX_WHILE_WLAN_RX 323 324 When set, a WLAN tx coex event started while wlan was in 325 the middle of TX a transmission. 326 327 Field set when coex broadcast TLV received with WLAN tx 328 activity set and during WLAN rx 329 <legal all> 330 */ 331 332 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 333 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 5 334 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 5 335 #define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000020 336 337 338 /* Description COEX_BT_TX_WHILE_WLAN_TX 339 340 When set, a BT tx coex event started while wlan was in the 341 middle of TX a transmission. 342 343 Field set when coex_status_broadcast TLV received with bt 344 tx activity set and during WLAN tx 345 <legal all> 346 */ 347 348 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 349 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_LSB 6 350 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MSB 6 351 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000040 352 353 354 /* Description COEX_BT_TX_WHILE_WLAN_RX 355 356 When set, a BT tx coex event started while wlan was in the 357 middle of TX a transmission. 358 359 Field set when coex broadcast TLV received with bt tx activity 360 set and during WLAN rx 361 <legal all> 362 */ 363 364 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 365 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_LSB 7 366 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MSB 7 367 #define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x0000000000000080 368 369 370 /* Description COEX_WAN_TX_WHILE_WLAN_TX 371 372 When set, a WAN tx coex event started while wlan was in 373 the middle of TX a transmission. 374 375 Field set when coex_status_broadcast TLV received with WAN 376 tx activity set and during WLAN tx 377 <legal all> 378 */ 379 380 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 381 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_LSB 8 382 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MSB 8 383 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000100 384 385 386 /* Description COEX_WAN_TX_WHILE_WLAN_RX 387 388 When set, a WAN tx coex event started while wlan was in 389 the middle of TX a transmission. 390 391 Field set when coex broadcast TLV received with WAN tx activity 392 set and during WLAN rx 393 <legal all> 394 */ 395 396 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 397 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_LSB 9 398 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MSB 9 399 #define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000200 400 401 402 /* Description COEX_WLAN_TX_WHILE_WLAN_TX 403 404 When set, a WLAN tx coex event started while wlan was in 405 the middle of TX a transmission. 406 407 Field set when coex_status_broadcast TLV received with WLAN 408 tx activity set and during WLAN tx 409 <legal all> 410 */ 411 412 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 413 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 10 414 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 10 415 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000400 416 417 418 /* Description COEX_WLAN_TX_WHILE_WLAN_RX 419 420 When set, a WLAN tx coex event started while wlan was in 421 the middle of TX a transmission. 422 423 Field set when coex broadcast TLV received with WLAN tx 424 activity set and during WLAN rx 425 <legal all> 426 */ 427 428 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 429 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 11 430 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 11 431 #define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000800 432 433 434 /* Description GLOBAL_DATA_UNDERFLOW_WARNING 435 436 Consumer: SCH/SW 437 Producer: TXPCU 438 439 When set, during transmission a data underflow occurred 440 for one or more users.<legal all> 441 */ 442 443 #define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 444 #define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 12 445 #define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 12 446 #define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000001000 447 448 449 /* Description GLOBAL_FES_TRANSMIT_RESULT 450 451 Consumer: SCH/SW 452 Producer: TXPCU 453 454 Global Transmit result, not per USER transmit result 455 456 Note: field "Response_type" indicates if the expected response 457 was MU related or not. 458 459 <enum 0 tx_ok> Successful transmission of entire Frame exchange 460 sequence 461 <enum 1 prot_resp_rx_timeout> 462 No Protection response frame received so timeout is triggered. 463 464 <enum 2 ppdu_resp_rx_timeout> No PPDU response frame received 465 so timeout is triggered. 466 <enum 3 resp_frame_crc_err> Response frame was received 467 with an invalid FCS. 468 <enum 4 SU_Response_type_mismatch> Response frame is received 469 without CRC error but it's not matched with expected SU_Response_type. 470 471 <enum 5 cbf_mimo_ctrl_mismatch> Set if CBF is received without 472 any error but the Nr, Nc, BW, type or token in VHT MIMO 473 control field is not matched with expected values which 474 are specified by TX_FES_SETUP.cbf_* fields. 475 <enum 7 MU_Response_type_mismatch> Response frame is received 476 without CRC error but it's not matched with expected SU_Response_type. 477 478 <enum 8 MU_Response_mpdu_not_valid> For this user, no MPDU 479 was received at all, or all received MPDUs had an FCS error. 480 481 <enum 9 MU_UL_not_enough_user_response> An MU UL response 482 reception was expected. That response came but the threshold 483 for number of successful user receptions was not met. 484 NOTE: This e-num will only be used in the TX_FES_STATUS_END 485 TLV... 486 <enum 10 Transmit_data_null_ratio_not_met> transmission 487 was successful and proper responses have been received. 488 But the required ratio between useful MPDU data and null 489 delimiters was not met as specified by field : Fes_continuation_ratio_threshold. 490 The FES (and potentially the SIFS burst) shall be terminated 491 by the SCHeduler 492 NOTE 1: This e-num will only be used in the TX_FES_STATUS_END 493 TLV... 494 NOTE 2: This Feature is not supported in Napier and Hastings. 495 496 <enum 6 TB_ranging_resp_timeout> A TB ranging response was 497 expected for a sounding TF, but the response did not arrive 498 and timeout is triggered. 499 NOTE: This e-num will only be used in the TX_FES_STATUS_END 500 TLV... 501 <enum 11 tb_ranging_resp_mismatch> A TB ranging response 502 was expected for a sounding TF, but the reception did not 503 match the expected response. 504 NOTE: This e-num will only be used in the TX_FES_STATUS_END 505 TLV... 506 507 <legal 0-11> 508 */ 509 510 #define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 511 #define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB 13 512 #define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB 16 513 #define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK 0x000000000001e000 514 515 516 /* Description CBF_BW_RECEIVED_VALID 517 518 Field only valid in case of SU reception. 519 In MU set to 0 520 521 When set, the cbf_bw_received field contains valid info 522 */ 523 524 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET 0x0000000000000000 525 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB 17 526 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB 17 527 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK 0x0000000000020000 528 529 530 /* Description CBF_BW_RECEIVED 531 532 Field only valid when cbf_bw_received_valid is set. 533 534 In MU set to 0 535 536 <enum 0 20_mhz>20 Mhz BW 537 <enum 1 40_mhz>40 Mhz BW 538 <enum 2 80_mhz>80 Mhz BW 539 <enum 3 160_mhz>160 Mhz BW 540 <enum 4 320_mhz>320 Mhz BW 541 <enum 5 240_mhz>240 Mhz BW 542 */ 543 544 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET 0x0000000000000000 545 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB 18 546 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB 20 547 #define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK 0x00000000001c0000 548 549 550 /* Description ACTUAL_RECEIVED_ACK_TYPE 551 552 Field only valid in case of SU reception. 553 In MU set to 0 554 555 556 Field indicates what type of ACK was received. Can help 557 determine if unexpected ACK Types (like 256 BA instead of 558 64 BA) is received. 559 560 <enum 0 Ack_not_applicable> No ACK type response was received 561 or expected 562 <enum 1 ACK_basic_received > a basic ACk frame is received 563 564 <enum 2 ACK_BA_0 > An ACK embedded in BA frame is received 565 566 <enum 3 ACK_BA_32_received > a 32 bit BA has been received 567 568 <enum 4 ACK_BA_64_received > a 64 bit BA has been received 569 570 <enum 5 ACK_BA_128_received > a 128 bit BA has been received 571 572 573 <enum 6 ACK_BA_256_received > a 256 bit BA has been received 574 575 <enum 8 ACK_BA_512_received> a 512-bit BA has been received 576 577 <enum 9 ACK_BA_1024_received> a 1024-bit BA has been received 578 579 <enum 7 ACK_BA_multiple_received > multiple BA responses 580 have been received. This field to be used in scenarios 581 where multi TID data was send or data with management frames 582 was send 583 584 <legal 0-9> 585 */ 586 587 #define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET 0x0000000000000000 588 #define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB 21 589 #define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB 24 590 #define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK 0x0000000001e00000 591 592 593 /* Description STA_RESPONSE_COUNT 594 595 In of case of a transmission where a response from multiple 596 STAs in SIFS time is expected, this field indicates how 597 many STAs actually send a response. 598 599 <legal 0-63> 600 */ 601 602 #define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET 0x0000000000000000 603 #define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB 25 604 #define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB 30 605 #define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK 0x000000007e000000 606 607 608 /* Description DPDTRAIN_DONE 609 610 Field only valid when PHYTX_PKT_END_info_valid is set 611 612 For DPD Training packets, this bit is set to indicate that 613 DPD Training was successfully run to completion. Also 614 reused by Implicit BF Calibration Packets. This bit is intended 615 for debug purposes. 616 <legal all> 617 */ 618 619 #define TX_FES_STATUS_END_DPDTRAIN_DONE_OFFSET 0x0000000000000000 620 #define TX_FES_STATUS_END_DPDTRAIN_DONE_LSB 31 621 #define TX_FES_STATUS_END_DPDTRAIN_DONE_MSB 31 622 #define TX_FES_STATUS_END_DPDTRAIN_DONE_MASK 0x0000000080000000 623 624 625 /* Description PHYTX_ABORT_REQUEST_INFO_DETAILS 626 627 Field only valid when PHYTX_ABORT_REQUEST_info_valid is 628 set 629 630 The reason why PHYTX is requested an abort 631 */ 632 633 634 /* Description PHYTX_ABORT_REASON 635 636 Reason for early termination of TX packet by the PHY 637 638 <enum_type PHYTX_ABORT_ENUM> 639 */ 640 641 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 642 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 643 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 644 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 645 646 647 /* Description USER_NUMBER 648 649 For some errors, the user for which this error was detected 650 can be indicated in this field. 651 <legal 0-36> 652 */ 653 654 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 655 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 656 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 657 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 658 659 660 /* Description RESERVED 661 662 <legal 0> 663 */ 664 665 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 666 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 667 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 668 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 669 670 671 /* Description RESERVED_AFTER_STRUCT16 672 673 <legal 0> 674 */ 675 676 #define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 677 #define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB 48 678 #define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB 51 679 #define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK 0x000f000000000000 680 681 682 /* Description BRP_INFO_VALID 683 684 When set, TXPCU sent CBF segments. 685 686 Fields cbf_segment_request_mask and cbf_segment_sent_mask 687 contain valid info. 688 689 <legal all> 690 */ 691 692 #define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET 0x0000000000000000 693 #define TX_FES_STATUS_END_BRP_INFO_VALID_LSB 52 694 #define TX_FES_STATUS_END_BRP_INFO_VALID_MSB 52 695 #define TX_FES_STATUS_END_BRP_INFO_VALID_MASK 0x0010000000000000 696 697 698 /* Description RESERVED_1A 699 700 <legal 0> 701 */ 702 703 #define TX_FES_STATUS_END_RESERVED_1A_OFFSET 0x0000000000000000 704 #define TX_FES_STATUS_END_RESERVED_1A_LSB 53 705 #define TX_FES_STATUS_END_RESERVED_1A_MSB 58 706 #define TX_FES_STATUS_END_RESERVED_1A_MASK 0x07e0000000000000 707 708 709 /* Description PHYTX_PKT_END_INFO_VALID 710 711 All the fields originating from PHYTX_PKT_END TLV contain 712 valid info 713 */ 714 715 #define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 716 #define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB 59 717 #define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB 59 718 #define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK 0x0800000000000000 719 720 721 /* Description PHYTX_ABORT_REQUEST_INFO_VALID 722 723 Field Phytx_abort_request_info_details contains valid info 724 725 */ 726 727 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 728 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 60 729 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 60 730 #define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x1000000000000000 731 732 733 /* Description FES_IN_11AX_TRIGGER_RESPONSE_CONFIG 734 735 When set, this transmission was the result of responding 736 to the reception of an 11ax trigger. This is a copy of 737 field Fes_in_11ax_Trigger_response_config in the TX_FES_SETUP 738 TLV. 739 <legal all> 740 */ 741 742 #define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 743 #define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 61 744 #define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 61 745 #define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x2000000000000000 746 747 748 /* Description NULL_DELIM_INSERTED_BEFORE_MPDUS 749 750 Field only valid when "Fes_in_11ax_Trigger_response_config" 751 is set. 752 753 This bit will get set if any NULL delimiter is sent out 754 to PHY, during the whole transmit duration(self_gen + FES). 755 756 This bit will NOT be set, if no MPDU data is sent out to 757 PHY and whole transmit duration is filled with NULL delimiters. 758 759 760 Note that SCH does not evaluate this field. It is only for 761 SW to look at. 762 763 <legal all> 764 */ 765 766 #define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET 0x0000000000000000 767 #define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB 62 768 #define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB 62 769 #define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK 0x4000000000000000 770 771 772 /* Description ONLY_NULL_DELIM_SENT 773 774 Field only valid when "Fes_in_11ax_Trigger_response_config" 775 is set. 776 777 This bit will be set if only NULL delimiters are sent to 778 the PHY and no SCH sourced MPDU data is sent out. 779 NOTE here that self-gen MPDU data will not be considered 780 while evaluating this bit. 781 782 Note that SCH does not evaluate this field. It is only for 783 SW to look at. 784 785 <legal all> 786 */ 787 788 #define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000000 789 #define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB 63 790 #define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB 63 791 #define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK 0x8000000000000000 792 793 794 /* Description START_OF_FRAME_TIMESTAMP_15_0 795 796 PHYTX_PKT_END info 797 798 Field only valid when PHYTX_PKT_END_info_valid is set 799 800 bits 15:0 of a 64 bit time stamp 801 Start of frame in the medium @960 MHz 802 <legal all> 803 */ 804 805 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 806 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 807 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 808 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff 809 810 811 /* Description START_OF_FRAME_TIMESTAMP_31_16 812 813 PHYTX_PKT_END info 814 815 Field only valid when PHYTX_PKT_END_info_valid is set 816 817 bits 31:16 of a 64 bit time stamp 818 Start of frame in the medium @960 MHz 819 <legal all> 820 */ 821 822 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 823 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 16 824 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 31 825 #define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 826 827 828 /* Description END_OF_FRAME_TIMESTAMP_15_0 829 830 PHYTX_PKT_END info 831 832 Field only valid when PHYTX_PKT_END_info_valid is set 833 834 bits 15:0 of a 64 bit time stamp 835 End of frame in the medium @960 MHz 836 <legal all> 837 */ 838 839 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 840 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 32 841 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 47 842 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 843 844 845 /* Description END_OF_FRAME_TIMESTAMP_31_16 846 847 PHYTX_PKT_END info 848 849 Field only valid when PHYTX_PKT_END_info_valid is set 850 851 bits 31:16 of a 64 bit time stamp 852 End of frame in the medium @960 MHz 853 <legal all> 854 */ 855 856 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 857 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 48 858 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 63 859 #define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 860 861 862 /* Description TERMINATE_RANGING_SEQUENCE 863 864 Consumer: SW/SCH 865 Producer: TXPCU 866 867 If set to 1, HWSCH will flush the TX pipeline and terminate 868 the ongoing SIFS sequence for TB Ranging. 869 870 TXPCU to set it only in the context of TB Ranging, when 871 the condition to terminate the TB Ranging sequence is met 872 873 874 <legal all> 875 */ 876 877 #define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_OFFSET 0x0000000000000010 878 #define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_LSB 0 879 #define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MSB 0 880 #define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MASK 0x0000000000000001 881 882 883 /* Description RESERVED_4A 884 885 <legal 0> 886 */ 887 888 #define TX_FES_STATUS_END_RESERVED_4A_OFFSET 0x0000000000000010 889 #define TX_FES_STATUS_END_RESERVED_4A_LSB 1 890 #define TX_FES_STATUS_END_RESERVED_4A_MSB 7 891 #define TX_FES_STATUS_END_RESERVED_4A_MASK 0x00000000000000fe 892 893 894 /* Description TIMING_STATUS 895 896 PHYTX_PKT_END info 897 898 Field only valid when PHYTX_PKT_END_info_valid is set 899 900 <enum 0 No_tx_timing_request> The MAC did not request for 901 the transmission to start at a particular time 902 <enum 1 successful_tx_timing > MAC did request for transmission 903 to start at a particular time and PHY was able to do so. 904 905 <enum 2 tx_timing_not_honoured> PHY was not able to honour 906 the requested transmit time by the MAC. The transmission 907 started later, and field transmit_delay indicates how much 908 later. 909 <legal 0-2> 910 */ 911 912 #define TX_FES_STATUS_END_TIMING_STATUS_OFFSET 0x0000000000000010 913 #define TX_FES_STATUS_END_TIMING_STATUS_LSB 8 914 #define TX_FES_STATUS_END_TIMING_STATUS_MSB 9 915 #define TX_FES_STATUS_END_TIMING_STATUS_MASK 0x0000000000000300 916 917 918 /* Description RESPONSE_TYPE 919 920 The response type that TXPCU was checking for 921 922 <enum 0 no_response_expected>After transmission of this 923 frame, no response in SIFS time is expected 924 925 When TXPCU sees this setting, it shall not generated the 926 EXPECTED_RESPONSE TLV. 927 928 RXPCU should never see this setting 929 <enum 1 ack_expected>An ACK frame is expected as response 930 931 932 RXPCU is just expecting any response. It is TXPCU who checks 933 that the right response was received. 934 <enum 2 ba_64_bitmap_expected>BA with 64 bitmap is expected. 935 936 937 PDG DOES NOT use the size info to calculated response duration. 938 The length of the response will have to be programmed by 939 SW in the per-BW 'Expected_ppdu_resp_length' field. 940 941 For TXPCU only the fact that it is a BA is important. Actual 942 received BA size is not important 943 944 RXPCU is just expecting any response. It is TXPCU who checks 945 that the right response was received. 946 <enum 3 ba_256_expected>BA with 256 bitmap is expected. 947 948 PDG DOES NOT use the size info to calculated response duration. 949 The length of the response will have to be programmed by 950 SW in the per-BW 'Expected_ppdu_resp_length' field. 951 952 For TXPCU only the fact that it is a BA is important. Actual 953 received BA size is not important 954 955 RXPCU is just expecting any response. It is TXPCU who checks 956 that the right response was received. 957 <enum 4 actionnoack_expected>SW sets this after sending 958 NDP or BR-Poll. 959 960 As PDG has no idea on how long the reception is going to 961 be, the reception time of the response will have to be 962 programmed by SW in the 'Extend_duration_value_bw...' field 963 964 965 RXPCU is just expecting any response. It is TXPCU who checks 966 that the right response was received. 967 <enum 5 ack_ba_expected>PDG uses the size info and assumes 968 single BA format with ACK and 64 bitmap embedded. 969 If SW expects more bitmaps in case of multi-TID, is shall 970 program the 'Extend_duration_value_bw...' field for additional 971 duration time. 972 For TXPCU only the fact that an ACK and/or BA is received 973 is important. Reception of only ACK or BA is also considered 974 a success. 975 SW also typically sets this when sending VHT single MPDU. 976 Some chip vendors might send BA rather than ACK in response 977 to VHT single MPDU but still we want to accept BA as well. 978 979 980 RXPCU is just expecting any response. It is TXPCU who checks 981 that the right response was received. 982 <enum 6 cts_expected>SW sets this after queuing RTS frame 983 as standalone packet and sending it. 984 985 RXPCU is just expecting any response. It is TXPCU who checks 986 that the right response was received. 987 <enum 7 ack_data_expected>SW sets this after sending PS-Poll. 988 989 990 For TXPCU either ACK and/or data reception is considered 991 success. 992 PDG basis it's response duration calculation on an ACK. 993 For the data portion, SW shall program the 'Extend_duration_value_bw...' 994 field 995 <enum 8 ndp_ack_expected>Reserved for 11ah usage. 996 <enum 9 ndp_modified_ack>Reserved for 11ah usage 997 <enum 10 ndp_ba_expected>Reserved for 11ah usage. 998 <enum 11 ndp_cts_expected>Reserved for 11ah usage 999 <enum 12 ndp_ack_or_ndp_modified_ack_expected>Reserved for 1000 11ah usage 1001 <enum 13 ul_mu_ba_expected>NOT SUPPORTED IN NAPIER AX AND 1002 HASTINGS 1003 1004 TXPCU expects UL MU OFDMA or UL MU MIMO reception. 1005 As PDG does not know how RUs are assigned for the uplink 1006 portion, PDG can not calculate the uplink duration. Therefor 1007 SW shall program the 'Extend_duration_value_bw...' field 1008 1009 1010 RXPCU will report any frame received, irrespective of it 1011 having been UL MU or SU It is TXPCUs responsibility to 1012 distinguish between the UL MU or SU 1013 1014 TXPCU can check in TLV RECEIVED_RESPONSE_INFO MU_Response_BA_bitmap 1015 if indeed BA was received 1016 <enum 14 ul_mu_ba_and_data_expected>NOT SUPPORTED IN NAPIER 1017 AX AND HASTINGS 1018 1019 TXPCU expects UL MU OFDMA or UL MU MIMO reception. 1020 As PDG does not know how RUs are assigned for the uplink 1021 portion, PDG can not calculate the uplink duration. Therefor 1022 SW shall program the 'Extend_duration_value_bw...' field 1023 1024 1025 RXPCU will report any frame received, irrespective of it 1026 having been UL MU or SU It is TXPCUs responsibility to 1027 distinguish between the UL MU or SU 1028 1029 TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_data_bitmap 1030 and MU_Response_BA_bitmap if indeed BA and data was received 1031 1032 <enum 15 ul_mu_cbf_expected>NOT SUPPORTED IN NAPIER AX AND 1033 HASTINGS 1034 1035 When selected, CBF frames are expected to be received in 1036 MU reception (uplink OFDMA or uplink MIMO) 1037 1038 RXPCU is just expecting any response. It is TXPCU who checks 1039 that the right response was received 1040 TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_cbf_bitmap 1041 if indeed CBF frames were received. 1042 <enum 16 ul_mu_frames_expected>When selected, MPDU frames 1043 are expected in the MU reception (uplink OFDMA or uplink 1044 MIMO) 1045 1046 RXPCU is just expecting any response. It is TXPCU who checks 1047 that the right response was received 1048 1049 TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_bitmap 1050 if indeed frames were received. 1051 <enum 17 any_response_to_this_device>Any response expected 1052 to be send to this device in SIFS time is acceptable. 1053 1054 RXPCU is just expecting any response. It is TXPCU who checks 1055 that the right response was received 1056 1057 For TXPCU, UL MU or SU is both acceptable. 1058 1059 Can be used for complex OFDMA scenarios. PDG can not calculate 1060 the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' 1061 field 1062 <enum 18 any_response_accepted>Any frame in the medium to 1063 this or any other device, is acceptable as response. 1064 RXPCU is just expecting any response. It is TXPCU who checks 1065 that the right response was received 1066 1067 For TXPCU, UL MU or SU is both acceptable. 1068 1069 Can be used for complex OFDMA scenarios. PDG can not calculate 1070 the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' 1071 field 1072 <enum 19 frameless_phyrx_response_accepted>Any MU frameless 1073 reception generated by the PHY is acceptable. 1074 1075 PHY indicates this type of reception explicitly in TLV PHYRX_RSSI_LEGACY, 1076 field Reception_type == reception_is_frameless 1077 1078 RXPCU will report any frame received, irrespective of it 1079 having been UL MU or SU. 1080 1081 This can be used for complex MU-MIMO or OFDMA scenarios, 1082 like receiving MU-CTS. 1083 1084 PDG can not calculate the uplink duration. Therefor SW shall 1085 program the 'Extend_duration_value_bw...' field 1086 <enum 20 ranging_ndp_and_lmr_expected>SW sets this after 1087 sending ranging NDPA followed by NDP as an ISTA and NDP 1088 and LMR (Action No Ack) are expected as back-to-back reception 1089 in SIFS. 1090 1091 As PDG has no idea on how long the reception is going to 1092 be, the reception time of the response will have to be 1093 programmed by SW in the 'Extend_duration_value_bw...' field 1094 1095 1096 RXPCU is just expecting any response. It is TXPCU who checks 1097 that the right response was received. 1098 <enum 21 ba_512_expected>BA with 512 bitmap is expected. 1099 1100 1101 PDG DOES NOT use the size info to calculated response duration. 1102 The length of the response will have to be programmed by 1103 SW in the per-BW 'Expected_ppdu_resp_length' field. 1104 1105 For TXPCU only the fact that it is a BA is important. Actual 1106 received BA size is not important 1107 1108 RXPCU is just expecting any response. It is TXPCU who checks 1109 that the right response was received. 1110 <enum 22 ba_1024_expected>BA with 1024 bitmap is expected. 1111 1112 1113 PDG DOES NOT use the size info to calculated response duration. 1114 The length of the response will have to be programmed by 1115 SW in the per-BW 'Expected_ppdu_resp_length' field. 1116 1117 For TXPCU only the fact that it is a BA is important. Actual 1118 received BA size is not important 1119 1120 RXPCU is just expecting any response. It is TXPCU who checks 1121 that the right response was received. 1122 <enum 23 ul_mu_ranging_cts2s_expected>When selected, CTS2S 1123 frames are expected to be received in MU reception (uplink 1124 OFDMA) 1125 1126 RXPCU shall check each response for CTS2S and report to 1127 TXPCU. 1128 1129 TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields 1130 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed CTS2S 1131 frames were received. 1132 <enum 24 ul_mu_ranging_ndp_expected>When selected, UL NDP 1133 frames are expected to be received in MU reception (uplink 1134 spatial multiplexing) 1135 1136 RXPCU shall check each response for NDP and report to TXPCU. 1137 1138 1139 TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields 1140 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed NDP 1141 frames were received. 1142 <enum 25 ul_mu_ranging_lmr_expected>When selected, LMR frames 1143 are expected to be received in MU reception (uplink OFDMA 1144 or uplink MIMO) 1145 1146 RXPCU shall check each response for LMR and report to TXPCU. 1147 1148 1149 TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields 1150 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed LMR 1151 frames were received. 1152 */ 1153 1154 #define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET 0x0000000000000010 1155 #define TX_FES_STATUS_END_RESPONSE_TYPE_LSB 10 1156 #define TX_FES_STATUS_END_RESPONSE_TYPE_MSB 14 1157 #define TX_FES_STATUS_END_RESPONSE_TYPE_MASK 0x0000000000007c00 1158 1159 1160 /* Description R2R_END_STATUS_TO_FOLLOW 1161 1162 When set, TXPCU will still generate an R2R frame (typically 1163 M-BA), and the 'R2R_STATUS_END' TLV. 1164 <legal all> 1165 */ 1166 1167 #define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000010 1168 #define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB 15 1169 #define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB 15 1170 #define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000000008000 1171 1172 1173 /* Description TRANSMIT_DELAY 1174 1175 PHYTX_PKT_END info 1176 1177 Field only valid when PHYTX_PKT_END_info_valid is set 1178 1179 The number of 480 MHz clock cycles that the transmission 1180 started after the actual requested transmit start time. 1181 1182 Value saturates at 0xFFFF 1183 <legal all> 1184 */ 1185 1186 #define TX_FES_STATUS_END_TRANSMIT_DELAY_OFFSET 0x0000000000000010 1187 #define TX_FES_STATUS_END_TRANSMIT_DELAY_LSB 16 1188 #define TX_FES_STATUS_END_TRANSMIT_DELAY_MSB 31 1189 #define TX_FES_STATUS_END_TRANSMIT_DELAY_MASK 0x00000000ffff0000 1190 1191 1192 /* Description TX_GROUP_DELAY 1193 1194 PHYTX_PKT_END info 1195 1196 Field only valid when PHYTX_PKT_END_info_valid is set 1197 1198 Group delay on TxTD+PHYRF path for this PPDU (packet BW 1199 dependent), useful for RTT 1200 1201 Unit is 960MHz cycles. 1202 <legal all> 1203 */ 1204 1205 #define TX_FES_STATUS_END_TX_GROUP_DELAY_OFFSET 0x0000000000000010 1206 #define TX_FES_STATUS_END_TX_GROUP_DELAY_LSB 32 1207 #define TX_FES_STATUS_END_TX_GROUP_DELAY_MSB 43 1208 #define TX_FES_STATUS_END_TX_GROUP_DELAY_MASK 0x00000fff00000000 1209 1210 1211 /* Description RESERVED_5A 1212 1213 Bits [14:12]: service_cbw: 1214 1215 Field only valid when a response was received 1216 1217 Source of the info here is the 'RECEIVED_RESPONSE_INFO' 1218 TLV 1219 1220 This field reflects the BW extracted from the Serivce Field 1221 for 11ac mode of operation . 1222 1223 This field is used in the context of Dynamic BW evaluation 1224 purposes in SCH in case of SW-queued protection frame. 1225 1226 Please refer 'BW_ENUM' e-num for the values used. 1227 <legal 0-5> 1228 */ 1229 1230 #define TX_FES_STATUS_END_RESERVED_5A_OFFSET 0x0000000000000010 1231 #define TX_FES_STATUS_END_RESERVED_5A_LSB 44 1232 #define TX_FES_STATUS_END_RESERVED_5A_MSB 47 1233 #define TX_FES_STATUS_END_RESERVED_5A_MASK 0x0000f00000000000 1234 1235 1236 /* Description TPC_DBG_INFO_CMN_15_0 1237 1238 PHYTX_PKT_END info 1239 1240 Field only valid when PHYTX_PKT_END_info_valid is set 1241 1242 Some TPC debug info that PHY can pass back to MAC FW 1243 <legal all> 1244 */ 1245 1246 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000010 1247 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_LSB 48 1248 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_MSB 63 1249 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_MASK 0xffff000000000000 1250 1251 1252 /* Description TPC_DBG_INFO_CMN_31_16 1253 1254 PHYTX_PKT_END info 1255 1256 Field only valid when PHYTX_PKT_END_info_valid is set 1257 1258 Some TPC debug info that PHY can pass back to MAC FW 1259 <legal all> 1260 */ 1261 1262 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000000000018 1263 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_LSB 0 1264 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_MSB 15 1265 #define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_MASK 0x000000000000ffff 1266 1267 1268 /* Description TPC_DBG_INFO_47_32 1269 1270 PHYTX_PKT_END info 1271 1272 Field only valid when PHYTX_PKT_END_info_valid is set 1273 1274 Some TPC debu info that PHY can pass back to MAC FW 1275 <legal all> 1276 */ 1277 1278 #define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_OFFSET 0x0000000000000018 1279 #define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_LSB 16 1280 #define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_MSB 31 1281 #define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_MASK 0x00000000ffff0000 1282 1283 1284 /* Description TPC_DBG_INFO_CHN1_15_0 1285 1286 PHYTX_PKT_END info 1287 1288 Field only valid when PHYTX_PKT_END_info_valid is set 1289 1290 Some per-chain TPC debug info for the first selected chain 1291 that PHY can pass back to MAC FW 1292 <legal all> 1293 */ 1294 1295 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000018 1296 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_LSB 32 1297 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_MSB 47 1298 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff00000000 1299 1300 1301 /* Description TPC_DBG_INFO_CHN1_31_16 1302 1303 PHYTX_PKT_END info 1304 1305 Field only valid when PHYTX_PKT_END_info_valid is set 1306 1307 Some per-chain TPC debug info for the first selected chain 1308 that PHY can pass back to MAC FW 1309 <legal all> 1310 */ 1311 1312 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000018 1313 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_LSB 48 1314 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_MSB 63 1315 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_MASK 0xffff000000000000 1316 1317 1318 /* Description TPC_DBG_INFO_CHN1_47_32 1319 1320 PHYTX_PKT_END info 1321 1322 Field only valid when PHYTX_PKT_END_info_valid is set 1323 1324 Some per-chain TPC debug info for the first selected chain 1325 that PHY can pass back to MAC FW 1326 <legal all> 1327 */ 1328 1329 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000020 1330 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_LSB 0 1331 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_MSB 15 1332 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x000000000000ffff 1333 1334 1335 /* Description TPC_DBG_INFO_CHN1_63_48 1336 1337 PHYTX_PKT_END info 1338 1339 Field only valid when PHYTX_PKT_END_info_valid is set 1340 1341 Some per-chain TPC debug info for the first selected chain 1342 that PHY can pass back to MAC FW 1343 <legal all> 1344 */ 1345 1346 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000020 1347 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_LSB 16 1348 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_MSB 31 1349 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x00000000ffff0000 1350 1351 1352 /* Description TPC_DBG_INFO_CHN1_79_64 1353 1354 PHYTX_PKT_END info 1355 1356 Field only valid when PHYTX_PKT_END_info_valid is set 1357 1358 Some per-chain TPC debug info for the first selected chain 1359 that PHY can pass back to MAC FW 1360 <legal all> 1361 */ 1362 1363 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000020 1364 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_LSB 32 1365 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_MSB 47 1366 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff00000000 1367 1368 1369 /* Description TPC_DBG_INFO_CHN2_15_0 1370 1371 PHYTX_PKT_END info 1372 1373 Field only valid when PHYTX_PKT_END_info_valid is set 1374 1375 Some per-chain TPC debug info for the second selected chain 1376 that PHY can pass back to MAC FW 1377 <legal all> 1378 */ 1379 1380 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000020 1381 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_LSB 48 1382 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_MSB 63 1383 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_MASK 0xffff000000000000 1384 1385 1386 /* Description TPC_DBG_INFO_CHN2_31_16 1387 1388 PHYTX_PKT_END info 1389 1390 Field only valid when PHYTX_PKT_END_info_valid is set 1391 1392 Some per-chain TPC debug info for the second selected chain 1393 that PHY can pass back to MAC FW 1394 <legal all> 1395 */ 1396 1397 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000028 1398 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_LSB 0 1399 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_MSB 15 1400 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x000000000000ffff 1401 1402 1403 /* Description TPC_DBG_INFO_CHN2_47_32 1404 1405 PHYTX_PKT_END info 1406 1407 Field only valid when PHYTX_PKT_END_info_valid is set 1408 1409 Some per-chain TPC debug info for the second selected chain 1410 that PHY can pass back to MAC FW 1411 <legal all> 1412 */ 1413 1414 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000028 1415 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_LSB 16 1416 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_MSB 31 1417 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x00000000ffff0000 1418 1419 1420 /* Description TPC_DBG_INFO_CHN2_63_48 1421 1422 PHYTX_PKT_END info 1423 1424 Field only valid when PHYTX_PKT_END_info_valid is set 1425 1426 Some per-chain TPC debug info for the second selected chain 1427 that PHY can pass back to MAC FW 1428 <legal all> 1429 */ 1430 1431 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000028 1432 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_LSB 32 1433 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_MSB 47 1434 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff00000000 1435 1436 1437 /* Description TPC_DBG_INFO_CHN2_79_64 1438 1439 PHYTX_PKT_END info 1440 1441 Field only valid when PHYTX_PKT_END_info_valid is set 1442 1443 Some per-chain TPC debug info for the second selected chain 1444 that PHY can pass back to MAC FW 1445 <legal all> 1446 */ 1447 1448 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000028 1449 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_LSB 48 1450 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_MSB 63 1451 #define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_MASK 0xffff000000000000 1452 1453 1454 /* Description PHYTX_TX_END_SW_INFO_15_0 1455 1456 PHYTX_PKT_END info 1457 1458 Field only valid when PHYTX_PKT_END_info_valid is set 1459 1460 Some PHY status data that PHY microcode can pass back to 1461 MAC FW, for any future requests, e.g. any DMA download 1462 time 1463 <legal all> 1464 */ 1465 1466 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000030 1467 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0 1468 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15 1469 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff 1470 1471 1472 /* Description PHYTX_TX_END_SW_INFO_31_16 1473 1474 PHYTX_PKT_END info 1475 1476 Field only valid when PHYTX_PKT_END_info_valid is set 1477 1478 Some PHY status data that PHY microcode can pass back to 1479 MAC FW, for any future requests, e.g. any DMA download 1480 time 1481 <legal all> 1482 */ 1483 1484 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000030 1485 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_LSB 16 1486 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_MSB 31 1487 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 1488 1489 1490 /* Description PHYTX_TX_END_SW_INFO_47_32 1491 1492 PHYTX_PKT_END info 1493 1494 Field only valid when PHYTX_PKT_END_info_valid is set 1495 1496 Some PHY status data that PHY microcode can pass back to 1497 MAC FW, for any future requests, e.g. any DMA download 1498 time 1499 <legal all> 1500 */ 1501 1502 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000030 1503 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_LSB 32 1504 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_MSB 47 1505 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 1506 1507 1508 /* Description PHYTX_TX_END_SW_INFO_63_48 1509 1510 PHYTX_PKT_END info 1511 1512 Field only valid when PHYTX_PKT_END_info_valid is set 1513 1514 Some PHY status data that PHY microcode can pass back to 1515 MAC FW, for any future requests, e.g. any DMA download 1516 time 1517 <legal all> 1518 */ 1519 1520 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000030 1521 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_LSB 48 1522 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_MSB 63 1523 #define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 1524 1525 1526 /* Description BEAMFORM_MASKED_USER_BITMAP_15_0 1527 1528 Lower 16 bits of 'Beamform_masked_user_bitmap' 1529 1530 PHY indicates in this field for which users it actually 1531 did not beamform it's transmission even though this was 1532 requested 1533 1534 Bit 0: user 0, bit 1: user 1, etc. 1535 1536 When 0: No beamform issue for this user 1537 When 1: PHY could not beamform for this user, but did not 1538 terminate the transmission 1539 1540 <legal all> 1541 */ 1542 1543 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000000000000038 1544 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0 1545 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15 1546 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x000000000000ffff 1547 1548 1549 /* Description BEAMFORM_MASKED_USER_BITMAP_31_16 1550 1551 Middle 16 bits of 'Beamform_masked_user_bitmap' 1552 See description above. 1553 <legal all> 1554 */ 1555 1556 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x0000000000000038 1557 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 16 1558 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 31 1559 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x00000000ffff0000 1560 1561 1562 /* Description CBF_SEGMENT_REQUEST_MASK 1563 1564 Field only valid when brp_info_valid is set. 1565 1566 Field equal to the 'Feedback Segment Retransmission Bitmap' 1567 from the Beamform Report Poll frame OR Beamform Report Poll 1568 Trigger frame 1569 1570 Bit 0 represents segment 0 1571 Bit 1 represents segment 1 1572 Etc. 1573 1574 1'b1: Segment is requested 1575 1'b0: Segment is NOT requested 1576 1577 <legal all> 1578 */ 1579 1580 #define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000038 1581 #define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB 32 1582 #define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB 39 1583 #define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK 0x000000ff00000000 1584 1585 1586 /* Description CBF_SEGMENT_SENT_MASK 1587 1588 Field only valid when brp_info_valid is set. 1589 1590 Bit 0 represents segment 0 1591 Bit 1 represents segment 1 1592 Etc. 1593 1594 1'b1: Segment is sent 1595 1'b0: Segment is not sent 1596 1597 <legal all> 1598 */ 1599 1600 #define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000038 1601 #define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB 40 1602 #define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB 47 1603 #define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK 0x0000ff0000000000 1604 1605 1606 /* Description HIGHEST_ACHIEVED_DATA_NULL_RATIO 1607 1608 Highest DATA:NULL ratio achieved for the current FES 1609 1610 <enum 0 No_Data_Null_ratio_requirement> There was no Data:NULL 1611 ratio established. 1612 <enum 1 Data_Null_ratio_16_1> Best Data:NULL ratio was 16:1. 1613 1614 <enum 2 Data_Null_ratio_8_1> Best Data:NULL ratio was 8:1. 1615 1616 <enum 3 Data_Null_ratio_4_1> Best Data:NULL ratio was 4:1. 1617 1618 <enum 4 Data_Null_ratio_2_1> Best Data:NULL ratio was 2:1. 1619 1620 <enum 5 Data_Null_ratio_1_1> Best Data:NULL ratio was 1:1. 1621 1622 terminate FES. 1623 <enum 6 Data_Null_ratio_1_2> Best Data:NULL ratio was 1:2. 1624 1625 <enum 7 Data_Null_ratio_1_4> Best Data:NULL ratio was 1:4. 1626 1627 <enum 8 Data_Null_ratio_1_8> Best Data:NULL ratio was 1:8. 1628 1629 <enum 9 Data_Null_ratio_1_16> Best Data:NULL ratio was 1:16. 1630 1631 1632 <legal 0-9> 1633 */ 1634 1635 #define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET 0x0000000000000038 1636 #define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB 48 1637 #define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB 52 1638 #define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK 0x001f000000000000 1639 1640 1641 /* Description USE_ALT_POWER_SR 1642 1643 0: Primary/default power1: Alternate power 1644 <legal all> 1645 */ 1646 1647 #define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET 0x0000000000000038 1648 #define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB 53 1649 #define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB 53 1650 #define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK 0x0020000000000000 1651 1652 1653 /* Description STATIC_2_PWR_MODE_STATUS 1654 1655 0: Static 2 power mode disabled1: Static 2 power mode enabled 1656 1657 <legal all> 1658 */ 1659 1660 #define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000038 1661 #define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB 54 1662 #define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB 54 1663 #define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK 0x0040000000000000 1664 1665 1666 /* Description OBSS_SRG_OPPORT_TRANSMIT_STATUS 1667 1668 0: Transmit based on SRG OBSS_PD opportunity initiated1: 1669 Transmit based on non-SRG OBSS_PD opportunity initiated 1670 <legal all> 1671 */ 1672 1673 #define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000038 1674 #define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 55 1675 #define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 55 1676 #define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0080000000000000 1677 1678 1679 /* Description SRP_BASED_TRANSMIT_STATUS 1680 1681 0: non-SRP based transmit initiated1: SRP based transmit 1682 initiated 1683 <legal all> 1684 */ 1685 1686 #define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000038 1687 #define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB 56 1688 #define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB 56 1689 #define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK 0x0100000000000000 1690 1691 1692 /* Description OBSS_PD_BASED_TRANSMIT_STATUS 1693 1694 0: non-OBSS_PD based transmit initiated1: obss_pd based 1695 transmit initiated 1696 <legal all> 1697 */ 1698 1699 #define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000038 1700 #define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 57 1701 #define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 57 1702 #define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0200000000000000 1703 1704 1705 /* Description BEAMFORM_MASKED_USER_BITMAP_36_32 1706 1707 Upper 5 bits of 'Beamform_masked_user_bitmap' 1708 See description above. 1709 <legal all> 1710 */ 1711 1712 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x0000000000000038 1713 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 58 1714 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 62 1715 #define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x7c00000000000000 1716 1717 1718 /* Description PDG_MPDU_READY 1719 1720 Field only valid in case of SU transmissions, copied over 1721 by TXPCU from 'PCU_PPDU_SETUP_END' 1722 1723 Indicates the 'MPDU_INFO' or 'MPDU_QUEUE_OVERVIEW' ready 1724 status in PDG. 1725 <legal all> 1726 */ 1727 1728 #define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET 0x0000000000000038 1729 #define TX_FES_STATUS_END_PDG_MPDU_READY_LSB 63 1730 #define TX_FES_STATUS_END_PDG_MPDU_READY_MSB 63 1731 #define TX_FES_STATUS_END_PDG_MPDU_READY_MASK 0x8000000000000000 1732 1733 1734 /* Description PDG_MPDU_COUNT 1735 1736 Field only valid in case of SU transmissions when pdg_MPDU_ready 1737 is set, copied over by TXPCU from 'PCU_PPDU_SETUP_END' 1738 1739 Total MPDU count from 'MPDU_INFO' or 'MPDU_QUEUE_OVERVIEW' 1740 1741 <legal 0-2130> 1742 */ 1743 1744 #define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET 0x0000000000000040 1745 #define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB 0 1746 #define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB 15 1747 #define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK 0x000000000000ffff 1748 1749 1750 /* Description PDG_EST_MPDU_TX_COUNT 1751 1752 Field only valid in case of SU transmissions when pdg_MPDU_ready 1753 is set, copied over by TXPCU from 'PCU_PPDU_SETUP_END' 1754 1755 PDG estimated MPDU Tx count from 'MPDU_INFO' or 'MPDU_QUEUE_OVERVIEW' 1756 limited by timing boundaries (HWSCH, COEX, SR, etc.) 1757 <legal 0-1024> 1758 */ 1759 1760 #define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET 0x0000000000000040 1761 #define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB 16 1762 #define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB 31 1763 #define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK 0x00000000ffff0000 1764 1765 1766 /* Description PDG_OVERVIEW_LENGTH 1767 1768 Field only valid in case of SU transmissions when pdg_MPDU_ready 1769 is set, copied over by TXPCU from 'PCU_PPDU_SETUP_END' 1770 1771 PDG estimated A-MPDU length from 'MPDU_QUEUE_OVERVIEW' limited 1772 by timing boundaries (HWSCH, COEX, SR, etc.) 1773 <legal all> 1774 */ 1775 1776 #define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET 0x0000000000000040 1777 #define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB 32 1778 #define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB 55 1779 #define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK 0x00ffffff00000000 1780 1781 1782 /* Description TXOP_DURATION 1783 1784 TXOP_DURATION of HE-SIG-A calculated by PDG, to be copied 1785 from 'PCU_PPDU_SETUP_END' by TXPCU 1786 */ 1787 1788 #define TX_FES_STATUS_END_TXOP_DURATION_OFFSET 0x0000000000000040 1789 #define TX_FES_STATUS_END_TXOP_DURATION_LSB 56 1790 #define TX_FES_STATUS_END_TXOP_DURATION_MSB 62 1791 #define TX_FES_STATUS_END_TXOP_DURATION_MASK 0x7f00000000000000 1792 1793 1794 /* Description PDG_DROPPED_MPDU_WARNING 1795 1796 Warning that PDG has dropped MPDUs due to SFM FIFO full 1797 condition, to be copied from 'PCU_PPDU_SETUP_END' by TXPCU 1798 1799 */ 1800 1801 #define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000040 1802 #define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB 63 1803 #define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB 63 1804 #define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK 0x8000000000000000 1805 1806 1807 /* Description PACKET_EXTENSION_A_FACTOR 1808 1809 The "a-factor" of the trigger-based PPDU response, to be 1810 copied from 'PCU_PPDU_SETUP_END' by TXPCU 1811 1812 This affects the packet extension duration. 1813 1814 <enum 0 a_factor_4> 1815 <enum 1 a_factor_1> 1816 <enum 2 a_factor_2> 1817 <enum 3 a_factor_3> 1818 1819 <legal all> 1820 */ 1821 1822 #define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000048 1823 #define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB 0 1824 #define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB 1 1825 #define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 1826 1827 1828 /* Description PACKET_EXTENSION_PE_DISAMBIGUITY 1829 1830 The "PE-Disambiguity" of the trigger-based PPDU response, 1831 to be copied from 'PCU_PPDU_SETUP_END' by TXPCU 1832 1833 This affects the packet extension duration. 1834 1835 <legal all> 1836 */ 1837 1838 #define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000048 1839 #define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 1840 #define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 1841 #define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 1842 1843 1844 /* Description PACKET_EXTENSION 1845 1846 Packet extension size, to be copied from 'PCU_PPDU_SETUP_END' 1847 by TXPCU 1848 1849 This is valid for all PPDUs including HE-Ranging NDPs (11az) 1850 and Short-NDPs. 1851 1852 <enum 0 packet_ext_0> 1853 <enum 1 packet_ext_4> 1854 <enum 2 packet_ext_8> 1855 <enum 3 packet_ext_12> 1856 <enum 4 packet_ext_16> 1857 <enum 5 packet_ext_20> 1858 <legal 0 - 5> 1859 */ 1860 1861 #define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET 0x0000000000000048 1862 #define TX_FES_STATUS_END_PACKET_EXTENSION_LSB 3 1863 #define TX_FES_STATUS_END_PACKET_EXTENSION_MSB 5 1864 #define TX_FES_STATUS_END_PACKET_EXTENSION_MASK 0x0000000000000038 1865 1866 1867 /* Description FEC_TYPE 1868 1869 For trigger-based PPDU response, to be copied from 'PCU_PPDU_SETUP_END' 1870 by TXPCU 1871 0: BCC 1872 1: LDPC 1873 <legal all> 1874 */ 1875 1876 #define TX_FES_STATUS_END_FEC_TYPE_OFFSET 0x0000000000000048 1877 #define TX_FES_STATUS_END_FEC_TYPE_LSB 6 1878 #define TX_FES_STATUS_END_FEC_TYPE_MSB 6 1879 #define TX_FES_STATUS_END_FEC_TYPE_MASK 0x0000000000000040 1880 1881 1882 /* Description STBC 1883 1884 For trigger-based PPDU response, to be copied from 'PCU_PPDU_SETUP_END' 1885 by TXPCU 1886 1887 When set, this transmission is based on STBC rates. 1888 */ 1889 1890 #define TX_FES_STATUS_END_STBC_OFFSET 0x0000000000000048 1891 #define TX_FES_STATUS_END_STBC_LSB 7 1892 #define TX_FES_STATUS_END_STBC_MSB 7 1893 #define TX_FES_STATUS_END_STBC_MASK 0x0000000000000080 1894 1895 1896 /* Description NUM_DATA_SYMBOLS 1897 1898 The number of data symbols in the transmission, to be copied 1899 from 'PCU_PPDU_SETUP_END' by TXPCU 1900 1901 This does not include PE_LTF. Also for STBC packets this 1902 has to be an even number. This is valid for all PPDUs. 1903 */ 1904 1905 #define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000048 1906 #define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB 8 1907 #define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB 23 1908 #define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK 0x0000000000ffff00 1909 1910 1911 /* Description RU_SIZE 1912 1913 The size of the RU for this user, for trigger-based PPDU 1914 response, to be copied from 'PCU_PPDU_SETUP_END' by TXPCU 1915 1916 1917 <enum 0 RU_26> 1918 <enum 1 RU_52> 1919 <enum 2 RU_106> 1920 <enum 3 RU_242> 1921 <enum 4 RU_484> 1922 <enum 5 RU_996> 1923 <enum 6 RU_1992> 1924 <enum 7 RU_FULLBW> Set when the RU occupies the full packet 1925 bandwidth 1926 <enum 8 RU_FULLBW_240> Set when the RU occupies the full 1927 packet bandwidth 1928 <enum 9 RU_FULLBW_320> Set when the RU occupies the full 1929 packet bandwidth 1930 <enum 10 RU_MULTI_LARGE> HW will use per-user sub-band-mask 1931 to infer the actual RU-size for Multi-large-RU/SU-Puncturing 1932 1933 <enum 11 RU_78> multi small RU 1934 <enum 12 RU_132> multi small RU 1935 <legal 0-12> 1936 */ 1937 1938 #define TX_FES_STATUS_END_RU_SIZE_OFFSET 0x0000000000000048 1939 #define TX_FES_STATUS_END_RU_SIZE_LSB 24 1940 #define TX_FES_STATUS_END_RU_SIZE_MSB 27 1941 #define TX_FES_STATUS_END_RU_SIZE_MASK 0x000000000f000000 1942 1943 1944 /* Description RESERVED_17A 1945 1946 Hamilton v1 used this for 'Nss' for trigger-based PPDU response. 1947 1948 <legal 0> 1949 */ 1950 1951 #define TX_FES_STATUS_END_RESERVED_17A_OFFSET 0x0000000000000048 1952 #define TX_FES_STATUS_END_RESERVED_17A_LSB 28 1953 #define TX_FES_STATUS_END_RESERVED_17A_MSB 31 1954 #define TX_FES_STATUS_END_RESERVED_17A_MASK 0x00000000f0000000 1955 1956 1957 /* Description NUM_LTF_SYMBOLS 1958 1959 Indicates the number of HE-LTF symbols, for trigger-based 1960 PPDU response, to be copied from 'PCU_PPDU_SETUP_END' by 1961 TXPCU 1962 1963 0: 1 symbol 1964 1: 2 symbols 1965 2: 3 symbols 1966 3: 4 symbols 1967 4: 5 symbols 1968 5: 6 symbols 1969 6: 7 symbols 1970 7: 8 symbols 1971 1972 NOTE that this encoding is different from what is in "Num_LTF_symbols" 1973 in the HE_SIG_A_MU_DL. 1974 <legal all> 1975 */ 1976 1977 #define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000048 1978 #define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB 32 1979 #define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB 34 1980 #define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 1981 1982 1983 /* Description LTF_SIZE 1984 1985 Ltf size, to be copied from 'PCU_PPDU_SETUP_END' by TXPCU 1986 1987 1988 This is valid for all PPDUs including HE-Ranging NDPs (11az) 1989 and Short-NDPs. 1990 1991 <enum 0 ltf_1x > 1992 <enum 1 ltf_2x > 1993 <enum 2 ltf_4x > 1994 <legal 0 - 2> 1995 */ 1996 1997 #define TX_FES_STATUS_END_LTF_SIZE_OFFSET 0x0000000000000048 1998 #define TX_FES_STATUS_END_LTF_SIZE_LSB 35 1999 #define TX_FES_STATUS_END_LTF_SIZE_MSB 36 2000 #define TX_FES_STATUS_END_LTF_SIZE_MASK 0x0000001800000000 2001 2002 2003 /* Description CP_SETTING 2004 2005 Field only valid when pkt type is HT, VHT or HE 2006 2007 GI setting, to be copied from 'PCU_PPDU_SETUP_END' by TXPCU 2008 2009 2010 This is valid for all PPDUs including HE-Ranging NDPs (11az) 2011 and Short-NDPs. 2012 2013 <enum 0 gi_0_8_us > Legacy normal GI 2014 <enum 1 gi_0_4_us > Legacy short GI 2015 <enum 2 gi_1_6_us > HE related GI 2016 <enum 3 gi_3_2_us > HE related GI 2017 <legal 0 - 3> 2018 */ 2019 2020 #define TX_FES_STATUS_END_CP_SETTING_OFFSET 0x0000000000000048 2021 #define TX_FES_STATUS_END_CP_SETTING_LSB 37 2022 #define TX_FES_STATUS_END_CP_SETTING_MSB 38 2023 #define TX_FES_STATUS_END_CP_SETTING_MASK 0x0000006000000000 2024 2025 2026 /* Description RESERVED_18A 2027 2028 Hamilton v1 used bits [11:8] for 'Mcs' for trigger-based 2029 PPDU response. 2030 <legal 0> 2031 */ 2032 2033 #define TX_FES_STATUS_END_RESERVED_18A_OFFSET 0x0000000000000048 2034 #define TX_FES_STATUS_END_RESERVED_18A_LSB 39 2035 #define TX_FES_STATUS_END_RESERVED_18A_MSB 43 2036 #define TX_FES_STATUS_END_RESERVED_18A_MASK 0x00000f8000000000 2037 2038 2039 /* Description DCM 2040 2041 Field only valid in case of 11ax transmission 2042 2043 Indicates whether dual sub-carrier modulation is applied, 2044 for trigger-based PPDU response, to be copied from 'PCU_PPDU_SETUP_END' 2045 by TXPCU 2046 0: No DCM 2047 1:DCM 2048 <legal all> 2049 */ 2050 2051 #define TX_FES_STATUS_END_DCM_OFFSET 0x0000000000000048 2052 #define TX_FES_STATUS_END_DCM_LSB 44 2053 #define TX_FES_STATUS_END_DCM_MSB 44 2054 #define TX_FES_STATUS_END_DCM_MASK 0x0000100000000000 2055 2056 2057 /* Description LDPC_EXTRA_SYMBOL 2058 2059 Set to 1 if the LDPC PPDU encoding process (if an SU PPDU), 2060 or at least one LDPC user's PPDU encoding process (if an 2061 MU PPDU), results in an extra OFDM symbol (or symbols) 2062 as described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5 2063 (Encoding process for MU PPDUs). Set to 0 otherwise. 2064 2065 To be copied from 'PCU_PPDU_SETUP_END' by TXPCU 2066 <legal all> 2067 */ 2068 2069 #define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000048 2070 #define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB 45 2071 #define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB 45 2072 #define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK 0x0000200000000000 2073 2074 2075 /* Description FORCE_EXTRA_SYMBOL 2076 2077 Set to 1 to force an extra OFDM symbol (or symbols) even 2078 if none of the users' PPDU encoding process resuls in an 2079 extra OFDM symbol (or symbols). 2080 2081 To be copied from 'PCU_PPDU_SETUP_END' by TXPCU 2082 <legal all> 2083 */ 2084 2085 #define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048 2086 #define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB 46 2087 #define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB 46 2088 #define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK 0x0000400000000000 2089 2090 2091 /* Description RESERVED_18B 2092 2093 <legal 0> 2094 */ 2095 2096 #define TX_FES_STATUS_END_RESERVED_18B_OFFSET 0x0000000000000048 2097 #define TX_FES_STATUS_END_RESERVED_18B_LSB 47 2098 #define TX_FES_STATUS_END_RESERVED_18B_MSB 47 2099 #define TX_FES_STATUS_END_RESERVED_18B_MASK 0x0000800000000000 2100 2101 2102 /* Description TX_PWR_SHARED 2103 2104 Transmit Power (signed value) in units of 0.25 dBm, to be 2105 copied from 'PCU_PPDU_SETUP_END' by TXPCU 2106 <legal all> 2107 */ 2108 2109 #define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET 0x0000000000000048 2110 #define TX_FES_STATUS_END_TX_PWR_SHARED_LSB 48 2111 #define TX_FES_STATUS_END_TX_PWR_SHARED_MSB 55 2112 #define TX_FES_STATUS_END_TX_PWR_SHARED_MASK 0x00ff000000000000 2113 2114 2115 /* Description TX_PWR_UNSHARED 2116 2117 Transmit Power (signed value) in units of 0.25 dBm, to be 2118 copied from 'PCU_PPDU_SETUP_END' by TXPCU 2119 <legal all> 2120 */ 2121 2122 #define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET 0x0000000000000048 2123 #define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB 56 2124 #define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB 63 2125 #define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK 0xff00000000000000 2126 2127 2128 /* Description RANGING_ACTIVE_USER_MAP 2129 2130 Field only valid for TB Ranging transmissions 2131 2132 TXPCU sets this to the current active user bitmap, with 2133 each bit set to: 2134 1: for an active user, and 2135 0: for any user not part of the ranging. 2136 2137 Hamilton v1 did not include this (and any subsequent) word. 2138 2139 */ 2140 2141 #define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_OFFSET 0x0000000000000050 2142 #define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_LSB 0 2143 #define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MSB 15 2144 #define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MASK 0x000000000000ffff 2145 2146 2147 /* Description RANGING_SENT_DUMMY_TX 2148 2149 Field only valid for TB Ranging transmissions 2150 2151 TXPCU sets this bit if some user's 'STA Info' or 'User Info' 2152 was sent out as dummy, or the whole transmission was sent 2153 out as dummy. 2154 */ 2155 2156 #define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_OFFSET 0x0000000000000050 2157 #define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_LSB 16 2158 #define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MSB 16 2159 #define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MASK 0x0000000000010000 2160 2161 2162 /* Description RANGING_FTM_FRAME_SENT 2163 2164 Field only valid for Ranging transmissions 2165 2166 TXPCU sets this bit if an FTM frame aggregated with an LMR 2167 was sent. 2168 */ 2169 2170 #define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_OFFSET 0x0000000000000050 2171 #define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_LSB 17 2172 #define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MSB 17 2173 #define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MASK 0x0000000000020000 2174 2175 2176 /* Description RESERVED_20A 2177 2178 <legal 0> 2179 */ 2180 2181 #define TX_FES_STATUS_END_RESERVED_20A_OFFSET 0x0000000000000050 2182 #define TX_FES_STATUS_END_RESERVED_20A_LSB 18 2183 #define TX_FES_STATUS_END_RESERVED_20A_MSB 23 2184 #define TX_FES_STATUS_END_RESERVED_20A_MASK 0x0000000000fc0000 2185 2186 2187 /* Description CV_CORR_STATUS 2188 2189 CV correlation status from 'PHYTX_CV_CORR_STATUS,' to be 2190 copied from 'PCU_PPDU_SETUP_END' by TXPCU 2191 <legal all> 2192 */ 2193 2194 #define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET 0x0000000000000050 2195 #define TX_FES_STATUS_END_CV_CORR_STATUS_LSB 24 2196 #define TX_FES_STATUS_END_CV_CORR_STATUS_MSB 31 2197 #define TX_FES_STATUS_END_CV_CORR_STATUS_MASK 0x00000000ff000000 2198 2199 2200 /* Description CURRENT_TX_DURATION 2201 2202 The duration of the transmission in us, copied over from 2203 PCU_PPDU_SETUP_{END, START} as the case may be 2204 <legal all> 2205 */ 2206 2207 #define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET 0x0000000000000050 2208 #define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB 32 2209 #define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB 47 2210 #define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK 0x0000ffff00000000 2211 2212 2213 /* Description RESERVED_21A 2214 2215 Bits [19:16]: num_cts2self_transmitted: 2216 2217 Number of CTS2SELF frames transmitted in this FES 2218 2219 <legal 0-15> 2220 */ 2221 2222 #define TX_FES_STATUS_END_RESERVED_21A_OFFSET 0x0000000000000050 2223 #define TX_FES_STATUS_END_RESERVED_21A_LSB 48 2224 #define TX_FES_STATUS_END_RESERVED_21A_MSB 63 2225 #define TX_FES_STATUS_END_RESERVED_21A_MASK 0xffff000000000000 2226 2227 2228 2229 #endif // TX_FES_STATUS_END 2230