1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _TX_FES_STATUS_PROT_H_ 27 #define _TX_FES_STATUS_PROT_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "phytx_abort_request_info.h" 32 #define NUM_OF_DWORDS_TX_FES_STATUS_PROT 14 33 34 #define NUM_OF_QWORDS_TX_FES_STATUS_PROT 7 35 36 37 struct tx_fes_status_prot { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 uint32_t success : 1, // [0:0] 40 phytx_pkt_end_info_valid : 1, // [1:1] 41 phytx_abort_request_info_valid : 1, // [2:2] 42 reserved_0 : 20, // [22:3] 43 pkt_type : 4, // [26:23] 44 dot11ax_su_extended : 1, // [27:27] 45 rate_mcs : 4; // [31:28] 46 uint32_t frame_type : 2, // [1:0] 47 frame_subtype : 4, // [5:2] 48 rx_pwr_mgmt : 1, // [6:6] 49 status : 1, // [7:7] 50 duration_field : 16, // [23:8] 51 reserved_1a : 2, // [25:24] 52 agc_cbw : 3, // [28:26] 53 service_cbw : 3; // [31:29] 54 uint32_t start_of_frame_timestamp_15_0 : 16, // [15:0] 55 start_of_frame_timestamp_31_16 : 16; // [31:16] 56 uint32_t end_of_frame_timestamp_15_0 : 16, // [15:0] 57 end_of_frame_timestamp_31_16 : 16; // [31:16] 58 uint32_t tx_group_delay : 12, // [11:0] 59 timing_status : 2, // [13:12] 60 dpdtrain_done : 1, // [14:14] 61 reserved_4 : 1, // [15:15] 62 transmit_delay : 16; // [31:16] 63 uint32_t tpc_dbg_info_cmn_15_0 : 16, // [15:0] 64 tpc_dbg_info_cmn_31_16 : 16; // [31:16] 65 uint32_t tpc_dbg_info_cmn_47_32 : 16, // [15:0] 66 tpc_dbg_info_chn1_15_0 : 16; // [31:16] 67 uint32_t tpc_dbg_info_chn1_31_16 : 16, // [15:0] 68 tpc_dbg_info_chn1_47_32 : 16; // [31:16] 69 uint32_t tpc_dbg_info_chn1_63_48 : 16, // [15:0] 70 tpc_dbg_info_chn1_79_64 : 16; // [31:16] 71 uint32_t tpc_dbg_info_chn2_15_0 : 16, // [15:0] 72 tpc_dbg_info_chn2_31_16 : 16; // [31:16] 73 uint32_t tpc_dbg_info_chn2_47_32 : 16, // [15:0] 74 tpc_dbg_info_chn2_63_48 : 16; // [31:16] 75 uint32_t tpc_dbg_info_chn2_79_64 : 16; // [15:0] 76 struct phytx_abort_request_info phytx_abort_request_info_details; 77 uint32_t phytx_tx_end_sw_info_15_0 : 16, // [15:0] 78 phytx_tx_end_sw_info_31_16 : 16; // [31:16] 79 uint32_t phytx_tx_end_sw_info_47_32 : 16, // [15:0] 80 phytx_tx_end_sw_info_63_48 : 16; // [31:16] 81 #else 82 uint32_t rate_mcs : 4, // [31:28] 83 dot11ax_su_extended : 1, // [27:27] 84 pkt_type : 4, // [26:23] 85 reserved_0 : 20, // [22:3] 86 phytx_abort_request_info_valid : 1, // [2:2] 87 phytx_pkt_end_info_valid : 1, // [1:1] 88 success : 1; // [0:0] 89 uint32_t service_cbw : 3, // [31:29] 90 agc_cbw : 3, // [28:26] 91 reserved_1a : 2, // [25:24] 92 duration_field : 16, // [23:8] 93 status : 1, // [7:7] 94 rx_pwr_mgmt : 1, // [6:6] 95 frame_subtype : 4, // [5:2] 96 frame_type : 2; // [1:0] 97 uint32_t start_of_frame_timestamp_31_16 : 16, // [31:16] 98 start_of_frame_timestamp_15_0 : 16; // [15:0] 99 uint32_t end_of_frame_timestamp_31_16 : 16, // [31:16] 100 end_of_frame_timestamp_15_0 : 16; // [15:0] 101 uint32_t transmit_delay : 16, // [31:16] 102 reserved_4 : 1, // [15:15] 103 dpdtrain_done : 1, // [14:14] 104 timing_status : 2, // [13:12] 105 tx_group_delay : 12; // [11:0] 106 uint32_t tpc_dbg_info_cmn_31_16 : 16, // [31:16] 107 tpc_dbg_info_cmn_15_0 : 16; // [15:0] 108 uint32_t tpc_dbg_info_chn1_15_0 : 16, // [31:16] 109 tpc_dbg_info_cmn_47_32 : 16; // [15:0] 110 uint32_t tpc_dbg_info_chn1_47_32 : 16, // [31:16] 111 tpc_dbg_info_chn1_31_16 : 16; // [15:0] 112 uint32_t tpc_dbg_info_chn1_79_64 : 16, // [31:16] 113 tpc_dbg_info_chn1_63_48 : 16; // [15:0] 114 uint32_t tpc_dbg_info_chn2_31_16 : 16, // [31:16] 115 tpc_dbg_info_chn2_15_0 : 16; // [15:0] 116 uint32_t tpc_dbg_info_chn2_63_48 : 16, // [31:16] 117 tpc_dbg_info_chn2_47_32 : 16; // [15:0] 118 struct phytx_abort_request_info phytx_abort_request_info_details; 119 uint16_t tpc_dbg_info_chn2_79_64 : 16; // [15:0] 120 uint32_t phytx_tx_end_sw_info_31_16 : 16, // [31:16] 121 phytx_tx_end_sw_info_15_0 : 16; // [15:0] 122 uint32_t phytx_tx_end_sw_info_63_48 : 16, // [31:16] 123 phytx_tx_end_sw_info_47_32 : 16; // [15:0] 124 #endif 125 }; 126 127 128 /* Description SUCCESS 129 130 When set, protection response has been received 131 */ 132 133 #define TX_FES_STATUS_PROT_SUCCESS_OFFSET 0x0000000000000000 134 #define TX_FES_STATUS_PROT_SUCCESS_LSB 0 135 #define TX_FES_STATUS_PROT_SUCCESS_MSB 0 136 #define TX_FES_STATUS_PROT_SUCCESS_MASK 0x0000000000000001 137 138 139 /* Description PHYTX_PKT_END_INFO_VALID 140 141 All the fields originating from PHYTX_PKT_END TLV contain 142 valid info 143 */ 144 145 #define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 146 #define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB 1 147 #define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB 1 148 #define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000002 149 150 151 /* Description PHYTX_ABORT_REQUEST_INFO_VALID 152 153 Field Phytx_abort_request_info_details contains valid info 154 155 */ 156 157 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 158 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 2 159 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 2 160 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000004 161 162 163 /* Description RESERVED_0 164 165 <legal 0> 166 */ 167 168 #define TX_FES_STATUS_PROT_RESERVED_0_OFFSET 0x0000000000000000 169 #define TX_FES_STATUS_PROT_RESERVED_0_LSB 3 170 #define TX_FES_STATUS_PROT_RESERVED_0_MSB 22 171 #define TX_FES_STATUS_PROT_RESERVED_0_MASK 0x00000000007ffff8 172 173 174 /* Description PKT_TYPE 175 176 Field only valid when success is set 177 Source of the info here is the 'RECEIVED_RESPONSE_INFO' 178 TLV. 179 180 Packet type: 181 <enum 0 dot11a>802.11a PPDU type 182 <enum 1 dot11b>802.11b PPDU type 183 <enum 2 dot11n_mm>802.11n Mixed Mode PPDU type 184 <enum 3 dot11ac>802.11ac PPDU type 185 <enum 4 dot11ax>802.11ax PPDU type 186 <enum 5 dot11ba>802.11ba (WUR) PPDU type 187 <enum 6 dot11be>802.11be PPDU type 188 <enum 7 dot11az>802.11az (ranging) PPDU type 189 <enum 8 dot11n_gf>802.11n Green Field PPDU type (unsupported 190 & aborted) 191 */ 192 193 #define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET 0x0000000000000000 194 #define TX_FES_STATUS_PROT_PKT_TYPE_LSB 23 195 #define TX_FES_STATUS_PROT_PKT_TYPE_MSB 26 196 #define TX_FES_STATUS_PROT_PKT_TYPE_MASK 0x0000000007800000 197 198 199 /* Description DOT11AX_SU_EXTENDED 200 201 Field only valid when success is set and pkt_type == 11ax 202 OR pkt_type == 11be 203 Source of the info here is the 'RECEIVED_RESPONSE_INFO' 204 TLV. 205 206 When set, the 11ax or 11be reception was an extended range 207 SU 208 */ 209 210 #define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 211 #define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB 27 212 #define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB 27 213 #define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK 0x0000000008000000 214 215 216 /* Description RATE_MCS 217 218 Field only valid when success is set 219 Source of the info here is the 'RECEIVED_RESPONSE_INFO' 220 TLV. 221 222 For details, refer to MCS_TYPE description 223 Note: This is "rate" in case of 11a/11b 224 225 <legal all> 226 */ 227 228 #define TX_FES_STATUS_PROT_RATE_MCS_OFFSET 0x0000000000000000 229 #define TX_FES_STATUS_PROT_RATE_MCS_LSB 28 230 #define TX_FES_STATUS_PROT_RATE_MCS_MSB 31 231 #define TX_FES_STATUS_PROT_RATE_MCS_MASK 0x00000000f0000000 232 233 234 /* Description FRAME_TYPE 235 236 Field only valid when 'success' is set. 237 Source of the info here is the RECEIVED_RESPONSE_INFO TLV 238 239 240 802.11 frame type field 241 This field applies for 11ah as well. 242 */ 243 244 #define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET 0x0000000000000000 245 #define TX_FES_STATUS_PROT_FRAME_TYPE_LSB 32 246 #define TX_FES_STATUS_PROT_FRAME_TYPE_MSB 33 247 #define TX_FES_STATUS_PROT_FRAME_TYPE_MASK 0x0000000300000000 248 249 250 /* Description FRAME_SUBTYPE 251 252 Field only valid when 'success' is set. 253 Source of the info here is the RECEIVED_RESPONSE_INFO TLV 254 255 256 802.11 frame subtype field 257 This field applies for 11ah as well. 258 */ 259 260 #define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET 0x0000000000000000 261 #define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB 34 262 #define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB 37 263 #define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK 0x0000003c00000000 264 265 266 /* Description RX_PWR_MGMT 267 268 Field only valid when 'success' is set. 269 Source of the info here is the RECEIVED_RESPONSE_INFO TLV 270 271 272 Power Management bit extracted from the header of the received 273 frame. 274 */ 275 276 #define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET 0x0000000000000000 277 #define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB 38 278 #define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB 38 279 #define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK 0x0000004000000000 280 281 282 /* Description STATUS 283 284 Field only valid when 'success' is set. 285 Source of the info here is the RECEIVED_RESPONSE_INFO TLV 286 287 288 If set indicates that receive packet passed FCS check. 289 */ 290 291 #define TX_FES_STATUS_PROT_STATUS_OFFSET 0x0000000000000000 292 #define TX_FES_STATUS_PROT_STATUS_LSB 39 293 #define TX_FES_STATUS_PROT_STATUS_MSB 39 294 #define TX_FES_STATUS_PROT_STATUS_MASK 0x0000008000000000 295 296 297 /* Description DURATION_FIELD 298 299 Field only valid when 'success' is set. 300 Source of the info here is the RECEIVED_RESPONSE_INFO TLV 301 302 303 The contents of the duration field of the received frame. 304 305 <legal all> 306 */ 307 308 #define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET 0x0000000000000000 309 #define TX_FES_STATUS_PROT_DURATION_FIELD_LSB 40 310 #define TX_FES_STATUS_PROT_DURATION_FIELD_MSB 55 311 #define TX_FES_STATUS_PROT_DURATION_FIELD_MASK 0x00ffff0000000000 312 313 314 /* Description RESERVED_1A 315 316 <legal 0> 317 */ 318 319 #define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET 0x0000000000000000 320 #define TX_FES_STATUS_PROT_RESERVED_1A_LSB 56 321 #define TX_FES_STATUS_PROT_RESERVED_1A_MSB 57 322 #define TX_FES_STATUS_PROT_RESERVED_1A_MASK 0x0300000000000000 323 324 325 /* Description AGC_CBW 326 327 Field only valid when 'success' is set. 328 Source of the info here is the RECEIVED_RESPONSE_INFO TLV 329 330 331 BW as detected by the AGC 332 333 <enum 0 20_mhz>20 Mhz BW 334 <enum 1 40_mhz>40 Mhz BW 335 <enum 2 80_mhz>80 Mhz BW 336 <enum 3 160_mhz>160 Mhz BW 337 <enum 4 320_mhz>320 Mhz BW 338 <enum 5 240_mhz>240 Mhz BW 339 */ 340 341 #define TX_FES_STATUS_PROT_AGC_CBW_OFFSET 0x0000000000000000 342 #define TX_FES_STATUS_PROT_AGC_CBW_LSB 58 343 #define TX_FES_STATUS_PROT_AGC_CBW_MSB 60 344 #define TX_FES_STATUS_PROT_AGC_CBW_MASK 0x1c00000000000000 345 346 347 /* Description SERVICE_CBW 348 349 Field only valid when 'success' is set. 350 351 Source of the info here is the RECEIVED_RESPONSE_INFO TLV 352 353 354 This field reflects the BW extracted from the Serivce Field 355 for 11ac mode of operation . 356 357 This field is used in the context of Dynamic/Static BW evaluation 358 purposes in TxPCU 359 CBW field extracted from Service field 360 361 <enum 0 20_mhz>20 Mhz BW 362 <enum 1 40_mhz>40 Mhz BW 363 <enum 2 80_mhz>80 Mhz BW 364 <enum 3 160_mhz>160 Mhz BW 365 <enum 4 320_mhz>320 Mhz BW 366 <enum 5 240_mhz>240 Mhz BW 367 */ 368 369 #define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET 0x0000000000000000 370 #define TX_FES_STATUS_PROT_SERVICE_CBW_LSB 61 371 #define TX_FES_STATUS_PROT_SERVICE_CBW_MSB 63 372 #define TX_FES_STATUS_PROT_SERVICE_CBW_MASK 0xe000000000000000 373 374 375 /* Description START_OF_FRAME_TIMESTAMP_15_0 376 377 PHYTX_PKT_END info 378 379 Field only valid when PHYTX_PKT_END_info_valid is set 380 381 bits 15:0 of a 64 bit time stamp 382 Start of frame in the medium @960 MHz 383 <legal all> 384 */ 385 386 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 387 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 388 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 389 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff 390 391 392 /* Description START_OF_FRAME_TIMESTAMP_31_16 393 394 PHYTX_PKT_END info 395 396 Field only valid when PHYTX_PKT_END_info_valid is set 397 398 bits 31:16 of a 64 bit time stamp 399 Start of frame in the medium @960 MHz 400 <legal all> 401 */ 402 403 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 404 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_LSB 16 405 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MSB 31 406 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 407 408 409 /* Description END_OF_FRAME_TIMESTAMP_15_0 410 411 PHYTX_PKT_END info 412 413 Field only valid when PHYTX_PKT_END_info_valid is set 414 415 bits 15:0 of a 64 bit time stamp 416 End of frame in the medium @960 MHz 417 <legal all> 418 */ 419 420 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 421 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_LSB 32 422 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MSB 47 423 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 424 425 426 /* Description END_OF_FRAME_TIMESTAMP_31_16 427 428 PHYTX_PKT_END info 429 430 Field only valid when PHYTX_PKT_END_info_valid is set 431 432 bits 31:16 of a 64 bit time stamp 433 End of frame in the medium @960 MHz 434 <legal all> 435 */ 436 437 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 438 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_LSB 48 439 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MSB 63 440 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 441 442 443 /* Description TX_GROUP_DELAY 444 445 PHYTX_PKT_END info 446 447 Field only valid when PHYTX_PKT_END_info_valid is set 448 449 Group delay on TxTD+PHYRF path for this PPDU (packet BW 450 dependent), useful for RTT 451 452 Unit is 960MHz cycles. 453 <legal all> 454 */ 455 456 #define TX_FES_STATUS_PROT_TX_GROUP_DELAY_OFFSET 0x0000000000000010 457 #define TX_FES_STATUS_PROT_TX_GROUP_DELAY_LSB 0 458 #define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MSB 11 459 #define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MASK 0x0000000000000fff 460 461 462 /* Description TIMING_STATUS 463 464 PHYTX_PKT_END info 465 466 Field only valid when PHYTX_PKT_END_info_valid is set 467 468 <enum 0 No_tx_timing_request> The MAC did not request for 469 the transmission to start at a particular time 470 <enum 1 successful_tx_timing > MAC did request for transmission 471 to start at a particular time and PHY was able to do so. 472 473 <enum 2 tx_timing_not_honoured> PHY was not able to honour 474 the requested transmit time by the MAC. The transmission 475 started later, and field transmit_delay indicates how much 476 later. 477 <legal 0-2> 478 */ 479 480 #define TX_FES_STATUS_PROT_TIMING_STATUS_OFFSET 0x0000000000000010 481 #define TX_FES_STATUS_PROT_TIMING_STATUS_LSB 12 482 #define TX_FES_STATUS_PROT_TIMING_STATUS_MSB 13 483 #define TX_FES_STATUS_PROT_TIMING_STATUS_MASK 0x0000000000003000 484 485 486 /* Description DPDTRAIN_DONE 487 488 Field only valid when PHYTX_PKT_END_info_valid is set 489 490 For DPD Training packets, this bit is set to indicate that 491 DPD Training was successfully run to completion. Also 492 reused by Implicit BF Calibration Packets. This bit is intended 493 for debug purposes. 494 <legal all> 495 */ 496 497 #define TX_FES_STATUS_PROT_DPDTRAIN_DONE_OFFSET 0x0000000000000010 498 #define TX_FES_STATUS_PROT_DPDTRAIN_DONE_LSB 14 499 #define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MSB 14 500 #define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MASK 0x0000000000004000 501 502 503 /* Description RESERVED_4 504 505 PHYTX_PKT_END info 506 507 <legal 0> 508 */ 509 510 #define TX_FES_STATUS_PROT_RESERVED_4_OFFSET 0x0000000000000010 511 #define TX_FES_STATUS_PROT_RESERVED_4_LSB 15 512 #define TX_FES_STATUS_PROT_RESERVED_4_MSB 15 513 #define TX_FES_STATUS_PROT_RESERVED_4_MASK 0x0000000000008000 514 515 516 /* Description TRANSMIT_DELAY 517 518 PHYTX_PKT_END info 519 520 The number of 480 MHz clock cycles that the transmission 521 started after the actual requested transmit start time. 522 523 Value saturates at 0xFFFF 524 <legal all> 525 */ 526 527 #define TX_FES_STATUS_PROT_TRANSMIT_DELAY_OFFSET 0x0000000000000010 528 #define TX_FES_STATUS_PROT_TRANSMIT_DELAY_LSB 16 529 #define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MSB 31 530 #define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MASK 0x00000000ffff0000 531 532 533 /* Description TPC_DBG_INFO_CMN_15_0 534 535 PHYTX_PKT_END info 536 537 Field only valid when PHYTX_PKT_END_info_valid is set 538 539 Some TPC debug info that PHY can pass back to MAC FW 540 <legal all> 541 */ 542 543 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000010 544 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_LSB 32 545 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MSB 47 546 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff00000000 547 548 549 /* Description TPC_DBG_INFO_CMN_31_16 550 551 PHYTX_PKT_END info 552 553 Field only valid when PHYTX_PKT_END_info_valid is set 554 555 Some TPC debug info that PHY can pass back to MAC FW 556 <legal all> 557 */ 558 559 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000000000010 560 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_LSB 48 561 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MSB 63 562 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MASK 0xffff000000000000 563 564 565 /* Description TPC_DBG_INFO_CMN_47_32 566 567 PHYTX_PKT_END info 568 569 Field only valid when PHYTX_PKT_END_info_valid is set 570 571 Some TPC debug info that PHY can pass back to MAC FW 572 <legal all> 573 */ 574 575 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_OFFSET 0x0000000000000018 576 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_LSB 0 577 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MSB 15 578 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MASK 0x000000000000ffff 579 580 581 /* Description TPC_DBG_INFO_CHN1_15_0 582 583 PHYTX_PKT_END info 584 585 Field only valid when PHYTX_PKT_END_info_valid is set 586 587 Some per-chain TPC debug info for the first selected chain 588 that PHY can pass back to MAC FW 589 <legal all> 590 */ 591 592 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000018 593 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_LSB 16 594 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MSB 31 595 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MASK 0x00000000ffff0000 596 597 598 /* Description TPC_DBG_INFO_CHN1_31_16 599 600 PHYTX_PKT_END info 601 602 Field only valid when PHYTX_PKT_END_info_valid is set 603 604 Some per-chain TPC debug info for the first selected chain 605 that PHY can pass back to MAC FW 606 <legal all> 607 */ 608 609 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000018 610 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_LSB 32 611 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MSB 47 612 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff00000000 613 614 615 /* Description TPC_DBG_INFO_CHN1_47_32 616 617 PHYTX_PKT_END info 618 619 Field only valid when PHYTX_PKT_END_info_valid is set 620 621 Some per-chain TPC debug info for the first selected chain 622 that PHY can pass back to MAC FW 623 <legal all> 624 */ 625 626 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000018 627 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_LSB 48 628 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MSB 63 629 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MASK 0xffff000000000000 630 631 632 /* Description TPC_DBG_INFO_CHN1_63_48 633 634 PHYTX_PKT_END info 635 636 Field only valid when PHYTX_PKT_END_info_valid is set 637 638 Some per-chain TPC debug info for the first selected chain 639 that PHY can pass back to MAC FW 640 <legal all> 641 */ 642 643 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000020 644 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_LSB 0 645 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MSB 15 646 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MASK 0x000000000000ffff 647 648 649 /* Description TPC_DBG_INFO_CHN1_79_64 650 651 PHYTX_PKT_END info 652 653 Field only valid when PHYTX_PKT_END_info_valid is set 654 655 Some per-chain TPC debug info for the first selected chain 656 that PHY can pass back to MAC FW 657 <legal all> 658 */ 659 660 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000020 661 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_LSB 16 662 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MSB 31 663 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MASK 0x00000000ffff0000 664 665 666 /* Description TPC_DBG_INFO_CHN2_15_0 667 668 PHYTX_PKT_END info 669 670 Field only valid when PHYTX_PKT_END_info_valid is set 671 672 Some per-chain TPC debug info for the second selected chain 673 that PHY can pass back to MAC FW 674 <legal all> 675 */ 676 677 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000020 678 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_LSB 32 679 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MSB 47 680 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff00000000 681 682 683 /* Description TPC_DBG_INFO_CHN2_31_16 684 685 PHYTX_PKT_END info 686 687 Field only valid when PHYTX_PKT_END_info_valid is set 688 689 Some per-chain TPC debug info for the second selected chain 690 that PHY can pass back to MAC FW 691 <legal all> 692 */ 693 694 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000020 695 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_LSB 48 696 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MSB 63 697 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MASK 0xffff000000000000 698 699 700 /* Description TPC_DBG_INFO_CHN2_47_32 701 702 PHYTX_PKT_END info 703 704 Field only valid when PHYTX_PKT_END_info_valid is set 705 706 Some per-chain TPC debug info for the second selected chain 707 that PHY can pass back to MAC FW 708 <legal all> 709 */ 710 711 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000028 712 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_LSB 0 713 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MSB 15 714 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MASK 0x000000000000ffff 715 716 717 /* Description TPC_DBG_INFO_CHN2_63_48 718 719 PHYTX_PKT_END info 720 721 Field only valid when PHYTX_PKT_END_info_valid is set 722 723 Some per-chain TPC debug info for the second selected chain 724 that PHY can pass back to MAC FW 725 <legal all> 726 */ 727 728 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000028 729 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_LSB 16 730 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MSB 31 731 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MASK 0x00000000ffff0000 732 733 734 /* Description TPC_DBG_INFO_CHN2_79_64 735 736 PHYTX_PKT_END info 737 738 Field only valid when PHYTX_PKT_END_info_valid is set 739 740 Some per-chain TPC debug info for the second selected chain 741 that PHY can pass back to MAC FW 742 <legal all> 743 */ 744 745 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000028 746 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_LSB 32 747 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MSB 47 748 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff00000000 749 750 751 /* Description PHYTX_ABORT_REQUEST_INFO_DETAILS 752 753 Field only valid when PHYTX_ABORT_REQUEST_info_valid is 754 set 755 756 The reason why PHYTX is requested an abort 757 */ 758 759 760 /* Description PHYTX_ABORT_REASON 761 762 Reason for early termination of TX packet by the PHY 763 764 <enum_type PHYTX_ABORT_ENUM> 765 */ 766 767 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000028 768 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 48 769 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 55 770 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x00ff000000000000 771 772 773 /* Description USER_NUMBER 774 775 For some errors, the user for which this error was detected 776 can be indicated in this field. 777 <legal 0-36> 778 */ 779 780 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000028 781 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 56 782 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 61 783 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x3f00000000000000 784 785 786 /* Description RESERVED 787 788 <legal 0> 789 */ 790 791 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000028 792 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 62 793 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 63 794 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0xc000000000000000 795 796 797 /* Description PHYTX_TX_END_SW_INFO_15_0 798 799 PHYTX_PKT_END info 800 801 Field only valid when PHYTX_PKT_END_info_valid is set 802 803 Some PHY status data that PHY microcode can pass back to 804 MAC FW, for any future requests, e.g. any DMA download 805 time 806 <legal all> 807 */ 808 809 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000030 810 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_LSB 0 811 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MSB 15 812 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff 813 814 815 /* Description PHYTX_TX_END_SW_INFO_31_16 816 817 PHYTX_PKT_END info 818 819 Field only valid when PHYTX_PKT_END_info_valid is set 820 821 Some PHY status data that PHY microcode can pass back to 822 MAC FW, for any future requests, e.g. any DMA download 823 time 824 <legal all> 825 */ 826 827 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000030 828 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_LSB 16 829 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MSB 31 830 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 831 832 833 /* Description PHYTX_TX_END_SW_INFO_47_32 834 835 PHYTX_PKT_END info 836 837 Field only valid when PHYTX_PKT_END_info_valid is set 838 839 Some PHY status data that PHY microcode can pass back to 840 MAC FW, for any future requests, e.g. any DMA download 841 time 842 <legal all> 843 */ 844 845 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000030 846 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_LSB 32 847 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MSB 47 848 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 849 850 851 /* Description PHYTX_TX_END_SW_INFO_63_48 852 853 PHYTX_PKT_END info 854 855 Field only valid when PHYTX_PKT_END_info_valid is set 856 857 Some PHY status data that PHY microcode can pass back to 858 MAC FW, for any future requests, e.g. any DMA download 859 time 860 <legal all> 861 */ 862 863 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000030 864 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_LSB 48 865 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MSB 63 866 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 867 868 869 870 #endif // TX_FES_STATUS_PROT 871