1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _TX_MPDU_START_H_ 27 #define _TX_MPDU_START_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_TX_MPDU_START 10 32 33 #define NUM_OF_QWORDS_TX_MPDU_START 5 34 35 36 struct tx_mpdu_start { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t mpdu_length : 14, // [13:0] 39 frame_not_from_tqm : 1, // [14:14] 40 vht_control_present : 1, // [15:15] 41 mpdu_header_length : 8, // [23:16] 42 retry_count : 7, // [30:24] 43 wds : 1; // [31:31] 44 uint32_t pn_31_0 : 32; // [31:0] 45 uint32_t pn_47_32 : 16, // [15:0] 46 mpdu_sequence_number : 12, // [27:16] 47 raw_already_encrypted : 1, // [28:28] 48 frame_type : 2, // [30:29] 49 txdma_dropped_mpdu_warning : 1; // [31:31] 50 uint32_t iv_byte_0 : 8, // [7:0] 51 iv_byte_1 : 8, // [15:8] 52 iv_byte_2 : 8, // [23:16] 53 iv_byte_3 : 8; // [31:24] 54 uint32_t iv_byte_4 : 8, // [7:0] 55 iv_byte_5 : 8, // [15:8] 56 iv_byte_6 : 8, // [23:16] 57 iv_byte_7 : 8; // [31:24] 58 uint32_t iv_byte_8 : 8, // [7:0] 59 iv_byte_9 : 8, // [15:8] 60 iv_byte_10 : 8, // [23:16] 61 iv_byte_11 : 8; // [31:24] 62 uint32_t iv_byte_12 : 8, // [7:0] 63 iv_byte_13 : 8, // [15:8] 64 iv_byte_14 : 8, // [23:16] 65 iv_byte_15 : 8; // [31:24] 66 uint32_t iv_byte_16 : 8, // [7:0] 67 iv_byte_17 : 8, // [15:8] 68 iv_len : 5, // [20:16] 69 icv_len : 5, // [25:21] 70 vht_control_offset : 6; // [31:26] 71 uint32_t mpdu_type : 1, // [0:0] 72 transmit_bw_restriction : 1, // [1:1] 73 allowed_transmit_bw : 4, // [5:2] 74 tx_notify_frame : 3, // [8:6] 75 reserved_8a : 23; // [31:9] 76 uint32_t tlv64_padding : 32; // [31:0] 77 #else 78 uint32_t wds : 1, // [31:31] 79 retry_count : 7, // [30:24] 80 mpdu_header_length : 8, // [23:16] 81 vht_control_present : 1, // [15:15] 82 frame_not_from_tqm : 1, // [14:14] 83 mpdu_length : 14; // [13:0] 84 uint32_t pn_31_0 : 32; // [31:0] 85 uint32_t txdma_dropped_mpdu_warning : 1, // [31:31] 86 frame_type : 2, // [30:29] 87 raw_already_encrypted : 1, // [28:28] 88 mpdu_sequence_number : 12, // [27:16] 89 pn_47_32 : 16; // [15:0] 90 uint32_t iv_byte_3 : 8, // [31:24] 91 iv_byte_2 : 8, // [23:16] 92 iv_byte_1 : 8, // [15:8] 93 iv_byte_0 : 8; // [7:0] 94 uint32_t iv_byte_7 : 8, // [31:24] 95 iv_byte_6 : 8, // [23:16] 96 iv_byte_5 : 8, // [15:8] 97 iv_byte_4 : 8; // [7:0] 98 uint32_t iv_byte_11 : 8, // [31:24] 99 iv_byte_10 : 8, // [23:16] 100 iv_byte_9 : 8, // [15:8] 101 iv_byte_8 : 8; // [7:0] 102 uint32_t iv_byte_15 : 8, // [31:24] 103 iv_byte_14 : 8, // [23:16] 104 iv_byte_13 : 8, // [15:8] 105 iv_byte_12 : 8; // [7:0] 106 uint32_t vht_control_offset : 6, // [31:26] 107 icv_len : 5, // [25:21] 108 iv_len : 5, // [20:16] 109 iv_byte_17 : 8, // [15:8] 110 iv_byte_16 : 8; // [7:0] 111 uint32_t reserved_8a : 23, // [31:9] 112 tx_notify_frame : 3, // [8:6] 113 allowed_transmit_bw : 4, // [5:2] 114 transmit_bw_restriction : 1, // [1:1] 115 mpdu_type : 1; // [0:0] 116 uint32_t tlv64_padding : 32; // [31:0] 117 #endif 118 }; 119 120 121 /* Description MPDU_LENGTH 122 123 Consumer: TXOLE/CRYPTO/TXPCU 124 Producer: TXDMA 125 126 Expected Length of the entire MPDU, which includes all MSDUs 127 within the MPDU and all OLE and Crypto processing. This 128 length includes the FCS field. 129 */ 130 131 #define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x0000000000000000 132 #define TX_MPDU_START_MPDU_LENGTH_LSB 0 133 #define TX_MPDU_START_MPDU_LENGTH_MSB 13 134 #define TX_MPDU_START_MPDU_LENGTH_MASK 0x0000000000003fff 135 136 137 /* Description FRAME_NOT_FROM_TQM 138 139 When set, TXPCU shall not take this frame into account for 140 indicating to TQM how many frames from it's queue got transmitted. 141 142 143 TXDMA gets this field from the TX_MSDU_DETAILS STRUCT (of 144 the first MSDU in the MPDU) in the MSDU link descriptor. 145 146 147 SW sets this bit (in TX_MSDU_DETAILS STRUCT) when it generates 148 a frame outside of the TQM path and that frame can be intermingled 149 with the other frames from the TQM. For example a trigger 150 frame embedded or put in front of data frames from TQM 151 within the same A-MPDU. For this SW generated frame, TXPCU 152 shall not include this frame in the transmit frame count 153 that is reported to TQM as that would result in incorrect 154 reporting to TQM. 155 156 <legal all> 157 */ 158 159 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x0000000000000000 160 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14 161 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14 162 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x0000000000004000 163 164 165 /* Description VHT_CONTROL_PRESENT 166 167 TXOLE sets this bit when it added 4 placeholder bytes for 168 VHT-CONTROL field in the MPDU header. 169 170 For RAW frames, OLE will set this bit and compute vht_control_offset 171 when the order bit and QoS bit in frame_control field are 172 set to 1. For RAW management frame, this bit will be set 173 if order bit is set to 1. 174 175 Used by TXPCU, to find out if it needs to overwrite the 176 HE-CONTROL field. 177 <legal all> 178 */ 179 180 #define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x0000000000000000 181 #define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15 182 #define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15 183 #define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x0000000000008000 184 185 186 /* Description MPDU_HEADER_LENGTH 187 188 This field is filled in by the OLE 189 Used by PCU, This prevents PCU from having to do this again 190 (in the same way)) 191 */ 192 193 #define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x0000000000000000 194 #define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16 195 #define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23 196 #define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x0000000000ff0000 197 198 199 /* Description RETRY_COUNT 200 201 Consumer: TXOLE/TXPCU 202 Producer: TXDMA 203 204 The number of times the frame is transmitted 205 <legal all> 206 */ 207 208 #define TX_MPDU_START_RETRY_COUNT_OFFSET 0x0000000000000000 209 #define TX_MPDU_START_RETRY_COUNT_LSB 24 210 #define TX_MPDU_START_RETRY_COUNT_MSB 30 211 #define TX_MPDU_START_RETRY_COUNT_MASK 0x000000007f000000 212 213 214 /* Description WDS 215 216 If set the current packet is 4-address frame. 217 218 Required because an aggregate can include some frames with 219 3 address format and other frames with 4 address format. 220 Used by the OLE during encapsulation. 221 222 TXDMA sets this when wds in the extension descriptor is 223 set. 224 225 If no extension descriptor is used for this MPDU, TXDMA 226 gets the setting for this bit from a control register in 227 TXDMA 228 <legal all> 229 */ 230 231 #define TX_MPDU_START_WDS_OFFSET 0x0000000000000000 232 #define TX_MPDU_START_WDS_LSB 31 233 #define TX_MPDU_START_WDS_MSB 31 234 #define TX_MPDU_START_WDS_MASK 0x0000000080000000 235 236 237 /* Description PN_31_0 238 239 Consumer: TXOLE 240 Producer: TXDMA 241 242 Bits 31 - 0 for the Packet Number used by encryption 243 <legal all> 244 */ 245 246 #define TX_MPDU_START_PN_31_0_OFFSET 0x0000000000000000 247 #define TX_MPDU_START_PN_31_0_LSB 32 248 #define TX_MPDU_START_PN_31_0_MSB 63 249 #define TX_MPDU_START_PN_31_0_MASK 0xffffffff00000000 250 251 252 /* Description PN_47_32 253 254 Consumer: TXOLE 255 Producer: TXDMA 256 257 Bits 47 - 32 for the Packet Number used by encryption 258 <legal all> 259 */ 260 261 #define TX_MPDU_START_PN_47_32_OFFSET 0x0000000000000008 262 #define TX_MPDU_START_PN_47_32_LSB 0 263 #define TX_MPDU_START_PN_47_32_MSB 15 264 #define TX_MPDU_START_PN_47_32_MASK 0x000000000000ffff 265 266 267 /* Description MPDU_SEQUENCE_NUMBER 268 269 Consumer: TXOLE 270 Producer: TXDMA 271 272 Sequence number assigned to this MPDU 273 <legal all> 274 */ 275 276 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000008 277 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16 278 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27 279 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x000000000fff0000 280 281 282 /* Description RAW_ALREADY_ENCRYPTED 283 284 Consumer: CRYPTO 285 Producer: TXDMA 286 287 If set it indicates that the RAW MPDU has already been encrypted 288 and does not require HW encryption. If clear and if the 289 frame control indicates that this is a "protected" MPDU 290 and the peer key type indicates a cipher type then the 291 HW is expected to encrypt this packet. 292 <legal all> 293 */ 294 295 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x0000000000000008 296 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28 297 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28 298 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x0000000010000000 299 300 301 /* Description FRAME_TYPE 302 303 Consumer: TXMON 304 Producer: TXOLE 305 306 802.11 frame type field 307 308 TXDMA fills this as zero and TXOLE overwrites it. 309 310 <legal all> 311 */ 312 313 #define TX_MPDU_START_FRAME_TYPE_OFFSET 0x0000000000000008 314 #define TX_MPDU_START_FRAME_TYPE_LSB 29 315 #define TX_MPDU_START_FRAME_TYPE_MSB 30 316 #define TX_MPDU_START_FRAME_TYPE_MASK 0x0000000060000000 317 318 319 /* Description TXDMA_DROPPED_MPDU_WARNING 320 321 Consumer: FW 322 Producer: TXDMA 323 324 Indication to TXPCU to indicate to FW a warning that Tx 325 DMA has dropped MPDUs due to SFM FIFO full condition 326 <legal all> 327 */ 328 329 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000008 330 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31 331 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31 332 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x0000000080000000 333 334 335 /* Description IV_BYTE_0 336 337 Byte 0 of the IV field of the MPDU 338 Based on the Encryption type the iv_byte_0 takes the appropriate 339 meaning. For IV formats, refer to the crypto MLDR document 340 341 */ 342 343 #define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000000000008 344 #define TX_MPDU_START_IV_BYTE_0_LSB 32 345 #define TX_MPDU_START_IV_BYTE_0_MSB 39 346 #define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff00000000 347 348 349 /* Description IV_BYTE_1 350 351 Byte 1 of the IV field of the MPDU 352 Based on the Encryption type the iv_byte_1 takes the appropriate 353 meaning. For IV formats, refer to the crypto MLDR document 354 355 */ 356 357 #define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000000000008 358 #define TX_MPDU_START_IV_BYTE_1_LSB 40 359 #define TX_MPDU_START_IV_BYTE_1_MSB 47 360 #define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff0000000000 361 362 363 /* Description IV_BYTE_2 364 365 Byte 2 of the IV field of the MDPU 366 Based on the Encryption type the iv_byte_2 takes the appropriate 367 meaning. For IV formats, refer to the crypto MLDR document 368 369 */ 370 371 #define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000000000008 372 #define TX_MPDU_START_IV_BYTE_2_LSB 48 373 #define TX_MPDU_START_IV_BYTE_2_MSB 55 374 #define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff000000000000 375 376 377 /* Description IV_BYTE_3 378 379 Byte 3 of the IV field of the MPDU 380 Based on the Encryption type the iv_byte_3 takes the appropriate 381 meaning. For IV formats, refer to the crypto MLDR document 382 383 */ 384 385 #define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000000000008 386 #define TX_MPDU_START_IV_BYTE_3_LSB 56 387 #define TX_MPDU_START_IV_BYTE_3_MSB 63 388 #define TX_MPDU_START_IV_BYTE_3_MASK 0xff00000000000000 389 390 391 /* Description IV_BYTE_4 392 393 Byte 4 of the IV field of the MPDU 394 Based on the Encryption type the iv_byte_4 takes the appropriate 395 meaning. For IV formats, refer to the crypto MLDR document 396 397 */ 398 399 #define TX_MPDU_START_IV_BYTE_4_OFFSET 0x0000000000000010 400 #define TX_MPDU_START_IV_BYTE_4_LSB 0 401 #define TX_MPDU_START_IV_BYTE_4_MSB 7 402 #define TX_MPDU_START_IV_BYTE_4_MASK 0x00000000000000ff 403 404 405 /* Description IV_BYTE_5 406 407 Byte 5 of the IV field of the MPDU 408 Based on the Encryption type the iv_byte_5 takes the appropriate 409 meaning. For IV formats, refer to the crypto MLDR document 410 411 */ 412 413 #define TX_MPDU_START_IV_BYTE_5_OFFSET 0x0000000000000010 414 #define TX_MPDU_START_IV_BYTE_5_LSB 8 415 #define TX_MPDU_START_IV_BYTE_5_MSB 15 416 #define TX_MPDU_START_IV_BYTE_5_MASK 0x000000000000ff00 417 418 419 /* Description IV_BYTE_6 420 421 Byte 6 of the IV field of the MDPU 422 Based on the Encryption type the iv_byte_6 takes the appropriate 423 meaning. For IV formats, refer to the crypto MLDR document 424 425 */ 426 427 #define TX_MPDU_START_IV_BYTE_6_OFFSET 0x0000000000000010 428 #define TX_MPDU_START_IV_BYTE_6_LSB 16 429 #define TX_MPDU_START_IV_BYTE_6_MSB 23 430 #define TX_MPDU_START_IV_BYTE_6_MASK 0x0000000000ff0000 431 432 433 /* Description IV_BYTE_7 434 435 Byte 7 of the IV field of the MPDU 436 Based on the Encryption type the iv_byte_7 takes the appropriate 437 meaning. For IV formats, refer to the crypto MLDR document 438 439 */ 440 441 #define TX_MPDU_START_IV_BYTE_7_OFFSET 0x0000000000000010 442 #define TX_MPDU_START_IV_BYTE_7_LSB 24 443 #define TX_MPDU_START_IV_BYTE_7_MSB 31 444 #define TX_MPDU_START_IV_BYTE_7_MASK 0x00000000ff000000 445 446 447 /* Description IV_BYTE_8 448 449 Byte 8 of the IV field of the MPDU 450 Based on the Encryption type the iv_byte_8 takes the appropriate 451 meaning. For IV formats, refer to the crypto MLDR document 452 453 */ 454 455 #define TX_MPDU_START_IV_BYTE_8_OFFSET 0x0000000000000010 456 #define TX_MPDU_START_IV_BYTE_8_LSB 32 457 #define TX_MPDU_START_IV_BYTE_8_MSB 39 458 #define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff00000000 459 460 461 /* Description IV_BYTE_9 462 463 Byte 9 of the IV field of the MPDU 464 Based on the Encryption type the iv_byte_9 takes the appropriate 465 meaning. For IV formats, refer to the crypto MLDR document 466 467 */ 468 469 #define TX_MPDU_START_IV_BYTE_9_OFFSET 0x0000000000000010 470 #define TX_MPDU_START_IV_BYTE_9_LSB 40 471 #define TX_MPDU_START_IV_BYTE_9_MSB 47 472 #define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff0000000000 473 474 475 /* Description IV_BYTE_10 476 477 Byte 10 of the IV field of the MDPU 478 Based on the Encryption type the iv_byte_10 takes the appropriate 479 meaning. For IV formats, refer to the crypto MLDR document 480 481 */ 482 483 #define TX_MPDU_START_IV_BYTE_10_OFFSET 0x0000000000000010 484 #define TX_MPDU_START_IV_BYTE_10_LSB 48 485 #define TX_MPDU_START_IV_BYTE_10_MSB 55 486 #define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff000000000000 487 488 489 /* Description IV_BYTE_11 490 491 Byte 11 of the IV field of the MPDU 492 Based on the Encryption type the iv_byte_11 takes the appropriate 493 meaning. For IV formats, refer to the crypto MLDR document 494 495 */ 496 497 #define TX_MPDU_START_IV_BYTE_11_OFFSET 0x0000000000000010 498 #define TX_MPDU_START_IV_BYTE_11_LSB 56 499 #define TX_MPDU_START_IV_BYTE_11_MSB 63 500 #define TX_MPDU_START_IV_BYTE_11_MASK 0xff00000000000000 501 502 503 /* Description IV_BYTE_12 504 505 Byte 8 of the IV field of the MPDU 506 Based on the Encryption type the iv_byte_12 takes the appropriate 507 meaning. For IV formats, refer to the crypto MLDR document 508 509 */ 510 511 #define TX_MPDU_START_IV_BYTE_12_OFFSET 0x0000000000000018 512 #define TX_MPDU_START_IV_BYTE_12_LSB 0 513 #define TX_MPDU_START_IV_BYTE_12_MSB 7 514 #define TX_MPDU_START_IV_BYTE_12_MASK 0x00000000000000ff 515 516 517 /* Description IV_BYTE_13 518 519 Byte 9 of the IV field of the MPDU 520 Based on the Encryption type the iv_byte_13 takes the appropriate 521 meaning. For IV formats, refer to the crypto MLDR document 522 523 */ 524 525 #define TX_MPDU_START_IV_BYTE_13_OFFSET 0x0000000000000018 526 #define TX_MPDU_START_IV_BYTE_13_LSB 8 527 #define TX_MPDU_START_IV_BYTE_13_MSB 15 528 #define TX_MPDU_START_IV_BYTE_13_MASK 0x000000000000ff00 529 530 531 /* Description IV_BYTE_14 532 533 Byte 10 of the IV field of the MDPU 534 Based on the Encryption type the iv_byte_14 takes the appropriate 535 meaning. For IV formats, refer to the crypto MLDR document 536 537 */ 538 539 #define TX_MPDU_START_IV_BYTE_14_OFFSET 0x0000000000000018 540 #define TX_MPDU_START_IV_BYTE_14_LSB 16 541 #define TX_MPDU_START_IV_BYTE_14_MSB 23 542 #define TX_MPDU_START_IV_BYTE_14_MASK 0x0000000000ff0000 543 544 545 /* Description IV_BYTE_15 546 547 Byte 11 of the IV field of the MPDU 548 Based on the Encryption type the iv_byte_15 takes the appropriate 549 meaning. For IV formats, refer to the crypto MLDR document 550 551 */ 552 553 #define TX_MPDU_START_IV_BYTE_15_OFFSET 0x0000000000000018 554 #define TX_MPDU_START_IV_BYTE_15_LSB 24 555 #define TX_MPDU_START_IV_BYTE_15_MSB 31 556 #define TX_MPDU_START_IV_BYTE_15_MASK 0x00000000ff000000 557 558 559 /* Description IV_BYTE_16 560 561 Byte 8 of the IV field of the MPDU 562 Based on the Encryption type the iv_byte_16 takes the appropriate 563 meaning. For IV formats, refer to the crypto MLDR document 564 565 */ 566 567 #define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000000000000018 568 #define TX_MPDU_START_IV_BYTE_16_LSB 32 569 #define TX_MPDU_START_IV_BYTE_16_MSB 39 570 #define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff00000000 571 572 573 /* Description IV_BYTE_17 574 575 Byte 9 of the IV field of the MPDU 576 Based on the Encryption type the iv_byte_17 takes the appropriate 577 meaning. For IV formats, refer to the crypto MLDR document 578 579 */ 580 581 #define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000000000000018 582 #define TX_MPDU_START_IV_BYTE_17_LSB 40 583 #define TX_MPDU_START_IV_BYTE_17_MSB 47 584 #define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff0000000000 585 586 587 /* Description IV_LEN 588 589 Length of the IV field generated by Tx OLE 590 */ 591 592 #define TX_MPDU_START_IV_LEN_OFFSET 0x0000000000000018 593 #define TX_MPDU_START_IV_LEN_LSB 48 594 #define TX_MPDU_START_IV_LEN_MSB 52 595 #define TX_MPDU_START_IV_LEN_MASK 0x001f000000000000 596 597 598 /* Description ICV_LEN 599 600 Length of the ICV field generated by Tx OLE. OLE will insert 601 zeros in the ICV field when it pushes a frame 602 */ 603 604 #define TX_MPDU_START_ICV_LEN_OFFSET 0x0000000000000018 605 #define TX_MPDU_START_ICV_LEN_LSB 53 606 #define TX_MPDU_START_ICV_LEN_MSB 57 607 #define TX_MPDU_START_ICV_LEN_MASK 0x03e0000000000000 608 609 610 /* Description VHT_CONTROL_OFFSET 611 612 Field only valid when vht_control_present is set. 613 614 Field filled in by TXOLE, used by TXPCU 615 616 The starting byte number of the VHT control field in the 617 header 618 <legal all> 619 */ 620 621 #define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000000000000018 622 #define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 58 623 #define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 63 624 #define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc00000000000000 625 626 627 /* Description MPDU_TYPE 628 629 Indicates the type of MPDU that OLE will generate: 630 631 <enum 0 mpdu_type_basic> This MPDU is not in the A-MSDU 632 format (meaning there is no A-MSDU delimeter present) if 633 there is only 1 MSDU in the MPDU. When there are multiple 634 MSDUs in the MPDU, there is no choice, and the MSDUs within 635 the MPDU shall all have A-MSDU delimiters in front of them. 636 637 <enum 1 mpdu_type_amsdu> The MSDUs within the MPDU will 638 all have to be in the A-MSDU format, even if there is just 639 a single MSDU embedded in the MPDU. In other words, there 640 is always an A-MSDU delimiter in front of the MSDU(s) in 641 the MPDU. 642 This is not supported in Hastings80 and HastingsPrime. 643 <legal all> 644 */ 645 646 #define TX_MPDU_START_MPDU_TYPE_OFFSET 0x0000000000000020 647 #define TX_MPDU_START_MPDU_TYPE_LSB 0 648 #define TX_MPDU_START_MPDU_TYPE_MSB 0 649 #define TX_MPDU_START_MPDU_TYPE_MASK 0x0000000000000001 650 651 652 /* Description TRANSMIT_BW_RESTRICTION 653 654 Consumer: TXPCU 655 Producer: TXDMA 656 657 1'b0: This is a normal frame and there are no restrictions 658 on the BW that this frame can be transmitted on. 659 660 1'b1: This MPDU is only allowed to be transmitted at certain 661 BWs. The one and only allowed BW is indicated in field 662 allowed_transmit_bw 663 When TXPCU has made a BW selection and then encounters this 664 frame, the frame will be dropped and TXPCU will continue 665 transmitting the next frame (assuming there is no BW restriction 666 on that one) 667 <legal all> 668 */ 669 670 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x0000000000000020 671 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1 672 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1 673 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x0000000000000002 674 675 676 /* Description ALLOWED_TRANSMIT_BW 677 678 Consumer: TXPCU 679 Producer: TXDMA 680 681 Field only valid when transmit_bw_restriction is set 682 683 TXDMA gets this from the three or four upper bits of the 684 "Sw_buffer_cookie" field from the TX_MPDU_DETAILS STRUCT 685 686 687 In case of NON punctured transmission: 688 allowed_transmit_bw[2:0] = 3'b000: 20 MHz TX only 689 allowed_transmit_bw[2:0] = 3'b001: 40 MHz TX only 690 allowed_transmit_bw[2:0] = 3'b010: 80 MHz TX only 691 allowed_transmit_bw[2:0] = 3'b011: 160 MHz TX only 692 allowed_transmit_bw[2:0] = 3'b100: 240 MHz TX only 693 allowed_transmit_bw[2:0] = 3'b101: 320 MHz TX only 694 allowed_transmit_bw[2:1] = 2'b11: reserved 695 696 In case of punctured transmission: 697 allowed_transmit_bw[3:0] = 4'b0000: pattern 0 only 698 allowed_transmit_bw[3:0] = 4'b0001: pattern 1 only 699 allowed_transmit_bw[3:0] = 4'b0010: pattern 2 only 700 allowed_transmit_bw[3:0] = 4'b0011: pattern 3 only 701 allowed_transmit_bw[3:0] = 4'b0100: pattern 4 only 702 allowed_transmit_bw[3:0] = 4'b0101: pattern 5 only 703 allowed_transmit_bw[3:0] = 4'b0110: pattern 6 only 704 allowed_transmit_bw[3:0] = 4'b0111: pattern 7 only 705 allowed_transmit_bw[3:0] = 4'b1000: pattern 8 only 706 allowed_transmit_bw[3:0] = 4'b1001: pattern 9 only 707 allowed_transmit_bw[3:0] = 4'b1010: pattern 10 only 708 allowed_transmit_bw[3:0] = 4'b1011: pattern 11 only 709 allowed_transmit_bw[3:2] = 2'b11: reserved 710 711 Note: a punctured transmission is indicated by the presence 712 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 713 714 <legal 0-11> 715 */ 716 717 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x0000000000000020 718 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2 719 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5 720 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x000000000000003c 721 722 723 /* Description TX_NOTIFY_FRAME 724 725 Consumer: TQM/PDG/TXOLE 726 Producer: FW/SW 727 728 When clear, this frame does not require any special handling. 729 730 731 When set, this MPDU contains an MSDU with the 'FW_tx_notify_frame' 732 field set. 733 This means this MPDU is a special frame that requires special 734 handling in TQM. 735 736 Note that FW/SW shall always set the amsdu_not_allowed bit 737 in 'TX_MSDU_DETAILS' for any notify frame. 738 739 <enum 0 NO_TX_NOTIFY> Not a notify frame 740 <enum 1 TX_HARD_NOTIFY> 741 <enum 2 TX_SOFT_NOTIFY> 742 <enum 3 TX_SEMI_HARD_NOTIFY> 743 <enum 4 TX_SEMI_HARD_NOTIFY_CURR_RATE> Rate cannot be overridden 744 by PDG 745 <legal 0-4> 746 */ 747 748 #define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x0000000000000020 749 #define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6 750 #define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8 751 #define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x00000000000001c0 752 753 754 /* Description RESERVED_8A 755 756 Bit 9: self_gen: 757 758 Field only used in the MAC-flexibility feature in TXPCU 759 and PHY microcode 760 761 0: Indicates a normal data MPDU 762 1: Indicates a self-gen MPDU 763 764 Not supported in Hamilton/Waikiki v1 765 <legal 0-1> 766 */ 767 768 #define TX_MPDU_START_RESERVED_8A_OFFSET 0x0000000000000020 769 #define TX_MPDU_START_RESERVED_8A_LSB 9 770 #define TX_MPDU_START_RESERVED_8A_MSB 31 771 #define TX_MPDU_START_RESERVED_8A_MASK 0x00000000fffffe00 772 773 774 /* Description TLV64_PADDING 775 776 Automatic DWORD padding inserted while converting TLV32 777 to TLV64 for 64 bit ARCH 778 <legal 0> 779 */ 780 781 #define TX_MPDU_START_TLV64_PADDING_OFFSET 0x0000000000000020 782 #define TX_MPDU_START_TLV64_PADDING_LSB 32 783 #define TX_MPDU_START_TLV64_PADDING_MSB 63 784 #define TX_MPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 785 786 787 788 #endif // TX_MPDU_START 789