1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _TX_PEER_ENTRY_H_ 27 #define _TX_PEER_ENTRY_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_TX_PEER_ENTRY 18 32 33 #define NUM_OF_QWORDS_TX_PEER_ENTRY 9 34 35 36 struct tx_peer_entry { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t mac_addr_a_31_0 : 32; // [31:0] 39 uint32_t mac_addr_a_47_32 : 16, // [15:0] 40 mac_addr_b_15_0 : 16; // [31:16] 41 uint32_t mac_addr_b_47_16 : 32; // [31:0] 42 uint32_t use_ad_b : 1, // [0:0] 43 strip_insert_vlan_inner : 1, // [1:1] 44 strip_insert_vlan_outer : 1, // [2:2] 45 vlan_llc_mode : 1, // [3:3] 46 key_type : 4, // [7:4] 47 a_msdu_wds_ad3_ad4 : 3, // [10:8] 48 ignore_hard_filters : 1, // [11:11] 49 ignore_soft_filters : 1, // [12:12] 50 epd_output : 1, // [13:13] 51 wds : 1, // [14:14] 52 insert_or_strip : 1, // [15:15] 53 sw_filter_id : 16; // [31:16] 54 uint32_t temporal_key_31_0 : 32; // [31:0] 55 uint32_t temporal_key_63_32 : 32; // [31:0] 56 uint32_t temporal_key_95_64 : 32; // [31:0] 57 uint32_t temporal_key_127_96 : 32; // [31:0] 58 uint32_t temporal_key_159_128 : 32; // [31:0] 59 uint32_t temporal_key_191_160 : 32; // [31:0] 60 uint32_t temporal_key_223_192 : 32; // [31:0] 61 uint32_t temporal_key_255_224 : 32; // [31:0] 62 uint32_t sta_partial_aid : 11, // [10:0] 63 transmit_vif : 4, // [14:11] 64 block_this_user : 1, // [15:15] 65 mesh_amsdu_mode : 2, // [17:16] 66 use_qos_alt_mute_mask : 1, // [18:18] 67 dl_ul_direction : 1, // [19:19] 68 reserved_12 : 12; // [31:20] 69 uint32_t insert_vlan_outer_tci : 16, // [15:0] 70 insert_vlan_inner_tci : 16; // [31:16] 71 uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] 72 uint32_t multi_link_addr_ad1_47_32 : 16, // [15:0] 73 multi_link_addr_ad2_15_0 : 16; // [31:16] 74 uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] 75 uint32_t multi_link_addr_crypto_enable : 1, // [0:0] 76 reserved_17a : 15, // [15:1] 77 sw_peer_id : 16; // [31:16] 78 #else 79 uint32_t mac_addr_a_31_0 : 32; // [31:0] 80 uint32_t mac_addr_b_15_0 : 16, // [31:16] 81 mac_addr_a_47_32 : 16; // [15:0] 82 uint32_t mac_addr_b_47_16 : 32; // [31:0] 83 uint32_t sw_filter_id : 16, // [31:16] 84 insert_or_strip : 1, // [15:15] 85 wds : 1, // [14:14] 86 epd_output : 1, // [13:13] 87 ignore_soft_filters : 1, // [12:12] 88 ignore_hard_filters : 1, // [11:11] 89 a_msdu_wds_ad3_ad4 : 3, // [10:8] 90 key_type : 4, // [7:4] 91 vlan_llc_mode : 1, // [3:3] 92 strip_insert_vlan_outer : 1, // [2:2] 93 strip_insert_vlan_inner : 1, // [1:1] 94 use_ad_b : 1; // [0:0] 95 uint32_t temporal_key_31_0 : 32; // [31:0] 96 uint32_t temporal_key_63_32 : 32; // [31:0] 97 uint32_t temporal_key_95_64 : 32; // [31:0] 98 uint32_t temporal_key_127_96 : 32; // [31:0] 99 uint32_t temporal_key_159_128 : 32; // [31:0] 100 uint32_t temporal_key_191_160 : 32; // [31:0] 101 uint32_t temporal_key_223_192 : 32; // [31:0] 102 uint32_t temporal_key_255_224 : 32; // [31:0] 103 uint32_t reserved_12 : 12, // [31:20] 104 dl_ul_direction : 1, // [19:19] 105 use_qos_alt_mute_mask : 1, // [18:18] 106 mesh_amsdu_mode : 2, // [17:16] 107 block_this_user : 1, // [15:15] 108 transmit_vif : 4, // [14:11] 109 sta_partial_aid : 11; // [10:0] 110 uint32_t insert_vlan_inner_tci : 16, // [31:16] 111 insert_vlan_outer_tci : 16; // [15:0] 112 uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] 113 uint32_t multi_link_addr_ad2_15_0 : 16, // [31:16] 114 multi_link_addr_ad1_47_32 : 16; // [15:0] 115 uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] 116 uint32_t sw_peer_id : 16, // [31:16] 117 reserved_17a : 15, // [15:1] 118 multi_link_addr_crypto_enable : 1; // [0:0] 119 #endif 120 }; 121 122 123 /* Description MAC_ADDR_A_31_0 124 125 Consumer: TX OLE 126 Producer: SW 127 128 Lower 32 bits of the MAC address A used by HW for encapsulating 129 802.11 130 <legal all> 131 */ 132 133 #define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET 0x0000000000000000 134 #define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB 0 135 #define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB 31 136 #define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK 0x00000000ffffffff 137 138 139 /* Description MAC_ADDR_A_47_32 140 141 Consumer: TX OLE 142 Producer: SW 143 144 Upper 16 bits of the MAC address A used by HW for encapsulating 145 802.11 146 <legal all> 147 */ 148 149 #define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET 0x0000000000000000 150 #define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB 32 151 #define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB 47 152 #define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK 0x0000ffff00000000 153 154 155 /* Description MAC_ADDR_B_15_0 156 157 Consumer: TX OLE 158 Producer: SW 159 160 Lower 16 bits of the MAC address B used by HW for encapsulating 161 802.11 162 <legal all> 163 */ 164 165 #define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET 0x0000000000000000 166 #define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB 48 167 #define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB 63 168 #define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK 0xffff000000000000 169 170 171 /* Description MAC_ADDR_B_47_16 172 173 Consumer: TX OLE 174 Producer: SW 175 176 Upper 32 bits of the MAC address B used by HW for encapsulating 177 802.11 178 <legal all> 179 */ 180 181 #define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET 0x0000000000000008 182 #define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB 0 183 #define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB 31 184 #define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK 0x00000000ffffffff 185 186 187 /* Description USE_AD_B 188 189 Consumer: TX OLE 190 Producer: SW 191 192 The bit is only evaluated when this MSDU is the first MSDU 193 in an MPDU. For other MSDUs this bit setting is ignored. 194 195 It is part of the sw_msdu_param coming from the QM ADD frame 196 command. 197 198 Normally in AP mode the DA address is used as the RA. This 199 is normally fine but the use_ad_b bit should be set when 200 DA is a multicast/broadcast address but we want to send 201 this packet using the destination STA address which will 202 be held in the mac_addr_b field of the peer descriptor. 203 204 <legal all> 205 */ 206 207 #define TX_PEER_ENTRY_USE_AD_B_OFFSET 0x0000000000000008 208 #define TX_PEER_ENTRY_USE_AD_B_LSB 32 209 #define TX_PEER_ENTRY_USE_AD_B_MSB 32 210 #define TX_PEER_ENTRY_USE_AD_B_MASK 0x0000000100000000 211 212 213 /* Description STRIP_INSERT_VLAN_INNER 214 215 Consumer: TX OLE 216 Producer: SW 217 218 Strip or insert C-VLAN during encapsulation. 219 Insert_or_strip determines whether C-VLAN is to be stripped 220 or inserted. 221 <legal all> 222 */ 223 224 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET 0x0000000000000008 225 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB 33 226 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB 33 227 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK 0x0000000200000000 228 229 230 /* Description STRIP_INSERT_VLAN_OUTER 231 232 Consumer: TX OLE 233 Producer: SW 234 235 Strip or insert S-VLAN during encapsulation. 236 Insert or strip determines whether S-VLAN is to be stripped 237 or inserted. 238 <legal all> 239 */ 240 241 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET 0x0000000000000008 242 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB 34 243 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB 34 244 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK 0x0000000400000000 245 246 247 /* Description VLAN_LLC_MODE 248 249 Consumer: TX OLE 250 Producer: SW 251 252 If set encapsulate/decapsulate using the Scorpion compatible 253 VLAN LLC format 254 */ 255 256 #define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET 0x0000000000000008 257 #define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB 35 258 #define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB 35 259 #define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK 0x0000000800000000 260 261 262 /* Description KEY_TYPE 263 264 Consumer: TX OLE, TX CRYPTO 265 Producer: SW 266 267 The key_type indicates the cipher suite corresponding to 268 this peer entry: 269 <enum 0 wep_40> WEP 40-bit 270 <enum 1 wep_104> WEP 104-bit 271 <enum 2 tkip_no_mic> TKIP without MIC 272 <enum 3 wep_128> WEP 128-bit 273 <enum 4 tkip_with_mic> TKIP with MIC 274 <enum 5 wapi> WAPI 275 <enum 6 aes_ccmp_128> AES CCMP 128 276 <enum 7 no_cipher> No crypto 277 <enum 8 aes_ccmp_256> AES CCMP 256 278 <enum 9 aes_gcmp_128> AES GCMP 128 279 <enum 10 aes_gcmp_256> AES GCMP 256 280 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 281 282 <enum 12 wep_varied_width> DO NOT USE. This Key type ONLY 283 to be used for RX side 284 285 <legal 0-12> 286 */ 287 288 #define TX_PEER_ENTRY_KEY_TYPE_OFFSET 0x0000000000000008 289 #define TX_PEER_ENTRY_KEY_TYPE_LSB 36 290 #define TX_PEER_ENTRY_KEY_TYPE_MSB 39 291 #define TX_PEER_ENTRY_KEY_TYPE_MASK 0x000000f000000000 292 293 294 /* Description A_MSDU_WDS_AD3_AD4 295 296 Consumer: TX OLE 297 Producer: SW 298 299 Determines the selection of AD3 and AD4 for A-MSDU 4 address 300 frames (WDS): 301 <enum 0 ad3_a__ad4_a> AD3 = AD_A, AD4 = AD_A 302 <enum 1 ad3_a__ad4_b> AD3 = AD_A, AD4 = AD_B 303 <enum 2 ad3_b__ad4_a> AD3 = AD_B, AD4 = AD_A 304 <enum 3 ad3_b__ad4_b> AD3 = AD_B, AD4 = AD_B 305 <enum 4 ad3_da__ad4_sa> AD3 = DA, AD4 = SA 306 <legal 0-4> 307 */ 308 309 #define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET 0x0000000000000008 310 #define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB 40 311 #define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB 42 312 #define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK 0x0000070000000000 313 314 315 /* Description IGNORE_HARD_FILTERS 316 317 SW can program this bit to 0x1 to ignore HARD filter conditions 318 and HWSCH will proceed with transmission, even if the HARD 319 filter bit is set in Filter LUT. 320 Note that SOFT filter conditions will filter the command, 321 even if this bit is set and ignore_soft_filters is not set 322 323 For filtering all frames marked in the Filter LUT, both 324 ignore_soft_filters and ignore_hard_filters should be set 325 326 <legal all> 327 */ 328 329 #define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET 0x0000000000000008 330 #define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB 43 331 #define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB 43 332 #define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK 0x0000080000000000 333 334 335 /* Description IGNORE_SOFT_FILTERS 336 337 SW can program this bit to 0x1 to ignore SOFT filter conditions 338 and HWSCH will proceed with transmission, even if the SOFT 339 filter bit is set in Filter LUT. 340 Note that HARD filter conditions will filter the command, 341 even if this bit is set and ignore_hard_filters is not set 342 343 For filtering all frames marked in the Filter LUT, both 344 ignore_soft_filters and ignore_hard_filters should be set 345 346 347 <legal all> 348 */ 349 350 #define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET 0x0000000000000008 351 #define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB 44 352 #define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB 44 353 #define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK 0x0000100000000000 354 355 356 /* Description EPD_OUTPUT 357 358 Consumer: TX OLE 359 Producer: SW 360 361 If set use EPD instead of LPD 362 */ 363 364 #define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET 0x0000000000000008 365 #define TX_PEER_ENTRY_EPD_OUTPUT_LSB 45 366 #define TX_PEER_ENTRY_EPD_OUTPUT_MSB 45 367 #define TX_PEER_ENTRY_EPD_OUTPUT_MASK 0x0000200000000000 368 369 370 /* Description WDS 371 372 If set all the frames in this transmission (for this user) 373 are 4-address frame. 374 375 If not all frames need to use 4 address format, SW has per 376 frame 'wds' control, by using the 'wds' flag in the MSDU_EXTENSION 377 descriptor 378 379 Used by the OLE during encapsulation. 380 <legal all> 381 */ 382 383 #define TX_PEER_ENTRY_WDS_OFFSET 0x0000000000000008 384 #define TX_PEER_ENTRY_WDS_LSB 46 385 #define TX_PEER_ENTRY_WDS_MSB 46 386 #define TX_PEER_ENTRY_WDS_MASK 0x0000400000000000 387 388 389 /* Description INSERT_OR_STRIP 390 391 <enum 0 TXOLE_STRIP_VLAN> TXOLE will strip inner or outer 392 VLAN (if present in the frame) based on Strip_insert_vlan_{inner, 393 outer} 394 <enum 1 TXOLE_INSERT_VLAN> TXOLE will insert inner or outer 395 VLAN (only if absent in the frame) based on Strip_insert_vlan_{inner, 396 outer} with the TCI(s) given by Insert_vlan_{inner, outer}_tci 397 398 NOTE: Strip VLAN is not supported by TCL. 399 <legal all> 400 */ 401 402 #define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET 0x0000000000000008 403 #define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB 47 404 #define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB 47 405 #define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK 0x0000800000000000 406 407 408 /* Description SW_FILTER_ID 409 410 Consumer: SCH 411 Producer: SW 412 413 The full STA AID. 414 Use by SCH to determine if transmission for this STA should 415 be filtered as it just went into power save state. 416 In case of MU transmission, it means only this STA needs 417 to be removed from the transmission... 418 419 <legal all> 420 */ 421 422 #define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET 0x0000000000000008 423 #define TX_PEER_ENTRY_SW_FILTER_ID_LSB 48 424 #define TX_PEER_ENTRY_SW_FILTER_ID_MSB 63 425 #define TX_PEER_ENTRY_SW_FILTER_ID_MASK 0xffff000000000000 426 427 428 /* Description TEMPORAL_KEY_31_0 429 430 Consumer: TX CRYPTO 431 Producer: SW 432 433 First 32 bits of the temporal key material. The temporal 434 key for WEP 40-bit uses the first 40 bits, WEP 104-bit 435 uses the first 104 bits, WEP 128-bit uses all 128 bits, 436 TKIP with/without MIC uses 128 bits, WAPI uses all 128 bits, 437 and AES-CCM uses all 128 bits. 438 439 Note that for TKIP, the 64 MIC bits are located in fields 440 'temporal_key[255:192] 441 <legal all> 442 */ 443 444 #define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET 0x0000000000000010 445 #define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB 0 446 #define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB 31 447 #define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK 0x00000000ffffffff 448 449 450 /* Description TEMPORAL_KEY_63_32 451 452 Consumer: TX CRYPTO 453 Producer: SW 454 455 Second 32 bits of the temporal key material. See the description 456 of temporal_key_31_0. 457 <legal all> 458 */ 459 460 #define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET 0x0000000000000010 461 #define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB 32 462 #define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB 63 463 #define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK 0xffffffff00000000 464 465 466 /* Description TEMPORAL_KEY_95_64 467 468 Consumer: TX CRYPTO 469 Producer: SW 470 471 Third 32 bits of the temporal key material. See the description 472 of temporal_key_31_0. 473 <legal all> 474 */ 475 476 #define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET 0x0000000000000018 477 #define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB 0 478 #define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB 31 479 #define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK 0x00000000ffffffff 480 481 482 /* Description TEMPORAL_KEY_127_96 483 484 Consumer: TX CRYPTO 485 Producer: SW 486 487 Fourth 32 bits of the temporal key material. See the description 488 of temporal_key_31_0. 489 <legal all> 490 */ 491 492 #define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET 0x0000000000000018 493 #define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB 32 494 #define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB 63 495 #define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK 0xffffffff00000000 496 497 498 /* Description TEMPORAL_KEY_159_128 499 500 Consumer: TX CRYPTO 501 Producer: SW 502 503 Fifth 32 bits of the temporal key material. See the description 504 of temporal_key_31_0. 505 506 <legal all> 507 */ 508 509 #define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET 0x0000000000000020 510 #define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB 0 511 #define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB 31 512 #define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK 0x00000000ffffffff 513 514 515 /* Description TEMPORAL_KEY_191_160 516 517 Consumer: TX CRYPTO 518 Producer: SW 519 520 Final 32 bits of the temporal key material. See the description 521 of temporal_key_31_0. 522 523 <legal all> 524 */ 525 526 #define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET 0x0000000000000020 527 #define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB 32 528 #define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB 63 529 #define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK 0xffffffff00000000 530 531 532 /* Description TEMPORAL_KEY_223_192 533 534 Consumer: TX CRYPTO 535 Producer: SW 536 537 Final 32 bits of the temporal key material. See the description 538 of temporal_key_31_0. 539 540 For TKIP this is the TX MIC key[31:0]. 541 <legal all> 542 */ 543 544 #define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET 0x0000000000000028 545 #define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB 0 546 #define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB 31 547 #define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK 0x00000000ffffffff 548 549 550 /* Description TEMPORAL_KEY_255_224 551 552 Consumer: TX CRYPTO 553 Producer: SW 554 555 Final 32 bits of the temporal key material. See the description 556 of temporal_key_31_0. 557 558 For TKIP this is the TX MIC key[63:32]. 559 <legal all> 560 */ 561 562 #define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET 0x0000000000000028 563 #define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB 32 564 #define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB 63 565 #define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK 0xffffffff00000000 566 567 568 /* Description STA_PARTIAL_AID 569 570 This field in only used by the PDG. All other modules should 571 ignore this field. 572 573 This field is only valid in case of a transmission at VHT 574 rates or HE rates. 575 576 For VHT: 577 This field is the Partial AID to be filled in to the VHT 578 preamble. 579 580 For HE: 581 This field is the sta_aid to be filled into the SIG B field. 582 583 584 In 11ah mode of operation, this field is provided by SW 585 to populate the the ID value of the SIG preamble of the 586 PPDU 587 */ 588 589 #define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET 0x0000000000000030 590 #define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB 0 591 #define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB 10 592 #define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK 0x00000000000007ff 593 594 595 /* Description TRANSMIT_VIF 596 597 Consumer: TXOLE 598 Producer: SW 599 600 The VIF for this transmission. Used in MCC mode to control/overwrite 601 the PM bit settings. 602 <legal all> 603 */ 604 605 #define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET 0x0000000000000030 606 #define TX_PEER_ENTRY_TRANSMIT_VIF_LSB 11 607 #define TX_PEER_ENTRY_TRANSMIT_VIF_MSB 14 608 #define TX_PEER_ENTRY_TRANSMIT_VIF_MASK 0x0000000000007800 609 610 611 /* Description BLOCK_THIS_USER 612 613 Consumer: PDG 614 Producer: SCH 615 616 Set by SCH when a MU transmission is started and this STA 617 has (just) entered or is in power save mode. 618 Due to the MU transmission SCH shall not terminate this 619 MU transmission (as is done with SU transmission), but continue 620 with the transmissions for all other STAs. 621 622 As a result of this bit being set, PDG will at certain moment 623 generate the MPDU limit TLV with field Num_mpdu_user set 624 to 0 625 626 PDG shall treat this user as a user without any data. All 627 rules related to terminating MU transmissions when too 628 many users do not have any data shall include this user 629 as a user having zero data. 630 631 When clear, PDG can ignore this bit 632 <legal all> 633 */ 634 635 #define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET 0x0000000000000030 636 #define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB 15 637 #define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB 15 638 #define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK 0x0000000000008000 639 640 641 /* Description MESH_AMSDU_MODE 642 643 Consumer: TX OLE 644 Producer: SW 645 646 This field is used only when the first MSDU of any MPDU 647 that TX OLE encounters is in Native WiFi format and includes 648 a 'Mesh Control' field between the header and the LLC. 649 650 The creation of the A-MSDU 'Length' field in the MPDU (if 651 aggregating multiple MSDUs) is decided by the value of 652 this field. 653 654 <enum 0 MESH_MODE_0> DO NOT USE 655 <enum 1 MESH_MODE_Q2Q> A-MSDU 'Length' is big endian and 656 includes the length of Mesh Control. 657 <enum 2 MESH_MODE_11S_BE> A-MSDU 'Length' is big endian 658 and excludes the length of Mesh Control. 659 <enum 3 MESH_MODE_11S_LE> A-MSDU 'Length' is little endian 660 and excludes the length of Mesh Control. This is 802.11s-compliant. 661 662 663 NOTE 1: For compatibility TXOLE treats MESH_MODE_0 identically 664 to MESH_MODE_Q2Q. 665 666 NOTE 2: This e-numeration is different from other fields 667 named Mesh_sta or mesh_enable where the value zero disables 668 mesh processing. 669 <legal 0-3> 670 */ 671 672 #define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET 0x0000000000000030 673 #define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB 16 674 #define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB 17 675 #define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK 0x0000000000030000 676 677 678 /* Description USE_QOS_ALT_MUTE_MASK 679 680 Lithium and prior generation WAPI implementations did not 681 mute any QoS Control bits when generating the AAD. Setting 682 this bit chooses an alternative configurable QoS Control 683 mute mask in Crypto for compatibility with those chips. 684 685 686 For AES, alternative configurable QoS Control mute mask 687 is required in Crypto to support SPP A-MSDUs for increased 688 security. 689 690 <legal all> 691 */ 692 693 #define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET 0x0000000000000030 694 #define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB 18 695 #define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB 18 696 #define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK 0x0000000000040000 697 698 699 /* Description DL_UL_DIRECTION 700 701 'Direction' to be inferred for raw WiFi esp. management 702 frames sent to a multi-link peer, for translating RA and/or 703 TA. 704 705 <enum 0 DL_UL_FLAG_IS_DL_OR_TDLS> 706 <enum 1 DL_UL_FLAG_IS_UL> 707 <legal all> 708 */ 709 710 #define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET 0x0000000000000030 711 #define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB 19 712 #define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB 19 713 #define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK 0x0000000000080000 714 715 716 /* Description RESERVED_12 717 718 <legal 0> 719 */ 720 721 #define TX_PEER_ENTRY_RESERVED_12_OFFSET 0x0000000000000030 722 #define TX_PEER_ENTRY_RESERVED_12_LSB 20 723 #define TX_PEER_ENTRY_RESERVED_12_MSB 31 724 #define TX_PEER_ENTRY_RESERVED_12_MASK 0x00000000fff00000 725 726 727 /* Description INSERT_VLAN_OUTER_TCI 728 729 The tag control info to use when TXOLE inserts outer VLAN 730 if enabled by Strip_insert_vlan_outer and Insert_or_strip 731 732 */ 733 734 #define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET 0x0000000000000030 735 #define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB 32 736 #define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB 47 737 #define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK 0x0000ffff00000000 738 739 740 /* Description INSERT_VLAN_INNER_TCI 741 742 The tag control info to use when TXOLE inserts inner VLAN 743 if enabled by Strip_insert_vlan_inner and Insert_or_strip 744 745 */ 746 747 #define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET 0x0000000000000030 748 #define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB 48 749 #define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB 63 750 #define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK 0xffff000000000000 751 752 753 /* Description MULTI_LINK_ADDR_AD1_31_0 754 755 Consumer: TX CRYPTO 756 Producer: FW 757 758 Field only valid if Multi_link_addr_crypto_enable is set 759 760 761 Multi-link receiver address (address1) for transmissions 762 matching this peer entry, bits [31:0] 763 */ 764 765 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_OFFSET 0x0000000000000038 766 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_LSB 0 767 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_MSB 31 768 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_MASK 0x00000000ffffffff 769 770 771 /* Description MULTI_LINK_ADDR_AD1_47_32 772 773 Consumer: TX CRYPTO 774 Producer: FW 775 776 Field only valid if Multi_link_addr_crypto_enable is set 777 778 779 Multi-link receiver address (address1) for transmissions 780 matching this peer entry, bits [47:32] 781 */ 782 783 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_OFFSET 0x0000000000000038 784 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_LSB 32 785 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_MSB 47 786 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_MASK 0x0000ffff00000000 787 788 789 /* Description MULTI_LINK_ADDR_AD2_15_0 790 791 Consumer: TX CRYPTO 792 Producer: FW 793 794 Field only valid if Multi_link_addr_crypto_enable is set 795 796 797 Multi-link transmitter address (address2) for transmissions 798 matching this peer entry, bits [15:0] 799 */ 800 801 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_OFFSET 0x0000000000000038 802 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_LSB 48 803 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_MSB 63 804 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_MASK 0xffff000000000000 805 806 807 /* Description MULTI_LINK_ADDR_AD2_47_16 808 809 Consumer: TX CRYPTO 810 Producer: FW 811 812 Field only valid if Multi_link_addr_crypto_enable is set 813 814 815 Multi-link transmitter address (address2) for transmissions 816 matching this peer entry, bits [47:16] 817 */ 818 819 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_OFFSET 0x0000000000000040 820 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_LSB 0 821 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_MSB 31 822 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_MASK 0x00000000ffffffff 823 824 825 /* Description MULTI_LINK_ADDR_CRYPTO_ENABLE 826 827 Consumer: TX CRYPTO 828 Producer: FW 829 830 If set, TX CRYPTO shall convert Address1, Address2 and BSSID 831 of received data frames to multi-link addresses for the 832 AAD and Nonce during encryption. 833 <legal all> 834 */ 835 836 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET 0x0000000000000040 837 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB 32 838 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB 32 839 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK 0x0000000100000000 840 841 842 /* Description RESERVED_17A 843 844 <legal 0> 845 */ 846 847 #define TX_PEER_ENTRY_RESERVED_17A_OFFSET 0x0000000000000040 848 #define TX_PEER_ENTRY_RESERVED_17A_LSB 33 849 #define TX_PEER_ENTRY_RESERVED_17A_MSB 47 850 #define TX_PEER_ENTRY_RESERVED_17A_MASK 0x0000fffe00000000 851 852 853 /* Description SW_PEER_ID 854 855 This field indicates a unique peer identifier provided by 856 FW, to be logged via TXMON to host SW. 857 858 <legal all> 859 */ 860 861 #define TX_PEER_ENTRY_SW_PEER_ID_OFFSET 0x0000000000000040 862 #define TX_PEER_ENTRY_SW_PEER_ID_LSB 48 863 #define TX_PEER_ENTRY_SW_PEER_ID_MSB 63 864 #define TX_PEER_ENTRY_SW_PEER_ID_MASK 0xffff000000000000 865 866 867 868 #endif // TX_PEER_ENTRY 869