1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _TX_QUEUE_EXTENSION_H_ 27 #define _TX_QUEUE_EXTENSION_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 14 32 33 #define NUM_OF_QWORDS_TX_QUEUE_EXTENSION 7 34 35 36 struct tx_queue_extension { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t frame_ctl : 16, // [15:0] 39 qos_ctl : 16; // [31:16] 40 uint32_t ampdu_flag : 1, // [0:0] 41 tx_notify_no_htc_override : 1, // [1:1] 42 reserved_1a : 7, // [8:2] 43 checksum_tso_disable_for_frag : 1, // [9:9] 44 key_id : 8, // [17:10] 45 qos_buf_state_overwrite : 1, // [18:18] 46 buf_state_sta_id : 1, // [19:19] 47 buf_state_source : 1, // [20:20] 48 ht_control_overwrite_enable : 1, // [21:21] 49 ht_control_overwrite_source : 4, // [25:22] 50 reserved_1b : 6; // [31:26] 51 uint32_t ul_headroom_insertion_enable : 1, // [0:0] 52 ul_headroom_offset : 5, // [5:1] 53 bqrp_insertion_enable : 1, // [6:6] 54 bqrp_offset : 5, // [11:7] 55 ul_headroom_rsvd_7_6 : 2, // [13:12] 56 bqr_rsvd_9_8 : 2, // [15:14] 57 base_pn_63_48 : 16; // [31:16] 58 uint32_t base_pn_95_64 : 32; // [31:0] 59 uint32_t base_pn_127_96 : 32; // [31:0] 60 uint32_t ht_control_field_bw20 : 32; // [31:0] 61 uint32_t ht_control_field_bw40 : 32; // [31:0] 62 uint32_t ht_control_field_bw80 : 32; // [31:0] 63 uint32_t ht_control_field_bw160 : 32; // [31:0] 64 uint32_t ht_control_overwrite_mask : 32; // [31:0] 65 uint32_t cas_control_info : 8, // [7:0] 66 cas_offset : 5, // [12:8] 67 cas_insertion_enable : 1, // [13:13] 68 reserved_10a : 2, // [15:14] 69 ht_control_overwrite_source_for_srp : 4, // [19:16] 70 ht_control_overwrite_source_for_bsrp : 4, // [23:20] 71 reserved_10b : 6, // [29:24] 72 mpdu_hdr_len_override_en : 1, // [30:30] 73 bar_ssn_overwrite_enable : 1; // [31:31] 74 uint32_t bar_ssn_offset : 12, // [11:0] 75 mpdu_hdr_len_override_val : 9, // [20:12] 76 reserved_11a : 11; // [31:21] 77 uint32_t ht_control_field_bw320 : 32; // [31:0] 78 uint32_t fw2sw_info : 32; // [31:0] 79 #else 80 uint32_t qos_ctl : 16, // [31:16] 81 frame_ctl : 16; // [15:0] 82 uint32_t reserved_1b : 6, // [31:26] 83 ht_control_overwrite_source : 4, // [25:22] 84 ht_control_overwrite_enable : 1, // [21:21] 85 buf_state_source : 1, // [20:20] 86 buf_state_sta_id : 1, // [19:19] 87 qos_buf_state_overwrite : 1, // [18:18] 88 key_id : 8, // [17:10] 89 checksum_tso_disable_for_frag : 1, // [9:9] 90 reserved_1a : 7, // [8:2] 91 tx_notify_no_htc_override : 1, // [1:1] 92 ampdu_flag : 1; // [0:0] 93 uint32_t base_pn_63_48 : 16, // [31:16] 94 bqr_rsvd_9_8 : 2, // [15:14] 95 ul_headroom_rsvd_7_6 : 2, // [13:12] 96 bqrp_offset : 5, // [11:7] 97 bqrp_insertion_enable : 1, // [6:6] 98 ul_headroom_offset : 5, // [5:1] 99 ul_headroom_insertion_enable : 1; // [0:0] 100 uint32_t base_pn_95_64 : 32; // [31:0] 101 uint32_t base_pn_127_96 : 32; // [31:0] 102 uint32_t ht_control_field_bw20 : 32; // [31:0] 103 uint32_t ht_control_field_bw40 : 32; // [31:0] 104 uint32_t ht_control_field_bw80 : 32; // [31:0] 105 uint32_t ht_control_field_bw160 : 32; // [31:0] 106 uint32_t ht_control_overwrite_mask : 32; // [31:0] 107 uint32_t bar_ssn_overwrite_enable : 1, // [31:31] 108 mpdu_hdr_len_override_en : 1, // [30:30] 109 reserved_10b : 6, // [29:24] 110 ht_control_overwrite_source_for_bsrp : 4, // [23:20] 111 ht_control_overwrite_source_for_srp : 4, // [19:16] 112 reserved_10a : 2, // [15:14] 113 cas_insertion_enable : 1, // [13:13] 114 cas_offset : 5, // [12:8] 115 cas_control_info : 8; // [7:0] 116 uint32_t reserved_11a : 11, // [31:21] 117 mpdu_hdr_len_override_val : 9, // [20:12] 118 bar_ssn_offset : 12; // [11:0] 119 uint32_t ht_control_field_bw320 : 32; // [31:0] 120 uint32_t fw2sw_info : 32; // [31:0] 121 #endif 122 }; 123 124 125 /* Description FRAME_CTL 126 127 Consumer: TXOLE 128 Producer: SW 129 130 131 802.11 Frame control field: 132 fc [1:0]: Protocol Version 133 fc[7:2]: type/subtypeFor non-11ah fc[3:2] = Type fc[7:4] = 134 Subtype For 11ah fc[4:2] = Typefc[7:5] = PTID/SubType 135 fc [8]: To DS ( for Non-11ah) From DS ( for 11ah ) 136 fc [9]: From DS ( for Non-11ah ) 137 More Frag ( for 11ah ) 138 fc [10]: More Frag ( for Non-11ah ) 139 Power Management ( for 11ah) 140 fc [11]: Retry ( for Non-11ah ) 141 More Data ( for 11ah ) 142 fc [12]: Pwr Mgt ( for Non-11ah ) 143 Protected Frame ( for 11ah ) 144 fc [13]: More Data( for Non-11ah ) 145 EOSP ( for 11ah ) 146 fc [14]: Protected Frame ( for Non-11ah) 147 Relayed Frame ( for 11ah ) 148 fc [15]: Order ( for Non-11ah ) 149 Ack Policy ( for 11ah ) 150 Used by OLE during the encapsulation process for Native 151 WiFi, Ethernet II, and 802.3. 152 When the Order field is set, TXOLE shall insert 4 placeholder 153 bytes for the HE-control field in the frame. TXPCU will 154 overwrite them with the final actual value... 155 */ 156 157 #define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET 0x0000000000000000 158 #define TX_QUEUE_EXTENSION_FRAME_CTL_LSB 0 159 #define TX_QUEUE_EXTENSION_FRAME_CTL_MSB 15 160 #define TX_QUEUE_EXTENSION_FRAME_CTL_MASK 0x000000000000ffff 161 162 163 /* Description QOS_CTL 164 165 Consumer: TXOLE 166 Producer: SW 167 168 QoS control field is valid if the type field is data and 169 the upper bit of the subtype field is set. The field decode 170 is as below: 171 qos_ctl[3:0]: TID 172 qos_ctl[4]: EOSP (with some exceptions) 173 qos_ctl[6:5]: Ack Policy 174 0x0: Normal Ack or Implicit BAR 175 0x1: No Ack 176 0x2: No explicit Ack or PSMP Ack (not supported) 177 0x3: Block Ack (Not supported) 178 Qos_ctl[7]: A-MSDU Present (with some exceptions) 179 Qos_ctl[15:8]: TXOP limit, AP PS buffer state, TXOP duration 180 requested or queue size 181 This field is inserted into the 802.11 header during the 182 encapsulation process 183 <legal all> 184 */ 185 186 #define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET 0x0000000000000000 187 #define TX_QUEUE_EXTENSION_QOS_CTL_LSB 16 188 #define TX_QUEUE_EXTENSION_QOS_CTL_MSB 31 189 #define TX_QUEUE_EXTENSION_QOS_CTL_MASK 0x00000000ffff0000 190 191 192 /* Description AMPDU_FLAG 193 194 Consumer: PDG/TXPCU 195 Producer: SW 196 197 Note: 198 For legacy rate transmissions (11 b and 11a, an 11g), this 199 bit shall always be set to zero. 200 201 0: 202 For legacy and .11n rates: 203 MPDUs are only allowed to be sent out 1 at a time in NON 204 A-MPDU format. 205 For .11ac and .11ax rates: 206 MPDUs are sent out in S-MPDU format (TXPCU sets the 'EOF' 207 bit in the MPDU delimiter). 208 1: All MPDUs should be sent out using the A-MPDU format, 209 even if there is only one MPDU. 210 211 Note that this bit should be set to 0 in order to construct 212 an S-MPDU frame. VHT and HE frames are all A-MPDU format 213 but if this bit is clear, EOF bit is set to 1 for the MPDU 214 delimiter in A-MPDU, which is the indicator of S-MPDU and 215 solicits ACK rather than BA as response frame. 216 217 This bit shall be set to 1 for any MD (Multi Destination) 218 transmission. 219 */ 220 221 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET 0x0000000000000000 222 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB 32 223 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB 32 224 #define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK 0x0000000100000000 225 226 227 /* Description TX_NOTIFY_NO_HTC_OVERRIDE 228 229 When set, and a 'TX_MPDU_START' TLV has Tx_notify_frame 230 set to TX_HARD_NOTIFY or TX_SOFT_NOTIFY or TX_SEMI_HARD_NOTIFY, 231 then PDG would have updated the rate fields for a legacy 232 PPDU which may not support HT Control. 233 234 In this case TXOLE shall not: 235 set the Order/+HTC bit in the 'Frame Control,' 236 include 4 bytes for TXPCU to fill the HT Control, or 237 set vht_control_present in 'TX_MPDU_START,' 238 even if requested, and instead shall subtract '4' from the 239 mpdu_length in 'TX_MPDU_START' and overwrite it. 240 241 Hamilton v1 used bits [29:26], [8:1] along with word 11 242 bits [31:12] for 'HT_control_field_bw320.' 243 <legal all> 244 */ 245 246 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET 0x0000000000000000 247 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB 33 248 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB 33 249 #define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK 0x0000000200000000 250 251 252 /* Description RESERVED_1A 253 254 Hamilton v1 used bits [29:26], [8:1] along with word 11 255 bits [31:12] for 'HT_control_field_bw320.' 256 <legal 0> 257 */ 258 259 #define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET 0x0000000000000000 260 #define TX_QUEUE_EXTENSION_RESERVED_1A_LSB 34 261 #define TX_QUEUE_EXTENSION_RESERVED_1A_MSB 40 262 #define TX_QUEUE_EXTENSION_RESERVED_1A_MASK 0x000001fc00000000 263 264 265 /* Description CHECKSUM_TSO_DISABLE_FOR_FRAG 266 267 Field only valid in case of level-1 fragmentation, identified 268 by TXOLE getting the 'TX_FRAG_STATE' TLV 269 270 If set, TXOLE disables all checksum and TSO overwrites for 271 the fragment(s) being transmitted. 272 273 This is useful if it is known that the checksum and TSO 274 overwrites affect only the first fragment (or first few 275 fragments) and for the rest these can be safely disabled. 276 277 278 <legal all> 279 */ 280 281 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET 0x0000000000000000 282 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB 41 283 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB 41 284 #define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK 0x0000020000000000 285 286 287 /* Description KEY_ID 288 289 Field only valid in case of encryption, and TXOLE being 290 instructured to insert the IV. 291 292 TXOLE blindly copies this field into the key ID octet (which 293 is part of the IV) of the encrypted frame. 294 295 For AES/TKIP the encoding is: 296 key_id_octet[7:6]: key ID 297 key_id_octet[5]: extended IV: 298 key_id_octet[4:0]: Reserved bits 299 300 For WEP the encoding is: 301 key_id_octet[7:6]: key ID 302 key_id_octet[5]: extended IV: 303 key_id_octet[4:0]: Reserved bits 304 305 For WAPI the encoding is: 306 key_id_octet[7:2]: Reserved bits 307 key_id_octet[1:0]: key ID 308 309 <legal all> 310 */ 311 312 #define TX_QUEUE_EXTENSION_KEY_ID_OFFSET 0x0000000000000000 313 #define TX_QUEUE_EXTENSION_KEY_ID_LSB 42 314 #define TX_QUEUE_EXTENSION_KEY_ID_MSB 49 315 #define TX_QUEUE_EXTENSION_KEY_ID_MASK 0x0003fc0000000000 316 317 318 /* Description QOS_BUF_STATE_OVERWRITE 319 320 When clear, TXPCU shall not overwrite buffer state field 321 in the QoS frame control field. 322 323 When set, TXPCU shall overwrite the buffer state field in 324 the QoS frame control field, with info that SW has programmed 325 in TXPCU registers. Note that TXPCU shall pick up the values 326 related to this TID. 327 <legal all> 328 */ 329 330 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET 0x0000000000000000 331 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB 50 332 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB 50 333 #define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK 0x0004000000000000 334 335 336 /* Description BUF_STATE_STA_ID 337 338 Field only valid when QoS_Buf_state_overwrite is set. 339 340 This field indicates what the STA ID register source is 341 of the buffer status. 342 343 1'b0: TXPCU registers: STA0_buf_status_... 344 1'b1: TXPCU registers: STA1_buf_status_... 345 <legal all> 346 */ 347 348 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET 0x0000000000000000 349 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB 51 350 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB 51 351 #define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK 0x0008000000000000 352 353 354 /* Description BUF_STATE_SOURCE 355 356 Field only valid when QoS_Buf_state_overwrite is set. 357 358 This field indicates what the source is of the actual value 359 TXPCU will insert 360 361 <enum 0 BUF_STATE_TID_BASED> TXPCU looks at the TID field 362 in the QoS control frame and based on this TID, selects 363 the buffer source value from the corresponding TID register. 364 365 <enum 1 BUF_STATE_SUM_BASED> TXPCU inserts the value from 366 the buffer_state_sum register 367 368 <legal all> 369 */ 370 371 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET 0x0000000000000000 372 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB 52 373 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB 52 374 #define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK 0x0010000000000000 375 376 377 /* Description HT_CONTROL_OVERWRITE_ENABLE 378 379 When set, TXPCU shall overwrite some (or all) of the HT_CONTROL 380 field with values that are programmed in TXPCU registers: 381 HT_CONTROL_OVERWRITE_IX??? 382 383 See HT/HE control overwrite order NOTE after this table 384 385 <legal all> 386 */ 387 388 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET 0x0000000000000000 389 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB 53 390 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB 53 391 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK 0x0020000000000000 392 393 394 /* Description HT_CONTROL_OVERWRITE_SOURCE 395 396 Field only valid when HT_control_overwrite_enable is set. 397 398 399 This field indicates the index of the TXPCU register HT_CONTROL_OVERWRITE_IX??? 400 That is the source of the overwrite data. 401 <legal all> 402 */ 403 404 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET 0x0000000000000000 405 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB 54 406 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB 57 407 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK 0x03c0000000000000 408 409 410 /* Description RESERVED_1B 411 412 Hamilton v1 used bits [29:26], [8:1] along with word 11 413 bits [31:12] for 'HT_control_field_bw320.' 414 <legal 0> 415 */ 416 417 #define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET 0x0000000000000000 418 #define TX_QUEUE_EXTENSION_RESERVED_1B_LSB 58 419 #define TX_QUEUE_EXTENSION_RESERVED_1B_MSB 63 420 #define TX_QUEUE_EXTENSION_RESERVED_1B_MASK 0xfc00000000000000 421 422 423 /* Description UL_HEADROOM_INSERTION_ENABLE 424 425 When set, and this transmission services a trigger response 426 transmission, TXPCU shall create and insert the UL headroom 427 info in the HE control field, starting at offset indicated 428 by field: UL_headroom_offset 429 430 See HT/HE control overwrite order NOTE after this table 431 <legal all> 432 */ 433 434 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET 0x0000000000000008 435 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB 0 436 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB 0 437 #define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK 0x0000000000000001 438 439 440 /* Description UL_HEADROOM_OFFSET 441 442 Field only valid when UL_headroom_insertion_enable is set. 443 444 445 The bit location in HE_CONTROL Field where TXPCU will start 446 writing the the 4 bit Control ID field that needs to be 447 inserted, followed by the lower 6 bits of the 8 bit bit 448 UL_headroom info (UPH Control). 449 450 NOTE: currently on 6 bits are defined in the UPH control 451 field. The upper two bits are provided by SW in UL_headroom_rsvd_7_6. 452 453 454 <legal 2-20> 455 */ 456 457 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET 0x0000000000000008 458 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB 1 459 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB 5 460 #define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK 0x000000000000003e 461 462 463 /* Description BQRP_INSERTION_ENABLE 464 465 When set, and this transmission services a BQRP trigger 466 response transmission, TXPCU shall create and insert the 467 BQR control field into the HE control field, as well as 468 the 4 bit preceding Control ID field. 469 470 See HT/HE control overwrite order NOTE after this table 471 <legal all> 472 */ 473 474 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET 0x0000000000000008 475 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB 6 476 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB 6 477 #define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK 0x0000000000000040 478 479 480 /* Description BQRP_OFFSET 481 482 Field only valid when BQRP_insertion_enable is set. 483 484 The bit location in HE_CONTROL Field where TXPCU will start 485 writing the 4 bit Control ID field that needs to be inserted, 486 followed by the lower 8 bits of the 10 bit BQR control field. 487 488 489 NOTE: currently only 8 bits are defined in the 10 bit BQR 490 control field. The upper two bits are provided by SW in 491 BQR_rsvd_9_8. 492 493 <legal 2-20> 494 */ 495 496 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET 0x0000000000000008 497 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB 7 498 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB 11 499 #define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK 0x0000000000000f80 500 501 502 /* Description UL_HEADROOM_RSVD_7_6 503 504 These will be used by TXPCU to fill the upper two bits of 505 the UPH control field. 506 <legal all> 507 */ 508 509 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET 0x0000000000000008 510 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB 12 511 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB 13 512 #define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK 0x0000000000003000 513 514 515 /* Description BQR_RSVD_9_8 516 517 These will be used by TXPCU to fill the upper two bits of 518 the BQR control field. 519 NOTE: When overwriting CAS control (8-bit) at the same offset 520 as BQR control (10-bit), TXPCU will ignore the BQR overwrite, 521 including these upper two bits. 522 <legal all> 523 */ 524 525 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET 0x0000000000000008 526 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB 14 527 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB 15 528 #define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK 0x000000000000c000 529 530 531 /* Description BASE_PN_63_48 532 533 Upper bits PN number, in case a larger then 48 bit PN number 534 needs to be inserted in the transmit frame. 535 536 63-48 bits of the 128-bit packet number 537 <legal all> 538 */ 539 540 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET 0x0000000000000008 541 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB 16 542 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB 31 543 #define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK 0x00000000ffff0000 544 545 546 /* Description BASE_PN_95_64 547 548 Upper bits PN number, in case a larger then 48 bit PN number 549 needs to be inserted in the transmit frame. 550 551 95-64 bits of the 128-bit packet number 552 <legal all> 553 */ 554 555 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET 0x0000000000000008 556 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB 32 557 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB 63 558 #define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK 0xffffffff00000000 559 560 561 /* Description BASE_PN_127_96 562 563 Upper bits PN number, in case a larger then 48 bit PN number 564 needs to be inserted in the transmit frame. 565 566 127-96 bits of the 128-bit packet number 567 <legal all> 568 */ 569 570 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET 0x0000000000000010 571 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB 0 572 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB 31 573 #define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK 0x00000000ffffffff 574 575 576 /* Description HT_CONTROL_FIELD_BW20 577 578 Field used by TXPCU when in TX_MPDU_START TLV field vht_control_present 579 is set. 580 581 Note that TXPCU might overwrite some fields. This is controlled 582 with field HT_control_overwrite_enable 583 584 See HT/HE control overwrite order NOTE after this table 585 586 <legal all> 587 */ 588 589 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_OFFSET 0x0000000000000010 590 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_LSB 32 591 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MSB 63 592 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MASK 0xffffffff00000000 593 594 595 /* Description HT_CONTROL_FIELD_BW40 596 597 Field used by TXPCU when in TX_MPDU_START TLV field vht_control_present 598 is set. 599 600 Note that TXPCU might overwrite some fields. This is controlled 601 with field HT_control_overwrite_enable 602 603 See HT/HE control overwrite order NOTE after this table 604 605 <legal all> 606 */ 607 608 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_OFFSET 0x0000000000000018 609 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_LSB 0 610 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MSB 31 611 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MASK 0x00000000ffffffff 612 613 614 /* Description HT_CONTROL_FIELD_BW80 615 616 Field used by TXPCU when in TX_MPDU_START TLV field vht_control_present 617 is set. 618 619 Note that TXPCU might overwrite some fields. This is controlled 620 with field HT_control_overwrite_enable 621 622 See HT/HE control overwrite order NOTE after this table 623 624 <legal all> 625 */ 626 627 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_OFFSET 0x0000000000000018 628 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_LSB 32 629 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MSB 63 630 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MASK 0xffffffff00000000 631 632 633 /* Description HT_CONTROL_FIELD_BW160 634 635 Field used by TXPCU when in TX_MPDU_START TLV field vht_control_present 636 is set. 637 638 Note that TXPCU might overwrite some fields. This is controlled 639 with field HT_control_overwrite_enable 640 641 See HT/HE control overwrite order NOTE after this table 642 643 <legal all> 644 */ 645 646 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_OFFSET 0x0000000000000020 647 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_LSB 0 648 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MSB 31 649 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MASK 0x00000000ffffffff 650 651 652 /* Description HT_CONTROL_OVERWRITE_MASK 653 654 Field only valid when HT_control_overwrite_enable is set. 655 656 657 This field indicates which bits of the HT_CONTROL_FIELD 658 shall be overwritten with bits from TXPCU register HT_CONTROL_OVERWRITE_IX??? 659 660 Every bit that needs to be overwritten is set to 1 in this 661 register. 662 <legal all> 663 */ 664 665 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET 0x0000000000000020 666 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB 32 667 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB 63 668 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK 0xffffffff00000000 669 670 671 /* Description CAS_CONTROL_INFO 672 673 This contains 8-bit CAS control field to be used for transmission 674 during SRP window 675 <legal all> 676 */ 677 678 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET 0x0000000000000028 679 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB 0 680 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB 7 681 #define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK 0x00000000000000ff 682 683 684 /* Description CAS_OFFSET 685 686 5 bit offset for CAS insertion 687 <legal 2-20> 688 */ 689 690 #define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET 0x0000000000000028 691 #define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB 8 692 #define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB 12 693 #define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK 0x0000000000001f00 694 695 696 /* Description CAS_INSERTION_ENABLE 697 698 single bit used as ENABLE for CAS control insertion for 699 transmission during SRP window 700 <legal all> 701 */ 702 703 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET 0x0000000000000028 704 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB 13 705 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB 13 706 #define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK 0x0000000000002000 707 708 709 /* Description RESERVED_10A 710 711 <legal 0> 712 */ 713 714 #define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET 0x0000000000000028 715 #define TX_QUEUE_EXTENSION_RESERVED_10A_LSB 14 716 #define TX_QUEUE_EXTENSION_RESERVED_10A_MSB 15 717 #define TX_QUEUE_EXTENSION_RESERVED_10A_MASK 0x000000000000c000 718 719 720 /* Description HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP 721 722 4-bit index similar to HT_control_overwrite_source field 723 to be used for transmission during SRP window 724 <legal all> 725 */ 726 727 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET 0x0000000000000028 728 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB 16 729 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB 19 730 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK 0x00000000000f0000 731 732 733 /* Description HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP 734 735 4-bit index similar to HT_control_overwrite_source field 736 to be used for response to BSRP triggers (even during SRP 737 window) 738 <legal all> 739 */ 740 741 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET 0x0000000000000028 742 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB 20 743 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB 23 744 #define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK 0x0000000000f00000 745 746 747 /* Description RESERVED_10B 748 749 <legal 0> 750 */ 751 752 #define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET 0x0000000000000028 753 #define TX_QUEUE_EXTENSION_RESERVED_10B_LSB 24 754 #define TX_QUEUE_EXTENSION_RESERVED_10B_MSB 29 755 #define TX_QUEUE_EXTENSION_RESERVED_10B_MASK 0x000000003f000000 756 757 758 /* Description MPDU_HDR_LEN_OVERRIDE_EN 759 760 This is for the FW override of MPDU overhead length programmed 761 in the TQM queue. 762 763 If enabled, PDG will update the length of each MPDU by subtracting 764 the value of field Mpdu_header_length in 'MPDU_QUEUE_OVERVIEW' 765 and adding Mpdu_hdr_len_override_val (in this TLV). 766 <legal all> 767 */ 768 769 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET 0x0000000000000028 770 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB 30 771 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB 30 772 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK 0x0000000040000000 773 774 775 /* Description BAR_SSN_OVERWRITE_ENABLE 776 777 If enabled, TXPCU will overwrite the starting sequence number 778 in case of Tx BAR or MU-BAR Trigger from with the sequence 779 number from 'MPDU_QUEUE_OVERVIEW' 780 <legal all> 781 */ 782 783 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET 0x0000000000000028 784 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB 31 785 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB 31 786 #define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK 0x0000000080000000 787 788 789 /* Description BAR_SSN_OFFSET 790 791 Offset to the starting sequence number in case of Tx BAR 792 or MU-BAR Trigger that TXPCU can overwrite with the sequence 793 number from 'MPDU_QUEUE_OVERVIEW' 794 <legal all> 795 */ 796 797 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET 0x0000000000000028 798 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB 32 799 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB 43 800 #define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK 0x00000fff00000000 801 802 803 /* Description MPDU_HDR_LEN_OVERRIDE_VAL 804 805 This is for the FW override of MPDU overhead length programmed 806 in the TQM queue. 807 808 See field Mpdu_hdr_len_override_en. 809 810 Hamilton v1 used bits [31:12] along with word 1 bits [29:26], [8:1] 811 for 'HT_control_field_bw320.' 812 <legal all> 813 */ 814 815 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET 0x0000000000000028 816 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB 44 817 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB 52 818 #define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK 0x001ff00000000000 819 820 821 /* Description RESERVED_11A 822 823 Hamilton v1 used bits [31:12] along with word 1 bits [29:26], [8:1] 824 for 'HT_control_field_bw320.' 825 <legal 0> 826 */ 827 828 #define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET 0x0000000000000028 829 #define TX_QUEUE_EXTENSION_RESERVED_11A_LSB 53 830 #define TX_QUEUE_EXTENSION_RESERVED_11A_MSB 63 831 #define TX_QUEUE_EXTENSION_RESERVED_11A_MASK 0xffe0000000000000 832 833 834 /* Description HT_CONTROL_FIELD_BW320 835 836 Field used by TXPCU when in TX_MPDU_START TLV field vht_control_present 837 is set. 838 839 Note that TXPCU might overwrite some fields. This is controlled 840 with field HT_control_overwrite_enable 841 842 See HT/HE control overwrite order NOTE after this table 843 844 Hamilton v1 did not include this (and any subsequent) word. 845 846 <legal all> 847 */ 848 849 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_OFFSET 0x0000000000000030 850 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_LSB 0 851 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MSB 31 852 #define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MASK 0x00000000ffffffff 853 854 855 /* Description FW2SW_INFO 856 857 This field is provided by FW, to be logged via TXMON to 858 host SW. It is transparent to HW. 859 860 <legal all> 861 */ 862 863 #define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET 0x0000000000000030 864 #define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB 32 865 #define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB 63 866 #define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK 0xffffffff00000000 867 868 869 870 #endif // TX_QUEUE_EXTENSION 871