xref: /wlan-driver/fw-api/hw/qca5332/txpcu_buffer_status.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 
2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 
19 
20 
21 
22 
23 
24 
25 
26 #ifndef _TXPCU_BUFFER_STATUS_H_
27 #define _TXPCU_BUFFER_STATUS_H_
28 #if !defined(__ASSEMBLER__)
29 #endif
30 
31 #include "txpcu_buffer_basics.h"
32 #define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2
33 
34 #define NUM_OF_QWORDS_TXPCU_BUFFER_STATUS 1
35 
36 
37 struct txpcu_buffer_status {
38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
39              struct   txpcu_buffer_basics                                       txpcu_basix_buffer_info;
40              uint32_t reserved                                                : 15, // [14:0]
41                       msdu_end                                                :  1, // [15:15]
42                       tx_data_sync_value                                      : 16; // [31:16]
43 #else
44              struct   txpcu_buffer_basics                                       txpcu_basix_buffer_info;
45              uint32_t tx_data_sync_value                                      : 16, // [31:16]
46                       msdu_end                                                :  1, // [15:15]
47                       reserved                                                : 15; // [14:0]
48 #endif
49 };
50 
51 
52 /* Description		TXPCU_BASIX_BUFFER_INFO
53 
54 			Global overview of the TXPCU buffer
55 			<legal all>
56 */
57 
58 
59 /* Description		AVAILABLE_MEMORY
60 
61 			The amount of TX_FIFO memory in 128 byte units that is available.
62 
63 			TXPCU gets this from the Avail_fifo_mem signal from SFM.
64 
65 
66 			When SFM is indicating a larger available amount, that value
67 			 shall be saturated to 0xFF in this field.
68 
69 			<legal all>
70 */
71 
72 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET         0x0000000000000000
73 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB            0
74 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB            7
75 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK           0x00000000000000ff
76 
77 
78 /* Description		PARTIAL_TX_DATA_TLV_COUNT
79 
80 			The number of  16 bytes units received of the TX_DATA TLV
81 			 that is currently under reception by TXPCU.
82 			Value saturates at 255 in case TX_DATA TLV length is larger
83 			 then 4080 bytes. This is unlikely as TX_DATA will generally
84 			 not be larger then then the Max MSDU size.
85 			<legal all>
86 */
87 
88 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000
89 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB   8
90 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB   15
91 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK  0x000000000000ff00
92 
93 
94 /* Description		TX_DATA_TLV_COUNT
95 
96 			The number of completely received TX_DATA TLVs (of all the
97 			 users together) received by TXPCU
98 			<legal all>
99 */
100 
101 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET        0x0000000000000000
102 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB           16
103 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB           31
104 #define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK          0x00000000ffff0000
105 
106 
107 /* Description		RESERVED
108 
109 			<legal 0>
110 */
111 
112 #define TXPCU_BUFFER_STATUS_RESERVED_OFFSET                                         0x0000000000000000
113 #define TXPCU_BUFFER_STATUS_RESERVED_LSB                                            32
114 #define TXPCU_BUFFER_STATUS_RESERVED_MSB                                            46
115 #define TXPCU_BUFFER_STATUS_RESERVED_MASK                                           0x00007fff00000000
116 
117 
118 /* Description		MSDU_END
119 
120 			Bit to indicate that TXPCU has received an entire MSDU and
121 			 'TX_MSDU_END'
122 			<legal all>
123 */
124 
125 #define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET                                         0x0000000000000000
126 #define TXPCU_BUFFER_STATUS_MSDU_END_LSB                                            47
127 #define TXPCU_BUFFER_STATUS_MSDU_END_MSB                                            47
128 #define TXPCU_BUFFER_STATUS_MSDU_END_MASK                                           0x0000800000000000
129 
130 
131 /* Description		TX_DATA_SYNC_VALUE
132 
133 			The last received sync_value number from the TX_DATA_SYNC
134 			 TLV
135 			At reception of TX_FES_SETUP, TXPCU initializes this value
136 			 to 0
137 			<legal all>
138 */
139 
140 #define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET                               0x0000000000000000
141 #define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB                                  48
142 #define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB                                  63
143 #define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK                                 0xffff000000000000
144 
145 
146 
147 #endif   // TXPCU_BUFFER_STATUS
148