1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _U_SIG_EHT_SU_MU_INFO_H_ 27 #define _U_SIG_EHT_SU_MU_INFO_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2 32 33 34 struct u_sig_eht_su_mu_info { 35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 36 uint32_t phy_version : 3, // [2:0] 37 transmit_bw : 3, // [5:3] 38 dl_ul_flag : 1, // [6:6] 39 bss_color_id : 6, // [12:7] 40 txop_duration : 7, // [19:13] 41 disregard_0a : 5, // [24:20] 42 validate_0b : 1, // [25:25] 43 reserved_0c : 6; // [31:26] 44 uint32_t eht_ppdu_sig_cmn_type : 2, // [1:0] 45 validate_1a : 1, // [2:2] 46 punctured_channel_information : 5, // [7:3] 47 validate_1b : 1, // [8:8] 48 mcs_of_eht_sig : 2, // [10:9] 49 num_eht_sig_symbols : 5, // [15:11] 50 crc : 4, // [19:16] 51 tail : 6, // [25:20] 52 dot11ax_su_extended : 1, // [26:26] 53 reserved_1d : 3, // [29:27] 54 rx_ndp : 1, // [30:30] 55 rx_integrity_check_passed : 1; // [31:31] 56 #else 57 uint32_t reserved_0c : 6, // [31:26] 58 validate_0b : 1, // [25:25] 59 disregard_0a : 5, // [24:20] 60 txop_duration : 7, // [19:13] 61 bss_color_id : 6, // [12:7] 62 dl_ul_flag : 1, // [6:6] 63 transmit_bw : 3, // [5:3] 64 phy_version : 3; // [2:0] 65 uint32_t rx_integrity_check_passed : 1, // [31:31] 66 rx_ndp : 1, // [30:30] 67 reserved_1d : 3, // [29:27] 68 dot11ax_su_extended : 1, // [26:26] 69 tail : 6, // [25:20] 70 crc : 4, // [19:16] 71 num_eht_sig_symbols : 5, // [15:11] 72 mcs_of_eht_sig : 2, // [10:9] 73 validate_1b : 1, // [8:8] 74 punctured_channel_information : 5, // [7:3] 75 validate_1a : 1, // [2:2] 76 eht_ppdu_sig_cmn_type : 2; // [1:0] 77 #endif 78 }; 79 80 81 /* Description PHY_VERSION 82 83 <enum 0 U_SIG_VERSION_EHT> 84 Values 1 - 7 are reserved. 85 <legal 0 86 */ 87 88 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET 0x00000000 89 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB 0 90 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB 2 91 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK 0x00000007 92 93 94 /* Description TRANSMIT_BW 95 96 Bandwidth of the PPDU 97 98 <enum 0 U_SIG_BW20> 20 MHz 99 <enum 1 U_SIG_BW40> 40 MHz 100 <enum 2 U_SIG_BW80> 80 MHz 101 <enum 3 U_SIG_BW160> 160 MHz 102 <enum 4 U_SIG_BW320> 320 MHz 103 <enum 5 U_SIG_BW320_2> DO NOT USE 104 105 Microcode remaps 'U_SIG_BW320' based on channelization. 106 107 On RX side, field used by MAC HW 108 <legal all> 109 */ 110 111 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000 112 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3 113 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5 114 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038 115 116 117 /* Description DL_UL_FLAG 118 119 Differentiates between DL and UL transmission 120 121 <enum 0 DL_UL_FLAG_IS_DL_OR_TDLS> 122 <enum 1 DL_UL_FLAG_IS_UL> 123 <legal all> 124 */ 125 126 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000 127 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6 128 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6 129 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040 130 131 132 /* Description BSS_COLOR_ID 133 134 BSS color ID 135 136 Field used by MAC HW 137 <legal all> 138 */ 139 140 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 141 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7 142 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12 143 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80 144 145 146 /* Description TXOP_DURATION 147 148 Indicates the remaining time in the current TXOP 149 150 Field used by MAC HW 151 <legal all> 152 */ 153 154 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000 155 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13 156 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19 157 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000 158 159 160 /* Description DISREGARD_0A 161 162 Note: spec indicates this shall be set to 1s 163 <legal 31> 164 */ 165 166 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000 167 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20 168 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24 169 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000 170 171 172 /* Description VALIDATE_0B 173 174 Note: spec indicates this shall be set to 1 175 <legal 1> 176 */ 177 178 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000 179 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25 180 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25 181 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000 182 183 184 /* Description RESERVED_0C 185 186 <legal 0> 187 */ 188 189 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000 190 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26 191 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31 192 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000 193 194 195 /* Description EHT_PPDU_SIG_CMN_TYPE 196 197 <enum 3 EHT_PPDU_SIG_rsvd> DO NOT USE 198 <enum 0 EHT_PPDU_SIG_TB_or_DL_OFDMA> Need to look at both 199 EHT-SIG content channels for DL OFDMA (including OFDMA+MU-MIMO) 200 201 <enum 2 EHT_PPDU_SIG_DL_MU_MIMO> Need to look at both EHT-SIG 202 content channels 203 <enum 1 EHT_PPDU_SIG_SU> Need to look at only one EHT-SIG 204 content channel 205 <legal all> 206 */ 207 208 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 209 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 210 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 211 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 212 213 214 /* Description VALIDATE_1A 215 216 Note: spec indicates this shall be set to 1 217 <legal 1> 218 */ 219 220 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004 221 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2 222 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2 223 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004 224 225 226 /* Description PUNCTURED_CHANNEL_INFORMATION 227 228 For OFDMA BW 20 MHz or 40 MHz: 229 Set to all 1s, i.e. 31 230 231 For OFDMA of higher BW: 232 Bit 3 = lowest 20 MHz in the current 80 MHz 233 Bit 6 = highest 20 MHz in the current 80 MHz 234 Bit 7 = 1 235 236 Each bit indicates whether the 20 MHz is modulated or punctured 237 238 0 = punctured 239 1 = modulated 240 241 For non-OFDMA: 242 Set to a 5-bit value encoding the puncture pattern, a.k.a. 'U_sig_puncture_pattern_encoding' 243 elsewhere in the data structures 244 245 <legal all> 246 */ 247 248 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 249 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3 250 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7 251 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 252 253 254 /* Description VALIDATE_1B 255 256 Note: spec indicates this shall be set to 1 257 <legal 1> 258 */ 259 260 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004 261 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8 262 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8 263 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100 264 265 266 /* Description MCS_OF_EHT_SIG 267 268 Indicates the MCS of EHT-SIG 269 0 - 1: MCS 0 - 1 270 2: MCS 3 271 3: MCS 0 with DCM 272 <legal all> 273 */ 274 275 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004 276 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9 277 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10 278 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600 279 280 281 /* Description NUM_EHT_SIG_SYMBOLS 282 283 Number of symbols 284 285 The actual number of symbols is 1 larger than indicated 286 in this field. 287 288 <legal all> 289 */ 290 291 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 292 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11 293 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15 294 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 295 296 297 /* Description CRC 298 299 CRC for U-SIG contents 300 <legal all> 301 */ 302 303 #define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004 304 #define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16 305 #define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19 306 #define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000 307 308 309 /* Description TAIL 310 311 <legal 0> 312 */ 313 314 #define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004 315 #define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20 316 #define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25 317 #define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000 318 319 320 /* Description DOT11AX_SU_EXTENDED 321 322 TX side: 323 Set to 0 324 325 RX side: On RX side, evaluated by MAC HW 326 327 This is the only way for MAC RX to know that this was a 328 U_SIG_EHT_SU received in extended range format. 329 330 When set, the 11be frame is of the extended range format. 331 332 <legal all> 333 */ 334 335 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 336 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26 337 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26 338 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 339 340 341 /* Description RESERVED_1D 342 343 <legal 0> 344 */ 345 346 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004 347 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27 348 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29 349 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000 350 351 352 /* Description RX_NDP 353 354 TX side: 355 Set to 0 356 357 RX side: On RX side, looked at by MAC HW 358 359 When set, PHY has received an (expected) NDP frame 360 <legal all> 361 */ 362 363 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004 364 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30 365 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30 366 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000 367 368 369 /* Description RX_INTEGRITY_CHECK_PASSED 370 371 TX side: Set to 0 372 RX side: Set to 1 if PHY determines the U-SIG CRC check 373 has passed, else set to 0 374 375 <legal all> 376 */ 377 378 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 379 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 380 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 381 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 382 383 384 385 #endif // U_SIG_EHT_SU_MU_INFO 386