1*5113495bSYour Name 2*5113495bSYour Name /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name 18*5113495bSYour Name #ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ 19*5113495bSYour Name #define _UNIFORM_DESCRIPTOR_HEADER_H_ 20*5113495bSYour Name #if !defined(__ASSEMBLER__) 21*5113495bSYour Name #endif 22*5113495bSYour Name 23*5113495bSYour Name #define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 24*5113495bSYour Name 25*5113495bSYour Name 26*5113495bSYour Name struct uniform_descriptor_header { 27*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 28*5113495bSYour Name uint32_t owner : 4, // [3:0] 29*5113495bSYour Name buffer_type : 4, // [7:4] 30*5113495bSYour Name tx_mpdu_queue_number : 20, // [27:8] 31*5113495bSYour Name reserved_0a : 4; // [31:28] 32*5113495bSYour Name #else 33*5113495bSYour Name uint32_t reserved_0a : 4, // [31:28] 34*5113495bSYour Name tx_mpdu_queue_number : 20, // [27:8] 35*5113495bSYour Name buffer_type : 4, // [7:4] 36*5113495bSYour Name owner : 4; // [3:0] 37*5113495bSYour Name #endif 38*5113495bSYour Name }; 39*5113495bSYour Name 40*5113495bSYour Name 41*5113495bSYour Name /* Description OWNER 42*5113495bSYour Name 43*5113495bSYour Name Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 44*5113495bSYour Name Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 45*5113495bSYour Name 46*5113495bSYour Name The owner of this data structure: 47*5113495bSYour Name <enum 0 WBM_owned> Buffer Manager currently owns this data 48*5113495bSYour Name structure. 49*5113495bSYour Name <enum 1 SW_OR_FW_owned> Software of FW currently owns this 50*5113495bSYour Name data structure. 51*5113495bSYour Name <enum 2 TQM_owned> Transmit Queue Manager currently owns 52*5113495bSYour Name this data structure. 53*5113495bSYour Name <enum 3 RXDMA_owned> Receive DMA currently owns this data 54*5113495bSYour Name structure. 55*5113495bSYour Name <enum 4 REO_owned> Reorder currently owns this data structure. 56*5113495bSYour Name 57*5113495bSYour Name <enum 5 SWITCH_owned> SWITCH currently owns this data structure. 58*5113495bSYour Name 59*5113495bSYour Name 60*5113495bSYour Name <legal 0-5> 61*5113495bSYour Name */ 62*5113495bSYour Name 63*5113495bSYour Name #define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 64*5113495bSYour Name #define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB 0 65*5113495bSYour Name #define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB 3 66*5113495bSYour Name #define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 67*5113495bSYour Name 68*5113495bSYour Name 69*5113495bSYour Name /* Description BUFFER_TYPE 70*5113495bSYour Name 71*5113495bSYour Name Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 72*5113495bSYour Name Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 73*5113495bSYour Name 74*5113495bSYour Name Field describing what contents format is of this descriptor 75*5113495bSYour Name 76*5113495bSYour Name 77*5113495bSYour Name <enum 0 Transmit_MSDU_Link_descriptor> 78*5113495bSYour Name <enum 1 Transmit_MPDU_Link_descriptor> 79*5113495bSYour Name <enum 2 Transmit_MPDU_Queue_head_descriptor> 80*5113495bSYour Name <enum 3 Transmit_MPDU_Queue_ext_descriptor> 81*5113495bSYour Name <enum 4 Transmit_flow_descriptor> 82*5113495bSYour Name <enum 5 Transmit_buffer> NOT TO BE USED: 83*5113495bSYour Name 84*5113495bSYour Name <enum 6 Receive_MSDU_Link_descriptor> 85*5113495bSYour Name <enum 7 Receive_MPDU_Link_descriptor> 86*5113495bSYour Name <enum 8 Receive_REO_queue_descriptor> 87*5113495bSYour Name <enum 9 Receive_REO_queue_1k_descriptor> 88*5113495bSYour Name <enum 10 Receive_REO_queue_ext_descriptor> 89*5113495bSYour Name 90*5113495bSYour Name <enum 11 Receive_buffer> 91*5113495bSYour Name 92*5113495bSYour Name <enum 12 Idle_link_list_entry> 93*5113495bSYour Name 94*5113495bSYour Name <legal 0-12> 95*5113495bSYour Name */ 96*5113495bSYour Name 97*5113495bSYour Name #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 98*5113495bSYour Name #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 99*5113495bSYour Name #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 100*5113495bSYour Name #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 101*5113495bSYour Name 102*5113495bSYour Name 103*5113495bSYour Name /* Description TX_MPDU_QUEUE_NUMBER 104*5113495bSYour Name 105*5113495bSYour Name Consumer: TQM/Debug 106*5113495bSYour Name Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) 107*5113495bSYour Name 108*5113495bSYour Name Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor 109*5113495bSYour Name 110*5113495bSYour Name 111*5113495bSYour Name Indicates the MPDU queue ID to which this MPDU descriptor 112*5113495bSYour Name belongs 113*5113495bSYour Name Used for tracking and debugging 114*5113495bSYour Name 115*5113495bSYour Name Hamilton and Waikiki used bits [19:0] of word 1 of 'TX_MPDU_LINK,' 116*5113495bSYour Name word 16 of 'TX_MPDU_QUEUE_HEAD' and word 1 of 'TX_MPDU_QUEUE_EXT' 117*5113495bSYour Name for this. 118*5113495bSYour Name <legal all> 119*5113495bSYour Name */ 120*5113495bSYour Name 121*5113495bSYour Name #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 122*5113495bSYour Name #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 123*5113495bSYour Name #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 124*5113495bSYour Name #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 125*5113495bSYour Name 126*5113495bSYour Name 127*5113495bSYour Name /* Description RESERVED_0A 128*5113495bSYour Name 129*5113495bSYour Name <legal 0> 130*5113495bSYour Name */ 131*5113495bSYour Name 132*5113495bSYour Name #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 133*5113495bSYour Name #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 134*5113495bSYour Name #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 135*5113495bSYour Name #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 136*5113495bSYour Name 137*5113495bSYour Name 138*5113495bSYour Name 139*5113495bSYour Name #endif // UNIFORM_DESCRIPTOR_HEADER 140