1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ 19 #define _UNIFORM_DESCRIPTOR_HEADER_H_ 20 #if !defined(__ASSEMBLER__) 21 #endif 22 23 #define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 24 25 26 struct uniform_descriptor_header { 27 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 28 uint32_t owner : 4, // [3:0] 29 buffer_type : 4, // [7:4] 30 tx_mpdu_queue_number : 20, // [27:8] 31 reserved_0a : 4; // [31:28] 32 #else 33 uint32_t reserved_0a : 4, // [31:28] 34 tx_mpdu_queue_number : 20, // [27:8] 35 buffer_type : 4, // [7:4] 36 owner : 4; // [3:0] 37 #endif 38 }; 39 40 41 /* Description OWNER 42 43 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 44 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 45 46 The owner of this data structure: 47 <enum 0 WBM_owned> Buffer Manager currently owns this data 48 structure. 49 <enum 1 SW_OR_FW_owned> Software of FW currently owns this 50 data structure. 51 <enum 2 TQM_owned> Transmit Queue Manager currently owns 52 this data structure. 53 <enum 3 RXDMA_owned> Receive DMA currently owns this data 54 structure. 55 <enum 4 REO_owned> Reorder currently owns this data structure. 56 57 <enum 5 SWITCH_owned> SWITCH currently owns this data structure. 58 59 60 <legal 0-5> 61 */ 62 63 #define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 64 #define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB 0 65 #define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB 3 66 #define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 67 68 69 /* Description BUFFER_TYPE 70 71 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 72 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 73 74 Field describing what contents format is of this descriptor 75 76 77 <enum 0 Transmit_MSDU_Link_descriptor> 78 <enum 1 Transmit_MPDU_Link_descriptor> 79 <enum 2 Transmit_MPDU_Queue_head_descriptor> 80 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 81 <enum 4 Transmit_flow_descriptor> 82 <enum 5 Transmit_buffer> NOT TO BE USED: 83 84 <enum 6 Receive_MSDU_Link_descriptor> 85 <enum 7 Receive_MPDU_Link_descriptor> 86 <enum 8 Receive_REO_queue_descriptor> 87 <enum 9 Receive_REO_queue_1k_descriptor> 88 <enum 10 Receive_REO_queue_ext_descriptor> 89 90 <enum 11 Receive_buffer> 91 92 <enum 12 Idle_link_list_entry> 93 94 <legal 0-12> 95 */ 96 97 #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 98 #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 99 #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 100 #define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 101 102 103 /* Description TX_MPDU_QUEUE_NUMBER 104 105 Consumer: TQM/Debug 106 Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) 107 108 Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor 109 110 111 Indicates the MPDU queue ID to which this MPDU descriptor 112 belongs 113 Used for tracking and debugging 114 115 Hamilton and Waikiki used bits [19:0] of word 1 of 'TX_MPDU_LINK,' 116 word 16 of 'TX_MPDU_QUEUE_HEAD' and word 1 of 'TX_MPDU_QUEUE_EXT' 117 for this. 118 <legal all> 119 */ 120 121 #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 122 #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 123 #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 124 #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 125 126 127 /* Description RESERVED_0A 128 129 <legal 0> 130 */ 131 132 #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 133 #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 134 #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 135 #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 136 137 138 139 #endif // UNIFORM_DESCRIPTOR_HEADER 140