1*5113495bSYour Name 2*5113495bSYour Name /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name 18*5113495bSYour Name 19*5113495bSYour Name 20*5113495bSYour Name 21*5113495bSYour Name 22*5113495bSYour Name 23*5113495bSYour Name 24*5113495bSYour Name 25*5113495bSYour Name 26*5113495bSYour Name #ifndef _WBM2SW_COMPLETION_RING_RX_H_ 27*5113495bSYour Name #define _WBM2SW_COMPLETION_RING_RX_H_ 28*5113495bSYour Name #if !defined(__ASSEMBLER__) 29*5113495bSYour Name #endif 30*5113495bSYour Name 31*5113495bSYour Name #include "rx_msdu_desc_info.h" 32*5113495bSYour Name #include "rx_mpdu_desc_info.h" 33*5113495bSYour Name #define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8 34*5113495bSYour Name 35*5113495bSYour Name 36*5113495bSYour Name struct wbm2sw_completion_ring_rx { 37*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38*5113495bSYour Name uint32_t buffer_virt_addr_31_0 : 32; // [31:0] 39*5113495bSYour Name uint32_t buffer_virt_addr_63_32 : 32; // [31:0] 40*5113495bSYour Name uint32_t release_source_module : 3, // [2:0] 41*5113495bSYour Name bm_action : 3, // [5:3] 42*5113495bSYour Name buffer_or_desc_type : 3, // [8:6] 43*5113495bSYour Name return_buffer_manager : 4, // [12:9] 44*5113495bSYour Name reserved_2a : 2, // [14:13] 45*5113495bSYour Name cache_id : 1, // [15:15] 46*5113495bSYour Name cookie_conversion_status : 1, // [16:16] 47*5113495bSYour Name rxdma_push_reason : 2, // [18:17] 48*5113495bSYour Name rxdma_error_code : 5, // [23:19] 49*5113495bSYour Name reo_push_reason : 2, // [25:24] 50*5113495bSYour Name reo_error_code : 5, // [30:26] 51*5113495bSYour Name wbm_internal_error : 1; // [31:31] 52*5113495bSYour Name struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 53*5113495bSYour Name struct rx_msdu_desc_info rx_msdu_desc_info_details; 54*5113495bSYour Name uint32_t buffer_phys_addr_31_0 : 32; // [31:0] 55*5113495bSYour Name uint32_t buffer_phys_addr_39_32 : 8, // [7:0] 56*5113495bSYour Name sw_buffer_cookie : 20, // [27:8] 57*5113495bSYour Name looping_count : 4; // [31:28] 58*5113495bSYour Name #else 59*5113495bSYour Name uint32_t buffer_virt_addr_31_0 : 32; // [31:0] 60*5113495bSYour Name uint32_t buffer_virt_addr_63_32 : 32; // [31:0] 61*5113495bSYour Name uint32_t wbm_internal_error : 1, // [31:31] 62*5113495bSYour Name reo_error_code : 5, // [30:26] 63*5113495bSYour Name reo_push_reason : 2, // [25:24] 64*5113495bSYour Name rxdma_error_code : 5, // [23:19] 65*5113495bSYour Name rxdma_push_reason : 2, // [18:17] 66*5113495bSYour Name cookie_conversion_status : 1, // [16:16] 67*5113495bSYour Name cache_id : 1, // [15:15] 68*5113495bSYour Name reserved_2a : 2, // [14:13] 69*5113495bSYour Name return_buffer_manager : 4, // [12:9] 70*5113495bSYour Name buffer_or_desc_type : 3, // [8:6] 71*5113495bSYour Name bm_action : 3, // [5:3] 72*5113495bSYour Name release_source_module : 3; // [2:0] 73*5113495bSYour Name struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 74*5113495bSYour Name struct rx_msdu_desc_info rx_msdu_desc_info_details; 75*5113495bSYour Name uint32_t buffer_phys_addr_31_0 : 32; // [31:0] 76*5113495bSYour Name uint32_t looping_count : 4, // [31:28] 77*5113495bSYour Name sw_buffer_cookie : 20, // [27:8] 78*5113495bSYour Name buffer_phys_addr_39_32 : 8; // [7:0] 79*5113495bSYour Name #endif 80*5113495bSYour Name }; 81*5113495bSYour Name 82*5113495bSYour Name 83*5113495bSYour Name /* Description BUFFER_VIRT_ADDR_31_0 84*5113495bSYour Name 85*5113495bSYour Name Lower 32 bits of the 64-bit virtual address corresponding 86*5113495bSYour Name to the MSDU being released 87*5113495bSYour Name <legal all> 88*5113495bSYour Name */ 89*5113495bSYour Name 90*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 91*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB 0 92*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB 31 93*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 94*5113495bSYour Name 95*5113495bSYour Name 96*5113495bSYour Name /* Description BUFFER_VIRT_ADDR_63_32 97*5113495bSYour Name 98*5113495bSYour Name Upper 32 bits of the 64-bit virtual address corresponding 99*5113495bSYour Name to the MSDU being released 100*5113495bSYour Name <legal all> 101*5113495bSYour Name */ 102*5113495bSYour Name 103*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 104*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB 0 105*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB 31 106*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 107*5113495bSYour Name 108*5113495bSYour Name 109*5113495bSYour Name /* Description RELEASE_SOURCE_MODULE 110*5113495bSYour Name 111*5113495bSYour Name Indicates which module initiated the release of this buffer 112*5113495bSYour Name or descriptor 113*5113495bSYour Name 114*5113495bSYour Name <enum 1 release_source_RXDMA> RXDMA released this buffer 115*5113495bSYour Name or descriptor 116*5113495bSYour Name <enum 2 release_source_REO> REO released this buffer or 117*5113495bSYour Name descriptor 118*5113495bSYour Name <enum 5 release_source_FW_RX> FW released this buffer or 119*5113495bSYour Name descriptor 120*5113495bSYour Name <enum 4 release_source_SW_RX> SW released this buffer or 121*5113495bSYour Name descriptor 122*5113495bSYour Name <enum 0 release_source_TQM> DO NOT USE 123*5113495bSYour Name <enum 3 release_source_FW_TX> DO NOT USE 124*5113495bSYour Name <enum 6 release_source_SW_TX> DO NOT USE 125*5113495bSYour Name <legal 0-6> 126*5113495bSYour Name */ 127*5113495bSYour Name 128*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 129*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 130*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 131*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 132*5113495bSYour Name 133*5113495bSYour Name 134*5113495bSYour Name /* Description BM_ACTION 135*5113495bSYour Name 136*5113495bSYour Name Consumer: WBM/SW/FW 137*5113495bSYour Name Producer: SW/TQM/RXDMA/REO/SWITCH 138*5113495bSYour Name 139*5113495bSYour Name Field only valid when the field return_buffer_manager in 140*5113495bSYour Name the Released_buff_or_desc_addr_info indicates: 141*5113495bSYour Name WBM_IDLE_BUF_LIST or 142*5113495bSYour Name WBM_IDLE_DESC_LIST 143*5113495bSYour Name 144*5113495bSYour Name An MSDU extension descriptor shall never be marked as WBM 145*5113495bSYour Name being the 'owner', and thus WBM will forward it to FW/SW 146*5113495bSYour Name 147*5113495bSYour Name 148*5113495bSYour Name <enum 0 Put_in_idle_list> Put the buffer or descriptor back 149*5113495bSYour Name in the idle list. In case of MSDU or MDPU link descriptor, 150*5113495bSYour Name BM does not need to check to release any individual MSDU 151*5113495bSYour Name buffers 152*5113495bSYour Name 153*5113495bSYour Name <enum 1 release_msdu_list > This BM action can only be used 154*5113495bSYour Name in combination with buffer_or_desc_type being msdu_link_descriptor. 155*5113495bSYour Name Field first_msdu_index points out which MSDU pointer in 156*5113495bSYour Name the MSDU link descriptor is the first of an MPDU that is 157*5113495bSYour Name released. 158*5113495bSYour Name BM shall release all the MSDU buffers linked to this first 159*5113495bSYour Name MSDU buffer pointer. All related MSDU buffer pointer entries 160*5113495bSYour Name shall be set to value 0, which represents the 'NULL" pointer. 161*5113495bSYour Name When all MSDU buffer pointers in the MSDU link descriptor 162*5113495bSYour Name are 'NULL', the MSDU link descriptor itself shall also 163*5113495bSYour Name be released. 164*5113495bSYour Name 165*5113495bSYour Name <enum 2 Put_in_idle_list_expanded> CURRENTLY NOT IMPLEMENTED.... 166*5113495bSYour Name 167*5113495bSYour Name Put the buffer or descriptor back in the idle list. Only 168*5113495bSYour Name valid in combination with buffer_or_desc_type indicating 169*5113495bSYour Name MDPU_link_descriptor. 170*5113495bSYour Name BM shall release the MPDU link descriptor as well as all 171*5113495bSYour Name MSDUs that are linked to the MPDUs in this descriptor. 172*5113495bSYour Name 173*5113495bSYour Name 174*5113495bSYour Name TODO: Any restrictions? 175*5113495bSYour Name <legal 0-2> 176*5113495bSYour Name */ 177*5113495bSYour Name 178*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET 0x00000008 179*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB 3 180*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB 5 181*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK 0x00000038 182*5113495bSYour Name 183*5113495bSYour Name 184*5113495bSYour Name /* Description BUFFER_OR_DESC_TYPE 185*5113495bSYour Name 186*5113495bSYour Name Consumer: WBM/SW/FW 187*5113495bSYour Name Producer: SW/TQM/RXDMA/REO/SWITCH 188*5113495bSYour Name 189*5113495bSYour Name Field only valid when WBM is marked as the return_buffer_manager 190*5113495bSYour Name in the Released_Buffer_address_info 191*5113495bSYour Name 192*5113495bSYour Name Indicates that type of buffer or descriptor is being released 193*5113495bSYour Name 194*5113495bSYour Name 195*5113495bSYour Name <enum 0 MSDU_rel_buffer> The address points to an MSDU buffer 196*5113495bSYour Name 197*5113495bSYour Name <enum 1 msdu_link_descriptor> The address points to an TX 198*5113495bSYour Name MSDU link descriptor 199*5113495bSYour Name <enum 2 mpdu_link_descriptor> The address points to an MPDU 200*5113495bSYour Name link descriptor 201*5113495bSYour Name <enum 3 msdu_ext_descriptor > The address points to an MSDU 202*5113495bSYour Name extension descriptor. 203*5113495bSYour Name In case BM finds this one in a release ring, it passes it 204*5113495bSYour Name on to FW... 205*5113495bSYour Name <enum 4 queue_ext_descriptor> The address points to an TQM 206*5113495bSYour Name queue extension descriptor. WBM should treat this is the 207*5113495bSYour Name same way as a link descriptor. That is, put the 128 byte 208*5113495bSYour Name buffer back in the link buffer idle list. 209*5113495bSYour Name 210*5113495bSYour Name TODO: Any restrictions? 211*5113495bSYour Name <legal 0-4> 212*5113495bSYour Name */ 213*5113495bSYour Name 214*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 215*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 216*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 217*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 218*5113495bSYour Name 219*5113495bSYour Name 220*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 221*5113495bSYour Name 222*5113495bSYour Name 'Return_buffer_manager' field of the MSDU's buffer address 223*5113495bSYour Name info, for debug 224*5113495bSYour Name */ 225*5113495bSYour Name 226*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 227*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB 9 228*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB 12 229*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 230*5113495bSYour Name 231*5113495bSYour Name 232*5113495bSYour Name /* Description RESERVED_2A 233*5113495bSYour Name 234*5113495bSYour Name <legal 0> 235*5113495bSYour Name */ 236*5113495bSYour Name 237*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET 0x00000008 238*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB 13 239*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB 14 240*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK 0x00006000 241*5113495bSYour Name 242*5113495bSYour Name 243*5113495bSYour Name /* Description CACHE_ID 244*5113495bSYour Name 245*5113495bSYour Name Indicates the WBM cache the MSDU was released from 246*5113495bSYour Name <legal all> 247*5113495bSYour Name */ 248*5113495bSYour Name 249*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET 0x00000008 250*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB 15 251*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB 15 252*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK 0x00008000 253*5113495bSYour Name 254*5113495bSYour Name 255*5113495bSYour Name /* Description COOKIE_CONVERSION_STATUS 256*5113495bSYour Name 257*5113495bSYour Name 0: 'Sw_buffer_cookie' not converted to 'Buffer_virt_addr' 258*5113495bSYour Name 259*5113495bSYour Name 1: 'Sw_buffer_cookie' coverted to 'Buffer_virt_addr' 260*5113495bSYour Name <legal 1> 261*5113495bSYour Name */ 262*5113495bSYour Name 263*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 264*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 265*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 266*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 267*5113495bSYour Name 268*5113495bSYour Name 269*5113495bSYour Name /* Description RXDMA_PUSH_REASON 270*5113495bSYour Name 271*5113495bSYour Name Field only valid when Release_source_module is set to release_source_RXDMA 272*5113495bSYour Name 273*5113495bSYour Name 274*5113495bSYour Name Indicates why rxdma pushed the frame to this ring 275*5113495bSYour Name 276*5113495bSYour Name <enum 0 rxdma_error_detected> RXDMA detected an error an 277*5113495bSYour Name pushed this frame to this queue 278*5113495bSYour Name <enum 1 rxdma_routing_instruction> RXDMA pushed the frame 279*5113495bSYour Name to this queue per received routing instructions. No error 280*5113495bSYour Name within RXDMA was detected 281*5113495bSYour Name <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 282*5113495bSYour Name result the MSDU link descriptor might not have the "last_msdu_in_mpdu_flag" 283*5113495bSYour Name set, but instead WBM might just see a NULL pointer in the 284*5113495bSYour Name MSDU link descriptor. This is to be considered a normal 285*5113495bSYour Name condition for this scenario. 286*5113495bSYour Name 287*5113495bSYour Name <legal 0 - 2> 288*5113495bSYour Name */ 289*5113495bSYour Name 290*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 291*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB 17 292*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB 18 293*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 294*5113495bSYour Name 295*5113495bSYour Name 296*5113495bSYour Name /* Description RXDMA_ERROR_CODE 297*5113495bSYour Name 298*5113495bSYour Name Field only valid when 'rxdma_push_reason' set to 'rxdma_error_detected'. 299*5113495bSYour Name 300*5113495bSYour Name 301*5113495bSYour Name <enum 0 rxdma_overflow_err>MPDU frame is not complete due 302*5113495bSYour Name to a FIFO overflow error in RXPCU. 303*5113495bSYour Name <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete 304*5113495bSYour Name due to receiving incomplete MPDU from the PHY 305*5113495bSYour Name <enum 2 rxdma_fcs_err>FCS check on the MPDU frame failed 306*5113495bSYour Name 307*5113495bSYour Name <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption error 308*5113495bSYour Name or CRYPTO received an encrypted frame, but did not get 309*5113495bSYour Name a valid corresponding key id in the peer entry. 310*5113495bSYour Name <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC error 311*5113495bSYour Name 312*5113495bSYour Name <enum 5 rxdma_unecrypted_err>CRYPTO reported an unencrypted 313*5113495bSYour Name frame error when encrypted was expected 314*5113495bSYour Name <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU length 315*5113495bSYour Name error 316*5113495bSYour Name <enum 7 rxdma_msdu_limit_err>RX OLE reported that max number 317*5113495bSYour Name of MSDUs allowed in an MPDU got exceeded 318*5113495bSYour Name <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing error 319*5113495bSYour Name 320*5113495bSYour Name <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU 321*5113495bSYour Name parsing error 322*5113495bSYour Name <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout 323*5113495bSYour Name during SA search 324*5113495bSYour Name <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout 325*5113495bSYour Name during DA search 326*5113495bSYour Name <enum 12 rxdma_flow_timeout_err>RX OLE reported a timeout 327*5113495bSYour Name during flow search 328*5113495bSYour Name <enum 13 rxdma_flush_request>RXDMA received a flush request 329*5113495bSYour Name 330*5113495bSYour Name <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU 331*5113495bSYour Name present as well as a fragmented MPDU. A-MSDU defragmentation 332*5113495bSYour Name is not supported in Lithium SW so this is treated as an 333*5113495bSYour Name error. 334*5113495bSYour Name <enum 15 rxdma_multicast_echo_err>RX OLE reported a multicast 335*5113495bSYour Name echo 336*5113495bSYour Name <enum 16 rxdma_amsdu_addr_mismatch_err>RX OLE reported an 337*5113495bSYour Name A-MSDU with either 'from DS = 0' with an SA mismatching 338*5113495bSYour Name TA or 'to DS = 0' with a DA mismatching RA. 339*5113495bSYour Name <enum 17 rxdma_unauthorized_wds_err>RX PCU reported that 340*5113495bSYour Name Rx peer entry did not indicate 'authorized_to_send_WDS' 341*5113495bSYour Name and also indicated 'from DS = to DS = 1.' 342*5113495bSYour Name <enum 18 rxdma_groupcast_amsdu_or_wds_err>RX PCU reported 343*5113495bSYour Name a broadcast or multicast RA as well as either A-MSDU present 344*5113495bSYour Name or 'from DS = to DS = 1.' 345*5113495bSYour Name */ 346*5113495bSYour Name 347*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 348*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB 19 349*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB 23 350*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 351*5113495bSYour Name 352*5113495bSYour Name 353*5113495bSYour Name /* Description REO_PUSH_REASON 354*5113495bSYour Name 355*5113495bSYour Name Field only valid when Release_source_module is set to release_source_REO 356*5113495bSYour Name 357*5113495bSYour Name 358*5113495bSYour Name Indicates why REO pushed the frame to this release ring 359*5113495bSYour Name 360*5113495bSYour Name <enum 0 reo_error_detected> Reo detected an error an pushed 361*5113495bSYour Name this frame to this queue 362*5113495bSYour Name <enum 1 reo_routing_instruction> Reo pushed the frame to 363*5113495bSYour Name this queue per received routing instructions. No error 364*5113495bSYour Name within REO was detected 365*5113495bSYour Name 366*5113495bSYour Name <legal 0 - 1> 367*5113495bSYour Name */ 368*5113495bSYour Name 369*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 370*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB 24 371*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB 25 372*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK 0x03000000 373*5113495bSYour Name 374*5113495bSYour Name 375*5113495bSYour Name /* Description REO_ERROR_CODE 376*5113495bSYour Name 377*5113495bSYour Name Field only valid when 'Reo_push_reason' set to 'reo_error_detected'. 378*5113495bSYour Name 379*5113495bSYour Name 380*5113495bSYour Name <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor provided 381*5113495bSYour Name in the REO_ENTRANCE ring is set to 0 382*5113495bSYour Name <enum 1 reo_queue_desc_not_valid> Reo queue descriptor valid 383*5113495bSYour Name bit is NOT set 384*5113495bSYour Name <enum 2 ampdu_in_non_ba> AMPDU frame received without BA 385*5113495bSYour Name session having been setup. 386*5113495bSYour Name <enum 3 non_ba_duplicate> Non-BA session, SN equal to SSN, 387*5113495bSYour Name Retry bit set: duplicate frame 388*5113495bSYour Name <enum 4 ba_duplicate> BA session, duplicate frame 389*5113495bSYour Name <enum 5 regular_frame_2k_jump> A normal (management/data 390*5113495bSYour Name frame) received with 2K jump in SN 391*5113495bSYour Name <enum 6 bar_frame_2k_jump> A bar received with 2K jump in 392*5113495bSYour Name SSN 393*5113495bSYour Name <enum 7 regular_frame_OOR> A normal (management/data frame) 394*5113495bSYour Name received with SN falling within the OOR window 395*5113495bSYour Name <enum 8 bar_frame_OOR> A bar received with SSN falling within 396*5113495bSYour Name the OOR window 397*5113495bSYour Name <enum 9 bar_frame_no_ba_session> A bar received without 398*5113495bSYour Name a BA session 399*5113495bSYour Name <enum 10 bar_frame_sn_equals_ssn> A bar received with SSN 400*5113495bSYour Name equal to SN 401*5113495bSYour Name <enum 11 pn_check_failed> PN Check Failed packet. 402*5113495bSYour Name <enum 12 2k_error_handling_flag_set> Frame is forwarded 403*5113495bSYour Name as a result of the 'Seq_2k_error_detected_flag' been set 404*5113495bSYour Name in the REO Queue descriptor 405*5113495bSYour Name <enum 13 pn_error_handling_flag_set> Frame is forwarded 406*5113495bSYour Name as a result of the 'pn_error_detected_flag' been set in 407*5113495bSYour Name the REO Queue descriptor 408*5113495bSYour Name <enum 14 queue_descriptor_blocked_set> Frame is forwarded 409*5113495bSYour Name as a result of the queue descriptor(address) being blocked 410*5113495bSYour Name as SW/FW seems to be currently in the process of making 411*5113495bSYour Name updates to this descriptor... 412*5113495bSYour Name 413*5113495bSYour Name <legal 0-14> 414*5113495bSYour Name */ 415*5113495bSYour Name 416*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 417*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB 26 418*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB 30 419*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 420*5113495bSYour Name 421*5113495bSYour Name 422*5113495bSYour Name /* Description WBM_INTERNAL_ERROR 423*5113495bSYour Name 424*5113495bSYour Name Can only be set by WBM. 425*5113495bSYour Name 426*5113495bSYour Name Is set when WBM got a buffer pointer but the action was 427*5113495bSYour Name to push it to the idle link descriptor ring or do link related 428*5113495bSYour Name activity 429*5113495bSYour Name OR 430*5113495bSYour Name Is set when WBM got a link buffer pointer but the action 431*5113495bSYour Name was to push it to the buffer descriptor ring 432*5113495bSYour Name 433*5113495bSYour Name <legal all> 434*5113495bSYour Name */ 435*5113495bSYour Name 436*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 437*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB 31 438*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB 31 439*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 440*5113495bSYour Name 441*5113495bSYour Name 442*5113495bSYour Name /* Description RX_MPDU_DESC_INFO_DETAILS 443*5113495bSYour Name 444*5113495bSYour Name Consumer: REO/SW/FW 445*5113495bSYour Name Producer: RXDMA 446*5113495bSYour Name 447*5113495bSYour Name General information related to the MPDU whose link descriptors 448*5113495bSYour Name are being released from Rx DMA or REO 449*5113495bSYour Name */ 450*5113495bSYour Name 451*5113495bSYour Name 452*5113495bSYour Name /* Description MSDU_COUNT 453*5113495bSYour Name 454*5113495bSYour Name Consumer: REO/SW/FW 455*5113495bSYour Name Producer: RXDMA 456*5113495bSYour Name 457*5113495bSYour Name The number of MSDUs within the MPDU 458*5113495bSYour Name <legal all> 459*5113495bSYour Name */ 460*5113495bSYour Name 461*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c 462*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 463*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 464*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 465*5113495bSYour Name 466*5113495bSYour Name 467*5113495bSYour Name /* Description FRAGMENT_FLAG 468*5113495bSYour Name 469*5113495bSYour Name Consumer: REO/SW/FW 470*5113495bSYour Name Producer: RXDMA 471*5113495bSYour Name 472*5113495bSYour Name When set, this MPDU is a fragment and REO should forward 473*5113495bSYour Name this fragment MPDU to the REO destination ring without 474*5113495bSYour Name any reorder checks, pn checks or bitmap update. This implies 475*5113495bSYour Name that REO is forwarding the pointer to the MSDU link descriptor. 476*5113495bSYour Name The destination ring is coming from a programmable register 477*5113495bSYour Name setting in REO 478*5113495bSYour Name 479*5113495bSYour Name <legal all> 480*5113495bSYour Name */ 481*5113495bSYour Name 482*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c 483*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 484*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 485*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 486*5113495bSYour Name 487*5113495bSYour Name 488*5113495bSYour Name /* Description MPDU_RETRY_BIT 489*5113495bSYour Name 490*5113495bSYour Name Consumer: REO/SW/FW 491*5113495bSYour Name Producer: RXDMA 492*5113495bSYour Name 493*5113495bSYour Name The retry bit setting from the MPDU header of the received 494*5113495bSYour Name frame 495*5113495bSYour Name <legal all> 496*5113495bSYour Name */ 497*5113495bSYour Name 498*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c 499*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 500*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 501*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 502*5113495bSYour Name 503*5113495bSYour Name 504*5113495bSYour Name /* Description AMPDU_FLAG 505*5113495bSYour Name 506*5113495bSYour Name Consumer: REO/SW/FW 507*5113495bSYour Name Producer: RXDMA 508*5113495bSYour Name 509*5113495bSYour Name When set, the MPDU was received as part of an A-MPDU. 510*5113495bSYour Name <legal all> 511*5113495bSYour Name */ 512*5113495bSYour Name 513*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c 514*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 515*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 516*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 517*5113495bSYour Name 518*5113495bSYour Name 519*5113495bSYour Name /* Description BAR_FRAME 520*5113495bSYour Name 521*5113495bSYour Name Consumer: REO/SW/FW 522*5113495bSYour Name Producer: RXDMA 523*5113495bSYour Name 524*5113495bSYour Name When set, the received frame is a BAR frame. After processing, 525*5113495bSYour Name this frame shall be pushed to SW or deleted. 526*5113495bSYour Name <legal all> 527*5113495bSYour Name */ 528*5113495bSYour Name 529*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c 530*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 531*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 532*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 533*5113495bSYour Name 534*5113495bSYour Name 535*5113495bSYour Name /* Description PN_FIELDS_CONTAIN_VALID_INFO 536*5113495bSYour Name 537*5113495bSYour Name Consumer: REO/SW/FW 538*5113495bSYour Name Producer: RXDMA 539*5113495bSYour Name 540*5113495bSYour Name Copied here by RXDMA from RX_MPDU_END 541*5113495bSYour Name When not set, REO will Not perform a PN sequence number 542*5113495bSYour Name check 543*5113495bSYour Name */ 544*5113495bSYour Name 545*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c 546*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 547*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 548*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 549*5113495bSYour Name 550*5113495bSYour Name 551*5113495bSYour Name /* Description RAW_MPDU 552*5113495bSYour Name 553*5113495bSYour Name Field only valid when first_msdu_in_mpdu_flag is set. 554*5113495bSYour Name 555*5113495bSYour Name When set, the contents in the MSDU buffer contains a 'RAW' 556*5113495bSYour Name MPDU. This 'RAW' MPDU might be spread out over multiple 557*5113495bSYour Name MSDU buffers. 558*5113495bSYour Name <legal all> 559*5113495bSYour Name */ 560*5113495bSYour Name 561*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c 562*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 563*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 564*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 565*5113495bSYour Name 566*5113495bSYour Name 567*5113495bSYour Name /* Description MORE_FRAGMENT_FLAG 568*5113495bSYour Name 569*5113495bSYour Name The More Fragment bit setting from the MPDU header of the 570*5113495bSYour Name received frame 571*5113495bSYour Name 572*5113495bSYour Name <legal all> 573*5113495bSYour Name */ 574*5113495bSYour Name 575*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c 576*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 577*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 578*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 579*5113495bSYour Name 580*5113495bSYour Name 581*5113495bSYour Name /* Description SRC_INFO 582*5113495bSYour Name 583*5113495bSYour Name Source (virtual) device/interface info. associated with 584*5113495bSYour Name this peer 585*5113495bSYour Name 586*5113495bSYour Name This field gets passed on by REO to PPE in the EDMA descriptor 587*5113495bSYour Name ('REO_TO_PPE_RING'). 588*5113495bSYour Name 589*5113495bSYour Name Hamilton v1 used this for 'vdev_id' instead. 590*5113495bSYour Name <legal all> 591*5113495bSYour Name */ 592*5113495bSYour Name 593*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c 594*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 595*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 596*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 597*5113495bSYour Name 598*5113495bSYour Name 599*5113495bSYour Name /* Description MPDU_QOS_CONTROL_VALID 600*5113495bSYour Name 601*5113495bSYour Name When set, the MPDU has a QoS control field. 602*5113495bSYour Name 603*5113495bSYour Name In case of ndp or phy_err, this field will never be set. 604*5113495bSYour Name 605*5113495bSYour Name <legal all> 606*5113495bSYour Name */ 607*5113495bSYour Name 608*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c 609*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 610*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 611*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 612*5113495bSYour Name 613*5113495bSYour Name 614*5113495bSYour Name /* Description TID 615*5113495bSYour Name 616*5113495bSYour Name Field only valid when mpdu_qos_control_valid is set 617*5113495bSYour Name 618*5113495bSYour Name The TID field in the QoS control field 619*5113495bSYour Name <legal all> 620*5113495bSYour Name */ 621*5113495bSYour Name 622*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c 623*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 624*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 625*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 626*5113495bSYour Name 627*5113495bSYour Name 628*5113495bSYour Name /* Description PEER_META_DATA 629*5113495bSYour Name 630*5113495bSYour Name Meta data that SW has programmed in the Peer table entry 631*5113495bSYour Name of the transmitting STA. 632*5113495bSYour Name <legal all> 633*5113495bSYour Name */ 634*5113495bSYour Name 635*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 636*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 637*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 638*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 639*5113495bSYour Name 640*5113495bSYour Name 641*5113495bSYour Name /* Description RX_MSDU_DESC_INFO_DETAILS 642*5113495bSYour Name 643*5113495bSYour Name Consumer: TQM/SW 644*5113495bSYour Name Producer: SW/SCH(from TXPCU, PDG) /WBM (from RXDMA) 645*5113495bSYour Name 646*5113495bSYour Name In case of RXDMA or REO releasing Rx MSDU link descriptors,' 647*5113495bSYour Name WBM fills this field with Rx_msdu_desc_info_details when 648*5113495bSYour Name releasing the MSDUs to SW (Maple/Spruce FR59859). 649*5113495bSYour Name */ 650*5113495bSYour Name 651*5113495bSYour Name 652*5113495bSYour Name /* Description FIRST_MSDU_IN_MPDU_FLAG 653*5113495bSYour Name 654*5113495bSYour Name Parsed from RX_MSDU_END TLV . In the case MSDU spans over 655*5113495bSYour Name multiple buffers, this field will be valid in the Last 656*5113495bSYour Name buffer used by the MSDU 657*5113495bSYour Name 658*5113495bSYour Name <enum 0 Not_first_msdu> This is not the first MSDU in the 659*5113495bSYour Name MPDU. 660*5113495bSYour Name <enum 1 first_msdu> This MSDU is the first one in the MPDU. 661*5113495bSYour Name 662*5113495bSYour Name 663*5113495bSYour Name <legal all> 664*5113495bSYour Name */ 665*5113495bSYour Name 666*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 667*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 668*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 669*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 670*5113495bSYour Name 671*5113495bSYour Name 672*5113495bSYour Name /* Description LAST_MSDU_IN_MPDU_FLAG 673*5113495bSYour Name 674*5113495bSYour Name Consumer: WBM/REO/SW/FW 675*5113495bSYour Name Producer: RXDMA 676*5113495bSYour Name 677*5113495bSYour Name Parsed from RX_MSDU_END TLV . In the case MSDU spans over 678*5113495bSYour Name multiple buffers, this field will be valid in the Last 679*5113495bSYour Name buffer used by the MSDU 680*5113495bSYour Name 681*5113495bSYour Name <enum 0 Not_last_msdu> There are more MSDUs linked to this 682*5113495bSYour Name MSDU that belongs to this MPDU 683*5113495bSYour Name <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 684*5113495bSYour Name This setting is only allowed in combination with 'Msdu_continuation' 685*5113495bSYour Name set to 0. This implies that when an msdu is spread out over 686*5113495bSYour Name multiple buffers and thus msdu_continuation is set, only 687*5113495bSYour Name for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 688*5113495bSYour Name be set. 689*5113495bSYour Name 690*5113495bSYour Name When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 691*5113495bSYour Name are set, the MPDU that this MSDU belongs to only contains 692*5113495bSYour Name a single MSDU. 693*5113495bSYour Name 694*5113495bSYour Name 695*5113495bSYour Name <legal all> 696*5113495bSYour Name */ 697*5113495bSYour Name 698*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 699*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 700*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 701*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 702*5113495bSYour Name 703*5113495bSYour Name 704*5113495bSYour Name /* Description MSDU_CONTINUATION 705*5113495bSYour Name 706*5113495bSYour Name When set, this MSDU buffer was not able to hold the entire 707*5113495bSYour Name MSDU. The next buffer will therefor contain additional 708*5113495bSYour Name information related to this MSDU. 709*5113495bSYour Name 710*5113495bSYour Name <legal all> 711*5113495bSYour Name */ 712*5113495bSYour Name 713*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 714*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 715*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 716*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 717*5113495bSYour Name 718*5113495bSYour Name 719*5113495bSYour Name /* Description MSDU_LENGTH 720*5113495bSYour Name 721*5113495bSYour Name Parsed from RX_MSDU_START TLV . In the case MSDU spans over 722*5113495bSYour Name multiple buffers, this field will be valid in the First 723*5113495bSYour Name buffer used by MSDU. 724*5113495bSYour Name 725*5113495bSYour Name Full MSDU length in bytes after decapsulation. 726*5113495bSYour Name 727*5113495bSYour Name This field is still valid for MPDU frames without A-MSDU. 728*5113495bSYour Name It still represents MSDU length after decapsulation 729*5113495bSYour Name 730*5113495bSYour Name Or in case of RAW MPDUs, it indicates the length of the 731*5113495bSYour Name entire MPDU (without FCS field) 732*5113495bSYour Name <legal all> 733*5113495bSYour Name */ 734*5113495bSYour Name 735*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 736*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 737*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 738*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 739*5113495bSYour Name 740*5113495bSYour Name 741*5113495bSYour Name /* Description MSDU_DROP 742*5113495bSYour Name 743*5113495bSYour Name Parsed from RX_MSDU_END TLV . In the case MSDU spans over 744*5113495bSYour Name multiple buffers, this field will be valid in the Last 745*5113495bSYour Name buffer used by the MSDU 746*5113495bSYour Name 747*5113495bSYour Name When set, REO shall drop this MSDU and not forward it to 748*5113495bSYour Name any other ring... 749*5113495bSYour Name <legal all> 750*5113495bSYour Name */ 751*5113495bSYour Name 752*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 753*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 754*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 755*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 756*5113495bSYour Name 757*5113495bSYour Name 758*5113495bSYour Name /* Description SA_IS_VALID 759*5113495bSYour Name 760*5113495bSYour Name Parsed from RX_MSDU_END TLV . In the case MSDU spans over 761*5113495bSYour Name multiple buffers, this field will be valid in the Last 762*5113495bSYour Name buffer used by the MSDU 763*5113495bSYour Name 764*5113495bSYour Name Indicates that OLE found a valid SA entry for this MSDU 765*5113495bSYour Name <legal all> 766*5113495bSYour Name */ 767*5113495bSYour Name 768*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 769*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 770*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 771*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 772*5113495bSYour Name 773*5113495bSYour Name 774*5113495bSYour Name /* Description DA_IS_VALID 775*5113495bSYour Name 776*5113495bSYour Name Parsed from RX_MSDU_END TLV . In the case MSDU spans over 777*5113495bSYour Name multiple buffers, this field will be valid in the Last 778*5113495bSYour Name buffer used by the MSDU 779*5113495bSYour Name 780*5113495bSYour Name Indicates that OLE found a valid DA entry for this MSDU 781*5113495bSYour Name <legal all> 782*5113495bSYour Name */ 783*5113495bSYour Name 784*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 785*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 786*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 787*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 788*5113495bSYour Name 789*5113495bSYour Name 790*5113495bSYour Name /* Description DA_IS_MCBC 791*5113495bSYour Name 792*5113495bSYour Name Field Only valid if "da_is_valid" is set 793*5113495bSYour Name 794*5113495bSYour Name Indicates the DA address was a Multicast of Broadcast address 795*5113495bSYour Name for this MSDU 796*5113495bSYour Name <legal all> 797*5113495bSYour Name */ 798*5113495bSYour Name 799*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 800*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 801*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 802*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 803*5113495bSYour Name 804*5113495bSYour Name 805*5113495bSYour Name /* Description L3_HEADER_PADDING_MSB 806*5113495bSYour Name 807*5113495bSYour Name Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 808*5113495bSYour Name as the LSB is always zero) 809*5113495bSYour Name Number of bytes padded to make sure that the L3 header will 810*5113495bSYour Name always start of a Dword boundary 811*5113495bSYour Name <legal all> 812*5113495bSYour Name */ 813*5113495bSYour Name 814*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 815*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 816*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 817*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 818*5113495bSYour Name 819*5113495bSYour Name 820*5113495bSYour Name /* Description TCP_UDP_CHKSUM_FAIL 821*5113495bSYour Name 822*5113495bSYour Name Passed on from 'RX_ATTENTION' TLV 823*5113495bSYour Name Indicates that the computed checksum did not match the checksum 824*5113495bSYour Name in the TCP/UDP header. 825*5113495bSYour Name <legal all> 826*5113495bSYour Name */ 827*5113495bSYour Name 828*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 829*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 830*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 831*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 832*5113495bSYour Name 833*5113495bSYour Name 834*5113495bSYour Name /* Description IP_CHKSUM_FAIL 835*5113495bSYour Name 836*5113495bSYour Name Passed on from 'RX_ATTENTION' TLV 837*5113495bSYour Name Indicates that the computed checksum did not match the checksum 838*5113495bSYour Name in the IP header. 839*5113495bSYour Name <legal all> 840*5113495bSYour Name */ 841*5113495bSYour Name 842*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 843*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 844*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 845*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 846*5113495bSYour Name 847*5113495bSYour Name 848*5113495bSYour Name /* Description FR_DS 849*5113495bSYour Name 850*5113495bSYour Name Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 851*5113495bSYour Name TLV 852*5113495bSYour Name Set if the 'from DS' bit is set in the frame control. 853*5113495bSYour Name <legal all> 854*5113495bSYour Name */ 855*5113495bSYour Name 856*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 857*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 858*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 859*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 860*5113495bSYour Name 861*5113495bSYour Name 862*5113495bSYour Name /* Description TO_DS 863*5113495bSYour Name 864*5113495bSYour Name Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 865*5113495bSYour Name TLV 866*5113495bSYour Name Set if the 'to DS' bit is set in the frame control. 867*5113495bSYour Name <legal all> 868*5113495bSYour Name */ 869*5113495bSYour Name 870*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 871*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 872*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 873*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 874*5113495bSYour Name 875*5113495bSYour Name 876*5113495bSYour Name /* Description INTRA_BSS 877*5113495bSYour Name 878*5113495bSYour Name This packet needs intra-BSS routing by SW as the 'vdev_id' 879*5113495bSYour Name for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 880*5113495bSYour Name that this MSDU was got in. 881*5113495bSYour Name 882*5113495bSYour Name <legal all> 883*5113495bSYour Name */ 884*5113495bSYour Name 885*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 886*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 887*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 888*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 889*5113495bSYour Name 890*5113495bSYour Name 891*5113495bSYour Name /* Description DEST_CHIP_ID 892*5113495bSYour Name 893*5113495bSYour Name If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 894*5113495bSYour Name to support intra-BSS routing with multi-chip multi-link 895*5113495bSYour Name operation. 896*5113495bSYour Name 897*5113495bSYour Name This indicates into which chip's TCL the packet should be 898*5113495bSYour Name queued. 899*5113495bSYour Name 900*5113495bSYour Name <legal all> 901*5113495bSYour Name */ 902*5113495bSYour Name 903*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 904*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 905*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 906*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 907*5113495bSYour Name 908*5113495bSYour Name 909*5113495bSYour Name /* Description DECAP_FORMAT 910*5113495bSYour Name 911*5113495bSYour Name Indicates the format after decapsulation: 912*5113495bSYour Name 913*5113495bSYour Name <enum 0 RAW> No encapsulation 914*5113495bSYour Name <enum 1 Native_WiFi> 915*5113495bSYour Name <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 916*5113495bSYour Name 917*5113495bSYour Name <enum 3 802_3> Indicate Ethernet 918*5113495bSYour Name 919*5113495bSYour Name <legal all> 920*5113495bSYour Name */ 921*5113495bSYour Name 922*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 923*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 924*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 925*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 926*5113495bSYour Name 927*5113495bSYour Name 928*5113495bSYour Name /* Description DEST_CHIP_PMAC_ID 929*5113495bSYour Name 930*5113495bSYour Name If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 931*5113495bSYour Name to support intra-BSS routing with multi-chip multi-link 932*5113495bSYour Name operation. 933*5113495bSYour Name 934*5113495bSYour Name This indicates into which link/'vdev' the packet should 935*5113495bSYour Name be queued in TCL. 936*5113495bSYour Name 937*5113495bSYour Name <legal all> 938*5113495bSYour Name */ 939*5113495bSYour Name 940*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000014 941*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 942*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 943*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 944*5113495bSYour Name 945*5113495bSYour Name 946*5113495bSYour Name /* Description BUFFER_PHYS_ADDR_31_0 947*5113495bSYour Name 948*5113495bSYour Name LSB 32 bits of the physical address from the MSDU's buffer 949*5113495bSYour Name address info, for debug 950*5113495bSYour Name */ 951*5113495bSYour Name 952*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET 0x00000018 953*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB 0 954*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB 31 955*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK 0xffffffff 956*5113495bSYour Name 957*5113495bSYour Name 958*5113495bSYour Name /* Description BUFFER_PHYS_ADDR_39_32 959*5113495bSYour Name 960*5113495bSYour Name MSB 8 bits of the physical address from the MSDU's buffer 961*5113495bSYour Name address info, for debug 962*5113495bSYour Name */ 963*5113495bSYour Name 964*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET 0x0000001c 965*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB 0 966*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB 7 967*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK 0x000000ff 968*5113495bSYour Name 969*5113495bSYour Name 970*5113495bSYour Name /* Description SW_BUFFER_COOKIE 971*5113495bSYour Name 972*5113495bSYour Name 'Sw_buffer_cookie' field of the MSDU's buffer address info 973*5113495bSYour Name used to fill 'Buffer_virt_addr_*,' for debug 974*5113495bSYour Name */ 975*5113495bSYour Name 976*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET 0x0000001c 977*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB 8 978*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB 27 979*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK 0x0fffff00 980*5113495bSYour Name 981*5113495bSYour Name 982*5113495bSYour Name /* Description LOOPING_COUNT 983*5113495bSYour Name 984*5113495bSYour Name Consumer: WBM/SW/FW 985*5113495bSYour Name Producer: SW/TQM/RXDMA/REO/SWITCH 986*5113495bSYour Name 987*5113495bSYour Name If WBM_internal_error is set, this descriptor is sent to 988*5113495bSYour Name the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count 989*5113495bSYour Name is used to indicate an error code. 990*5113495bSYour Name 991*5113495bSYour Name The values reported are documented further in the WBM MLD 992*5113495bSYour Name doc. 993*5113495bSYour Name 994*5113495bSYour Name If WBM_internal_error is not set, the following holds. 995*5113495bSYour Name 996*5113495bSYour Name A count value that indicates the number of times the producer 997*5113495bSYour Name of entries into the Buffer Manager Ring has looped around 998*5113495bSYour Name the ring. 999*5113495bSYour Name At initialization time, this value is set to 0. On the first 1000*5113495bSYour Name loop, this value is set to 1. After the max value is reached 1001*5113495bSYour Name allowed by the number of bits for this field, the count 1002*5113495bSYour Name value continues with 0 again. 1003*5113495bSYour Name 1004*5113495bSYour Name In case SW is the consumer of the ring entries, it can use 1005*5113495bSYour Name this field to figure out up to where the producer of entries 1006*5113495bSYour Name has created new entries. This eliminates the need to check 1007*5113495bSYour Name where the "head pointer' of the ring is located once the 1008*5113495bSYour Name SW starts processing an interrupt indicating that new entries 1009*5113495bSYour Name have been put into this ring... 1010*5113495bSYour Name 1011*5113495bSYour Name Also note that SW if it wants only needs to look at the 1012*5113495bSYour Name LSB bit of this count value. 1013*5113495bSYour Name <legal all> 1014*5113495bSYour Name */ 1015*5113495bSYour Name 1016*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c 1017*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB 28 1018*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB 31 1019*5113495bSYour Name #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK 0xf0000000 1020*5113495bSYour Name 1021*5113495bSYour Name 1022*5113495bSYour Name 1023*5113495bSYour Name #endif // WBM2SW_COMPLETION_RING_RX 1024