1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _WBM2SW_COMPLETION_RING_RX_H_ 27 #define _WBM2SW_COMPLETION_RING_RX_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "rx_msdu_desc_info.h" 32 #include "rx_mpdu_desc_info.h" 33 #define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8 34 35 36 struct wbm2sw_completion_ring_rx { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t buffer_virt_addr_31_0 : 32; // [31:0] 39 uint32_t buffer_virt_addr_63_32 : 32; // [31:0] 40 uint32_t release_source_module : 3, // [2:0] 41 bm_action : 3, // [5:3] 42 buffer_or_desc_type : 3, // [8:6] 43 return_buffer_manager : 4, // [12:9] 44 reserved_2a : 2, // [14:13] 45 cache_id : 1, // [15:15] 46 cookie_conversion_status : 1, // [16:16] 47 rxdma_push_reason : 2, // [18:17] 48 rxdma_error_code : 5, // [23:19] 49 reo_push_reason : 2, // [25:24] 50 reo_error_code : 5, // [30:26] 51 wbm_internal_error : 1; // [31:31] 52 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 53 struct rx_msdu_desc_info rx_msdu_desc_info_details; 54 uint32_t buffer_phys_addr_31_0 : 32; // [31:0] 55 uint32_t buffer_phys_addr_39_32 : 8, // [7:0] 56 sw_buffer_cookie : 20, // [27:8] 57 looping_count : 4; // [31:28] 58 #else 59 uint32_t buffer_virt_addr_31_0 : 32; // [31:0] 60 uint32_t buffer_virt_addr_63_32 : 32; // [31:0] 61 uint32_t wbm_internal_error : 1, // [31:31] 62 reo_error_code : 5, // [30:26] 63 reo_push_reason : 2, // [25:24] 64 rxdma_error_code : 5, // [23:19] 65 rxdma_push_reason : 2, // [18:17] 66 cookie_conversion_status : 1, // [16:16] 67 cache_id : 1, // [15:15] 68 reserved_2a : 2, // [14:13] 69 return_buffer_manager : 4, // [12:9] 70 buffer_or_desc_type : 3, // [8:6] 71 bm_action : 3, // [5:3] 72 release_source_module : 3; // [2:0] 73 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 74 struct rx_msdu_desc_info rx_msdu_desc_info_details; 75 uint32_t buffer_phys_addr_31_0 : 32; // [31:0] 76 uint32_t looping_count : 4, // [31:28] 77 sw_buffer_cookie : 20, // [27:8] 78 buffer_phys_addr_39_32 : 8; // [7:0] 79 #endif 80 }; 81 82 83 /* Description BUFFER_VIRT_ADDR_31_0 84 85 Lower 32 bits of the 64-bit virtual address corresponding 86 to the MSDU being released 87 <legal all> 88 */ 89 90 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 91 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB 0 92 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB 31 93 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 94 95 96 /* Description BUFFER_VIRT_ADDR_63_32 97 98 Upper 32 bits of the 64-bit virtual address corresponding 99 to the MSDU being released 100 <legal all> 101 */ 102 103 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 104 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB 0 105 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB 31 106 #define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 107 108 109 /* Description RELEASE_SOURCE_MODULE 110 111 Indicates which module initiated the release of this buffer 112 or descriptor 113 114 <enum 1 release_source_RXDMA> RXDMA released this buffer 115 or descriptor 116 <enum 2 release_source_REO> REO released this buffer or 117 descriptor 118 <enum 5 release_source_FW_RX> FW released this buffer or 119 descriptor 120 <enum 4 release_source_SW_RX> SW released this buffer or 121 descriptor 122 <enum 0 release_source_TQM> DO NOT USE 123 <enum 3 release_source_FW_TX> DO NOT USE 124 <enum 6 release_source_SW_TX> DO NOT USE 125 <legal 0-6> 126 */ 127 128 #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 129 #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 130 #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 131 #define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 132 133 134 /* Description BM_ACTION 135 136 Consumer: WBM/SW/FW 137 Producer: SW/TQM/RXDMA/REO/SWITCH 138 139 Field only valid when the field return_buffer_manager in 140 the Released_buff_or_desc_addr_info indicates: 141 WBM_IDLE_BUF_LIST or 142 WBM_IDLE_DESC_LIST 143 144 An MSDU extension descriptor shall never be marked as WBM 145 being the 'owner', and thus WBM will forward it to FW/SW 146 147 148 <enum 0 Put_in_idle_list> Put the buffer or descriptor back 149 in the idle list. In case of MSDU or MDPU link descriptor, 150 BM does not need to check to release any individual MSDU 151 buffers 152 153 <enum 1 release_msdu_list > This BM action can only be used 154 in combination with buffer_or_desc_type being msdu_link_descriptor. 155 Field first_msdu_index points out which MSDU pointer in 156 the MSDU link descriptor is the first of an MPDU that is 157 released. 158 BM shall release all the MSDU buffers linked to this first 159 MSDU buffer pointer. All related MSDU buffer pointer entries 160 shall be set to value 0, which represents the 'NULL" pointer. 161 When all MSDU buffer pointers in the MSDU link descriptor 162 are 'NULL', the MSDU link descriptor itself shall also 163 be released. 164 165 <enum 2 Put_in_idle_list_expanded> CURRENTLY NOT IMPLEMENTED.... 166 167 Put the buffer or descriptor back in the idle list. Only 168 valid in combination with buffer_or_desc_type indicating 169 MDPU_link_descriptor. 170 BM shall release the MPDU link descriptor as well as all 171 MSDUs that are linked to the MPDUs in this descriptor. 172 173 174 TODO: Any restrictions? 175 <legal 0-2> 176 */ 177 178 #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET 0x00000008 179 #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB 3 180 #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB 5 181 #define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK 0x00000038 182 183 184 /* Description BUFFER_OR_DESC_TYPE 185 186 Consumer: WBM/SW/FW 187 Producer: SW/TQM/RXDMA/REO/SWITCH 188 189 Field only valid when WBM is marked as the return_buffer_manager 190 in the Released_Buffer_address_info 191 192 Indicates that type of buffer or descriptor is being released 193 194 195 <enum 0 MSDU_rel_buffer> The address points to an MSDU buffer 196 197 <enum 1 msdu_link_descriptor> The address points to an TX 198 MSDU link descriptor 199 <enum 2 mpdu_link_descriptor> The address points to an MPDU 200 link descriptor 201 <enum 3 msdu_ext_descriptor > The address points to an MSDU 202 extension descriptor. 203 In case BM finds this one in a release ring, it passes it 204 on to FW... 205 <enum 4 queue_ext_descriptor> The address points to an TQM 206 queue extension descriptor. WBM should treat this is the 207 same way as a link descriptor. That is, put the 128 byte 208 buffer back in the link buffer idle list. 209 210 TODO: Any restrictions? 211 <legal 0-4> 212 */ 213 214 #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 215 #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 216 #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 217 #define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 218 219 220 /* Description RETURN_BUFFER_MANAGER 221 222 'Return_buffer_manager' field of the MSDU's buffer address 223 info, for debug 224 */ 225 226 #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 227 #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB 9 228 #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB 12 229 #define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 230 231 232 /* Description RESERVED_2A 233 234 <legal 0> 235 */ 236 237 #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET 0x00000008 238 #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB 13 239 #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB 14 240 #define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK 0x00006000 241 242 243 /* Description CACHE_ID 244 245 Indicates the WBM cache the MSDU was released from 246 <legal all> 247 */ 248 249 #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET 0x00000008 250 #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB 15 251 #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB 15 252 #define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK 0x00008000 253 254 255 /* Description COOKIE_CONVERSION_STATUS 256 257 0: 'Sw_buffer_cookie' not converted to 'Buffer_virt_addr' 258 259 1: 'Sw_buffer_cookie' coverted to 'Buffer_virt_addr' 260 <legal 1> 261 */ 262 263 #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 264 #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 265 #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 266 #define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 267 268 269 /* Description RXDMA_PUSH_REASON 270 271 Field only valid when Release_source_module is set to release_source_RXDMA 272 273 274 Indicates why rxdma pushed the frame to this ring 275 276 <enum 0 rxdma_error_detected> RXDMA detected an error an 277 pushed this frame to this queue 278 <enum 1 rxdma_routing_instruction> RXDMA pushed the frame 279 to this queue per received routing instructions. No error 280 within RXDMA was detected 281 <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 282 result the MSDU link descriptor might not have the "last_msdu_in_mpdu_flag" 283 set, but instead WBM might just see a NULL pointer in the 284 MSDU link descriptor. This is to be considered a normal 285 condition for this scenario. 286 287 <legal 0 - 2> 288 */ 289 290 #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 291 #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB 17 292 #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB 18 293 #define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 294 295 296 /* Description RXDMA_ERROR_CODE 297 298 Field only valid when 'rxdma_push_reason' set to 'rxdma_error_detected'. 299 300 301 <enum 0 rxdma_overflow_err>MPDU frame is not complete due 302 to a FIFO overflow error in RXPCU. 303 <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete 304 due to receiving incomplete MPDU from the PHY 305 <enum 2 rxdma_fcs_err>FCS check on the MPDU frame failed 306 307 <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption error 308 or CRYPTO received an encrypted frame, but did not get 309 a valid corresponding key id in the peer entry. 310 <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC error 311 312 <enum 5 rxdma_unecrypted_err>CRYPTO reported an unencrypted 313 frame error when encrypted was expected 314 <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU length 315 error 316 <enum 7 rxdma_msdu_limit_err>RX OLE reported that max number 317 of MSDUs allowed in an MPDU got exceeded 318 <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing error 319 320 <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU 321 parsing error 322 <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout 323 during SA search 324 <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout 325 during DA search 326 <enum 12 rxdma_flow_timeout_err>RX OLE reported a timeout 327 during flow search 328 <enum 13 rxdma_flush_request>RXDMA received a flush request 329 330 <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU 331 present as well as a fragmented MPDU. A-MSDU defragmentation 332 is not supported in Lithium SW so this is treated as an 333 error. 334 <enum 15 rxdma_multicast_echo_err>RX OLE reported a multicast 335 echo 336 <enum 16 rxdma_amsdu_addr_mismatch_err>RX OLE reported an 337 A-MSDU with either 'from DS = 0' with an SA mismatching 338 TA or 'to DS = 0' with a DA mismatching RA. 339 <enum 17 rxdma_unauthorized_wds_err>RX PCU reported that 340 Rx peer entry did not indicate 'authorized_to_send_WDS' 341 and also indicated 'from DS = to DS = 1.' 342 <enum 18 rxdma_groupcast_amsdu_or_wds_err>RX PCU reported 343 a broadcast or multicast RA as well as either A-MSDU present 344 or 'from DS = to DS = 1.' 345 */ 346 347 #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 348 #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB 19 349 #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB 23 350 #define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 351 352 353 /* Description REO_PUSH_REASON 354 355 Field only valid when Release_source_module is set to release_source_REO 356 357 358 Indicates why REO pushed the frame to this release ring 359 360 <enum 0 reo_error_detected> Reo detected an error an pushed 361 this frame to this queue 362 <enum 1 reo_routing_instruction> Reo pushed the frame to 363 this queue per received routing instructions. No error 364 within REO was detected 365 366 <legal 0 - 1> 367 */ 368 369 #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 370 #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB 24 371 #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB 25 372 #define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK 0x03000000 373 374 375 /* Description REO_ERROR_CODE 376 377 Field only valid when 'Reo_push_reason' set to 'reo_error_detected'. 378 379 380 <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor provided 381 in the REO_ENTRANCE ring is set to 0 382 <enum 1 reo_queue_desc_not_valid> Reo queue descriptor valid 383 bit is NOT set 384 <enum 2 ampdu_in_non_ba> AMPDU frame received without BA 385 session having been setup. 386 <enum 3 non_ba_duplicate> Non-BA session, SN equal to SSN, 387 Retry bit set: duplicate frame 388 <enum 4 ba_duplicate> BA session, duplicate frame 389 <enum 5 regular_frame_2k_jump> A normal (management/data 390 frame) received with 2K jump in SN 391 <enum 6 bar_frame_2k_jump> A bar received with 2K jump in 392 SSN 393 <enum 7 regular_frame_OOR> A normal (management/data frame) 394 received with SN falling within the OOR window 395 <enum 8 bar_frame_OOR> A bar received with SSN falling within 396 the OOR window 397 <enum 9 bar_frame_no_ba_session> A bar received without 398 a BA session 399 <enum 10 bar_frame_sn_equals_ssn> A bar received with SSN 400 equal to SN 401 <enum 11 pn_check_failed> PN Check Failed packet. 402 <enum 12 2k_error_handling_flag_set> Frame is forwarded 403 as a result of the 'Seq_2k_error_detected_flag' been set 404 in the REO Queue descriptor 405 <enum 13 pn_error_handling_flag_set> Frame is forwarded 406 as a result of the 'pn_error_detected_flag' been set in 407 the REO Queue descriptor 408 <enum 14 queue_descriptor_blocked_set> Frame is forwarded 409 as a result of the queue descriptor(address) being blocked 410 as SW/FW seems to be currently in the process of making 411 updates to this descriptor... 412 413 <legal 0-14> 414 */ 415 416 #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 417 #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB 26 418 #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB 30 419 #define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 420 421 422 /* Description WBM_INTERNAL_ERROR 423 424 Can only be set by WBM. 425 426 Is set when WBM got a buffer pointer but the action was 427 to push it to the idle link descriptor ring or do link related 428 activity 429 OR 430 Is set when WBM got a link buffer pointer but the action 431 was to push it to the buffer descriptor ring 432 433 <legal all> 434 */ 435 436 #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 437 #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB 31 438 #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB 31 439 #define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 440 441 442 /* Description RX_MPDU_DESC_INFO_DETAILS 443 444 Consumer: REO/SW/FW 445 Producer: RXDMA 446 447 General information related to the MPDU whose link descriptors 448 are being released from Rx DMA or REO 449 */ 450 451 452 /* Description MSDU_COUNT 453 454 Consumer: REO/SW/FW 455 Producer: RXDMA 456 457 The number of MSDUs within the MPDU 458 <legal all> 459 */ 460 461 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c 462 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 463 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 464 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 465 466 467 /* Description FRAGMENT_FLAG 468 469 Consumer: REO/SW/FW 470 Producer: RXDMA 471 472 When set, this MPDU is a fragment and REO should forward 473 this fragment MPDU to the REO destination ring without 474 any reorder checks, pn checks or bitmap update. This implies 475 that REO is forwarding the pointer to the MSDU link descriptor. 476 The destination ring is coming from a programmable register 477 setting in REO 478 479 <legal all> 480 */ 481 482 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c 483 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 484 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 485 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 486 487 488 /* Description MPDU_RETRY_BIT 489 490 Consumer: REO/SW/FW 491 Producer: RXDMA 492 493 The retry bit setting from the MPDU header of the received 494 frame 495 <legal all> 496 */ 497 498 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c 499 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 500 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 501 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 502 503 504 /* Description AMPDU_FLAG 505 506 Consumer: REO/SW/FW 507 Producer: RXDMA 508 509 When set, the MPDU was received as part of an A-MPDU. 510 <legal all> 511 */ 512 513 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c 514 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 515 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 516 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 517 518 519 /* Description BAR_FRAME 520 521 Consumer: REO/SW/FW 522 Producer: RXDMA 523 524 When set, the received frame is a BAR frame. After processing, 525 this frame shall be pushed to SW or deleted. 526 <legal all> 527 */ 528 529 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c 530 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 531 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 532 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 533 534 535 /* Description PN_FIELDS_CONTAIN_VALID_INFO 536 537 Consumer: REO/SW/FW 538 Producer: RXDMA 539 540 Copied here by RXDMA from RX_MPDU_END 541 When not set, REO will Not perform a PN sequence number 542 check 543 */ 544 545 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c 546 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 547 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 548 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 549 550 551 /* Description RAW_MPDU 552 553 Field only valid when first_msdu_in_mpdu_flag is set. 554 555 When set, the contents in the MSDU buffer contains a 'RAW' 556 MPDU. This 'RAW' MPDU might be spread out over multiple 557 MSDU buffers. 558 <legal all> 559 */ 560 561 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c 562 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 563 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 564 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 565 566 567 /* Description MORE_FRAGMENT_FLAG 568 569 The More Fragment bit setting from the MPDU header of the 570 received frame 571 572 <legal all> 573 */ 574 575 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c 576 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 577 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 578 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 579 580 581 /* Description SRC_INFO 582 583 Source (virtual) device/interface info. associated with 584 this peer 585 586 This field gets passed on by REO to PPE in the EDMA descriptor 587 ('REO_TO_PPE_RING'). 588 589 Hamilton v1 used this for 'vdev_id' instead. 590 <legal all> 591 */ 592 593 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c 594 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 595 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 596 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 597 598 599 /* Description MPDU_QOS_CONTROL_VALID 600 601 When set, the MPDU has a QoS control field. 602 603 In case of ndp or phy_err, this field will never be set. 604 605 <legal all> 606 */ 607 608 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c 609 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 610 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 611 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 612 613 614 /* Description TID 615 616 Field only valid when mpdu_qos_control_valid is set 617 618 The TID field in the QoS control field 619 <legal all> 620 */ 621 622 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c 623 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 624 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 625 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 626 627 628 /* Description PEER_META_DATA 629 630 Meta data that SW has programmed in the Peer table entry 631 of the transmitting STA. 632 <legal all> 633 */ 634 635 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 636 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 637 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 638 #define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 639 640 641 /* Description RX_MSDU_DESC_INFO_DETAILS 642 643 Consumer: TQM/SW 644 Producer: SW/SCH(from TXPCU, PDG) /WBM (from RXDMA) 645 646 In case of RXDMA or REO releasing Rx MSDU link descriptors,' 647 WBM fills this field with Rx_msdu_desc_info_details when 648 releasing the MSDUs to SW (Maple/Spruce FR59859). 649 */ 650 651 652 /* Description FIRST_MSDU_IN_MPDU_FLAG 653 654 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 655 multiple buffers, this field will be valid in the Last 656 buffer used by the MSDU 657 658 <enum 0 Not_first_msdu> This is not the first MSDU in the 659 MPDU. 660 <enum 1 first_msdu> This MSDU is the first one in the MPDU. 661 662 663 <legal all> 664 */ 665 666 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 667 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 668 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 669 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 670 671 672 /* Description LAST_MSDU_IN_MPDU_FLAG 673 674 Consumer: WBM/REO/SW/FW 675 Producer: RXDMA 676 677 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 678 multiple buffers, this field will be valid in the Last 679 buffer used by the MSDU 680 681 <enum 0 Not_last_msdu> There are more MSDUs linked to this 682 MSDU that belongs to this MPDU 683 <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 684 This setting is only allowed in combination with 'Msdu_continuation' 685 set to 0. This implies that when an msdu is spread out over 686 multiple buffers and thus msdu_continuation is set, only 687 for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 688 be set. 689 690 When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 691 are set, the MPDU that this MSDU belongs to only contains 692 a single MSDU. 693 694 695 <legal all> 696 */ 697 698 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 699 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 700 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 701 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 702 703 704 /* Description MSDU_CONTINUATION 705 706 When set, this MSDU buffer was not able to hold the entire 707 MSDU. The next buffer will therefor contain additional 708 information related to this MSDU. 709 710 <legal all> 711 */ 712 713 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 714 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 715 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 716 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 717 718 719 /* Description MSDU_LENGTH 720 721 Parsed from RX_MSDU_START TLV . In the case MSDU spans over 722 multiple buffers, this field will be valid in the First 723 buffer used by MSDU. 724 725 Full MSDU length in bytes after decapsulation. 726 727 This field is still valid for MPDU frames without A-MSDU. 728 It still represents MSDU length after decapsulation 729 730 Or in case of RAW MPDUs, it indicates the length of the 731 entire MPDU (without FCS field) 732 <legal all> 733 */ 734 735 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 736 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 737 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 738 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 739 740 741 /* Description MSDU_DROP 742 743 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 744 multiple buffers, this field will be valid in the Last 745 buffer used by the MSDU 746 747 When set, REO shall drop this MSDU and not forward it to 748 any other ring... 749 <legal all> 750 */ 751 752 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 753 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 754 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 755 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 756 757 758 /* Description SA_IS_VALID 759 760 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 761 multiple buffers, this field will be valid in the Last 762 buffer used by the MSDU 763 764 Indicates that OLE found a valid SA entry for this MSDU 765 <legal all> 766 */ 767 768 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 769 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 770 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 771 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 772 773 774 /* Description DA_IS_VALID 775 776 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 777 multiple buffers, this field will be valid in the Last 778 buffer used by the MSDU 779 780 Indicates that OLE found a valid DA entry for this MSDU 781 <legal all> 782 */ 783 784 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 785 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 786 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 787 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 788 789 790 /* Description DA_IS_MCBC 791 792 Field Only valid if "da_is_valid" is set 793 794 Indicates the DA address was a Multicast of Broadcast address 795 for this MSDU 796 <legal all> 797 */ 798 799 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 800 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 801 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 802 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 803 804 805 /* Description L3_HEADER_PADDING_MSB 806 807 Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 808 as the LSB is always zero) 809 Number of bytes padded to make sure that the L3 header will 810 always start of a Dword boundary 811 <legal all> 812 */ 813 814 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 815 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 816 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 817 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 818 819 820 /* Description TCP_UDP_CHKSUM_FAIL 821 822 Passed on from 'RX_ATTENTION' TLV 823 Indicates that the computed checksum did not match the checksum 824 in the TCP/UDP header. 825 <legal all> 826 */ 827 828 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 829 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 830 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 831 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 832 833 834 /* Description IP_CHKSUM_FAIL 835 836 Passed on from 'RX_ATTENTION' TLV 837 Indicates that the computed checksum did not match the checksum 838 in the IP header. 839 <legal all> 840 */ 841 842 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 843 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 844 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 845 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 846 847 848 /* Description FR_DS 849 850 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 851 TLV 852 Set if the 'from DS' bit is set in the frame control. 853 <legal all> 854 */ 855 856 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 857 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 858 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 859 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 860 861 862 /* Description TO_DS 863 864 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 865 TLV 866 Set if the 'to DS' bit is set in the frame control. 867 <legal all> 868 */ 869 870 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 871 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 872 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 873 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 874 875 876 /* Description INTRA_BSS 877 878 This packet needs intra-BSS routing by SW as the 'vdev_id' 879 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 880 that this MSDU was got in. 881 882 <legal all> 883 */ 884 885 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 886 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 887 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 888 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 889 890 891 /* Description DEST_CHIP_ID 892 893 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 894 to support intra-BSS routing with multi-chip multi-link 895 operation. 896 897 This indicates into which chip's TCL the packet should be 898 queued. 899 900 <legal all> 901 */ 902 903 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 904 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 905 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 906 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 907 908 909 /* Description DECAP_FORMAT 910 911 Indicates the format after decapsulation: 912 913 <enum 0 RAW> No encapsulation 914 <enum 1 Native_WiFi> 915 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 916 917 <enum 3 802_3> Indicate Ethernet 918 919 <legal all> 920 */ 921 922 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 923 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 924 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 925 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 926 927 928 /* Description DEST_CHIP_PMAC_ID 929 930 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 931 to support intra-BSS routing with multi-chip multi-link 932 operation. 933 934 This indicates into which link/'vdev' the packet should 935 be queued in TCL. 936 937 <legal all> 938 */ 939 940 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000014 941 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 942 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 943 #define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 944 945 946 /* Description BUFFER_PHYS_ADDR_31_0 947 948 LSB 32 bits of the physical address from the MSDU's buffer 949 address info, for debug 950 */ 951 952 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET 0x00000018 953 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB 0 954 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB 31 955 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK 0xffffffff 956 957 958 /* Description BUFFER_PHYS_ADDR_39_32 959 960 MSB 8 bits of the physical address from the MSDU's buffer 961 address info, for debug 962 */ 963 964 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET 0x0000001c 965 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB 0 966 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB 7 967 #define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK 0x000000ff 968 969 970 /* Description SW_BUFFER_COOKIE 971 972 'Sw_buffer_cookie' field of the MSDU's buffer address info 973 used to fill 'Buffer_virt_addr_*,' for debug 974 */ 975 976 #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET 0x0000001c 977 #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB 8 978 #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB 27 979 #define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK 0x0fffff00 980 981 982 /* Description LOOPING_COUNT 983 984 Consumer: WBM/SW/FW 985 Producer: SW/TQM/RXDMA/REO/SWITCH 986 987 If WBM_internal_error is set, this descriptor is sent to 988 the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count 989 is used to indicate an error code. 990 991 The values reported are documented further in the WBM MLD 992 doc. 993 994 If WBM_internal_error is not set, the following holds. 995 996 A count value that indicates the number of times the producer 997 of entries into the Buffer Manager Ring has looped around 998 the ring. 999 At initialization time, this value is set to 0. On the first 1000 loop, this value is set to 1. After the max value is reached 1001 allowed by the number of bits for this field, the count 1002 value continues with 0 again. 1003 1004 In case SW is the consumer of the ring entries, it can use 1005 this field to figure out up to where the producer of entries 1006 has created new entries. This eliminates the need to check 1007 where the "head pointer' of the ring is located once the 1008 SW starts processing an interrupt indicating that new entries 1009 have been put into this ring... 1010 1011 Also note that SW if it wants only needs to look at the 1012 LSB bit of this count value. 1013 <legal all> 1014 */ 1015 1016 #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c 1017 #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB 28 1018 #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB 31 1019 #define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK 0xf0000000 1020 1021 1022 1023 #endif // WBM2SW_COMPLETION_RING_RX 1024