1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _WBM2SW_COMPLETION_RING_TX_H_ 27 #define _WBM2SW_COMPLETION_RING_TX_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "tx_rate_stats_info.h" 32 #define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_TX 8 33 34 35 struct wbm2sw_completion_ring_tx { 36 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 37 uint32_t buffer_virt_addr_31_0 : 32; // [31:0] 38 uint32_t buffer_virt_addr_63_32 : 32; // [31:0] 39 uint32_t release_source_module : 3, // [2:0] 40 cache_id : 1, // [3:3] 41 reserved_2a : 2, // [5:4] 42 buffer_or_desc_type : 3, // [8:6] 43 return_buffer_manager : 4, // [12:9] 44 tqm_release_reason : 4, // [16:13] 45 rbm_override_valid : 1, // [17:17] 46 sw_buffer_cookie_11_0 : 12, // [29:18] 47 cookie_conversion_status : 1, // [30:30] 48 wbm_internal_error : 1; // [31:31] 49 uint32_t tqm_status_number : 24, // [23:0] 50 transmit_count : 7, // [30:24] 51 sw_release_details_valid : 1; // [31:31] 52 uint32_t ack_frame_rssi : 8, // [7:0] 53 first_msdu : 1, // [8:8] 54 last_msdu : 1, // [9:9] 55 fw_tx_notify_frame : 3, // [12:10] 56 buffer_timestamp : 19; // [31:13] 57 struct tx_rate_stats_info tx_rate_stats; 58 uint32_t sw_peer_id : 16, // [15:0] 59 tid : 4, // [19:16] 60 sw_buffer_cookie_19_12 : 8, // [27:20] 61 looping_count : 4; // [31:28] 62 #else 63 uint32_t buffer_virt_addr_31_0 : 32; // [31:0] 64 uint32_t buffer_virt_addr_63_32 : 32; // [31:0] 65 uint32_t wbm_internal_error : 1, // [31:31] 66 cookie_conversion_status : 1, // [30:30] 67 sw_buffer_cookie_11_0 : 12, // [29:18] 68 rbm_override_valid : 1, // [17:17] 69 tqm_release_reason : 4, // [16:13] 70 return_buffer_manager : 4, // [12:9] 71 buffer_or_desc_type : 3, // [8:6] 72 reserved_2a : 2, // [5:4] 73 cache_id : 1, // [3:3] 74 release_source_module : 3; // [2:0] 75 uint32_t sw_release_details_valid : 1, // [31:31] 76 transmit_count : 7, // [30:24] 77 tqm_status_number : 24; // [23:0] 78 uint32_t buffer_timestamp : 19, // [31:13] 79 fw_tx_notify_frame : 3, // [12:10] 80 last_msdu : 1, // [9:9] 81 first_msdu : 1, // [8:8] 82 ack_frame_rssi : 8; // [7:0] 83 struct tx_rate_stats_info tx_rate_stats; 84 uint32_t looping_count : 4, // [31:28] 85 sw_buffer_cookie_19_12 : 8, // [27:20] 86 tid : 4, // [19:16] 87 sw_peer_id : 16; // [15:0] 88 #endif 89 }; 90 91 92 /* Description BUFFER_VIRT_ADDR_31_0 93 94 Lower 32 bits of the 64-bit virtual address corresponding 95 to the MSDU being released 96 <legal all> 97 */ 98 99 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 100 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_LSB 0 101 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MSB 31 102 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 103 104 105 /* Description BUFFER_VIRT_ADDR_63_32 106 107 Upper 32 bits of the 64-bit virtual address corresponding 108 to the MSDU being released 109 <legal all> 110 */ 111 112 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 113 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_LSB 0 114 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MSB 31 115 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 116 117 118 /* Description RELEASE_SOURCE_MODULE 119 120 Indicates which module initiated the release of this buffer 121 or descriptor 122 123 <enum 1 release_source_RXDMA> DO NOT USE 124 <enum 2 release_source_REO> DO NOT USE 125 <enum 5 release_source_FW_RX> DO NOT USE 126 <enum 4 release_source_SW_RX> DO NOT USE 127 <enum 0 release_source_TQM> TQM released this buffer or 128 descriptor 129 <enum 3 release_source_FW_TX> FW released this buffer or 130 descriptor 131 <enum 6 release_source_SW_TX> SW released this buffer or 132 descriptor 133 <legal 0-6> 134 */ 135 136 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 137 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 138 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 139 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 140 141 142 /* Description CACHE_ID 143 144 To improve WBM performance, out-of-order completions may 145 be allowed to process multiple MPDUs in parallel. 146 147 The MSDUs released from each cache would be in order so 'First_msdu' 148 and this field together can be used by SW to reorder the 149 completions back to the original order by keeping all MSDUs 150 of an MPDU from one cache together before switching to 151 the next MPDU (from either cache). 152 <legal all> 153 */ 154 155 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_OFFSET 0x00000008 156 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_LSB 3 157 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MSB 3 158 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MASK 0x00000008 159 160 161 /* Description RESERVED_2A 162 163 <legal 0> 164 */ 165 166 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_OFFSET 0x00000008 167 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_LSB 4 168 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MSB 5 169 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MASK 0x00000030 170 171 172 /* Description BUFFER_OR_DESC_TYPE 173 174 Consumer: WBM/SW/FW 175 Producer: SW/TQM/RXDMA/REO/SWITCH 176 177 Field only valid when WBM is marked as the return_buffer_manager 178 in the Released_Buffer_address_info 179 180 Indicates that type of buffer or descriptor is being released 181 182 183 <enum 0 MSDU_rel_buffer> The address points to an MSDU buffer 184 185 <enum 1 msdu_link_descriptor> The address points to an TX 186 MSDU link descriptor 187 <enum 2 mpdu_link_descriptor> The address points to an MPDU 188 link descriptor 189 <enum 3 msdu_ext_descriptor > The address points to an MSDU 190 extension descriptor. 191 In case BM finds this one in a release ring, it passes it 192 on to FW... 193 <enum 4 queue_ext_descriptor> The address points to an TQM 194 queue extension descriptor. WBM should treat this is the 195 same way as a link descriptor. That is, put the 128 byte 196 buffer back in the link buffer idle list. 197 198 <legal 0-4> 199 */ 200 201 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 202 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 203 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 204 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 205 206 207 /* Description RETURN_BUFFER_MANAGER 208 209 'Return_buffer_manager' field of the MSDU's buffer address 210 info, for debug 211 */ 212 213 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 214 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_LSB 9 215 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MSB 12 216 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 217 218 219 /* Description TQM_RELEASE_REASON 220 221 Consumer: WBM/SW/FW 222 Producer: TQM 223 224 Field only valid when Release_source_module is set to release_source_TQM 225 226 227 (rr = Release Reason) 228 <enum 0 tqm_rr_frame_acked> frame is removed because an 229 ACK of BA for it was received 230 <enum 1 tqm_rr_rem_cmd_rem> frame is removed because a remove 231 command of type "Remove_mpdus" initiated by SW 232 <enum 2 tqm_rr_rem_cmd_tx> frame is removed because a remove 233 command of type "Remove_transmitted_mpdus" initiated by 234 SW 235 <enum 3 tqm_rr_rem_cmd_notx> frame is removed because a 236 remove command of type "Remove_untransmitted_mpdus" initiated 237 by SW 238 <enum 4 tqm_rr_rem_cmd_aged> frame is removed because a 239 remove command of type "Remove_aged_mpdus" or "Remove_aged_msdus" 240 initiated by SW 241 <enum 5 tqm_fw_reason1> frame is removed because a remove 242 command where fw indicated that remove reason is fw_reason1 243 244 <enum 6 tqm_fw_reason2> frame is removed because a remove 245 command where fw indicated that remove reason is fw_reason1 246 247 <enum 7 tqm_fw_reason3> frame is removed because a remove 248 command where fw indicated that remove reason is fw_reason1 249 250 <enum 8 tqm_rr_rem_cmd_disable_queue> frame is removed because 251 a remove command of type "remove_mpdus_and_disable_queue" 252 or "remove_msdus_and_disable_flow" initiated by SW 253 <enum 9 tqm_rr_rem_cmd_till_nonmatching> frame is removed 254 because remove command of type "remove_till_nonmatching_mpdu" 255 initiated by SW 256 <enum 10 tqm_rr_drop_threshold> frame is dropped at TQM 257 entrance due to one of slow/medium/hard drop threshold criteria 258 259 <enum 11 tqm_rr_link_desc_unavailable> frame is dropped 260 at TQM entrance due to the WBM2TQM_LINK_RING having fewer 261 descriptors than a threshold programmed in TQM 262 <enum 12 tqm_rr_drop_or_invalid_msdu> frame is dropped at 263 TQM entrance due to 'TQM_Drop_frame' being set or "null" 264 MSDU flow pointer or MSDU flow pointer 'Flow_valid' being 265 zero or MSDU_length being zero 266 <enum 13 tqm_rr_multicast_drop> frame is dropped at TQM 267 entrance due to 'TQM_Drop_frame' being set with 'TCL_drop_reason' 268 set to TCL_multicast_drop_for_vdev. 269 <enum 14 tqm_rr_vdev_mismatch_drop> frame is dropped at 270 TQM entrance due to 'TQM_Drop_frame' being set with 'TCL_drop_reason' 271 set to TCL_vdev_id_mismatch_drop. 272 Waikiki v1 and Hamilton v2 used value 12 for this. 273 274 <legal 0-14> 275 */ 276 277 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 278 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB 13 279 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MSB 16 280 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 281 282 283 /* Description RBM_OVERRIDE_VALID 284 285 This is set to 0 for Tx cases not involving reinjection, 286 and set to 1 for TQM release cases requiring FW reinjection 287 (HastingsPrime FR54309). 288 289 When set to 1, WBM releases the MSDU buffers to FW and overrides 290 the tx_rate_stats field with words 2 and 3 of the 'TX_MSDU_DETAILS' 291 structure, for FW reinjection of these MSDUs (HastingsPrime 292 FR54309). 293 294 When releasing to host SW, this will be 0 if there is no 295 misprogramming. 296 <legal 0> 297 */ 298 299 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 300 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_LSB 17 301 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MSB 17 302 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 303 304 305 /* Description SW_BUFFER_COOKIE_11_0 306 307 LSB 12 bits of the 'Sw_buffer_cookie' field of the MSDU's 308 buffer address info used to fill 'Buffer_virt_addr_*,' 309 for debug 310 */ 311 312 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_OFFSET 0x00000008 313 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_LSB 18 314 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MSB 29 315 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MASK 0x3ffc0000 316 317 318 /* Description COOKIE_CONVERSION_STATUS 319 320 0: 'Sw_buffer_cookie' not converted to 'Buffer_virt_addr' 321 322 1: 'Sw_buffer_cookie' coverted to 'Buffer_virt_addr' 323 <legal 1> 324 */ 325 326 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 327 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 328 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 329 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 330 331 332 /* Description WBM_INTERNAL_ERROR 333 334 Can only be set by WBM. 335 336 Is set when WBM got a buffer pointer but the action was 337 to push it to the idle link descriptor ring or do link related 338 activity 339 OR 340 Is set when WBM got a link buffer pointer but the action 341 was to push it to the buffer descriptor ring 342 343 <legal all> 344 */ 345 346 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 347 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_LSB 31 348 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MSB 31 349 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 350 351 352 /* Description TQM_STATUS_NUMBER 353 354 Field only valid when Release_source_module is set to release_source_TQM 355 356 357 The value in this field is equal to value of the 'TQM_CMD_Number' 358 field from the TQM command or the 'TQM_add_cmd_Number' field 359 from the TQM entrance ring descriptor LSB 24-bits. 360 361 This field helps to correlate the statuses with the TQM 362 commands. 363 364 NOTE that SW could program this number to be equal to the 365 PPDU_ID number in case direct correlation with the PPDU 366 ID is desired 367 368 <legal all> 369 */ 370 371 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c 372 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_LSB 0 373 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MSB 23 374 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff 375 376 377 /* Description TRANSMIT_COUNT 378 379 Field only valid when Release_source_module is set to release_source_TQM 380 381 382 The number of times this frame has been transmitted 383 */ 384 385 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c 386 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_LSB 24 387 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MSB 30 388 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 389 390 391 /* Description SW_RELEASE_DETAILS_VALID 392 393 Consumer: SW 394 Producer: WBM 395 396 When set, some WBM specific release info for SW is valid. 397 398 This is set when WMB got a 'release_msdu_list' command from 399 TQM and the return buffer manager is not WMB. WBM will 400 then de-aggregate all the MSDUs and pass them one at a time 401 on to the 'buffer owner' 402 403 <legal all> 404 */ 405 406 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c 407 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 408 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 409 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 410 411 412 /* Description ACK_FRAME_RSSI 413 414 This field is only valid when the source is TQM. 415 416 If this frame is removed as the result of the reception 417 of an ACK or BA, this field indicates the RSSI of the received 418 ACK or BA frame. 419 420 When the frame is removed as result of a direct remove command 421 from the SW, this field is set to 0x0 (which is never 422 a valid value when real RSSI is available) 423 424 <legal all> 425 */ 426 427 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 428 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_LSB 0 429 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MSB 7 430 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff 431 432 433 /* Description FIRST_MSDU 434 435 Field only valid when SW_release_details_valid is set. 436 437 Consumer: SW 438 Producer: WBM 439 440 When set, this MSDU is the first MSDU pointed to in the 'release_msdu_list' 441 command. 442 <legal all> 443 */ 444 445 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_OFFSET 0x00000010 446 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_LSB 8 447 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MSB 8 448 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MASK 0x00000100 449 450 451 /* Description LAST_MSDU 452 453 Field only valid when SW_release_details_valid is set. 454 455 Consumer: SW 456 Producer: WBM 457 458 When set, this MSDU is the last MSDU pointed to in the 'release_msdu_list' 459 command. 460 <legal all> 461 */ 462 463 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_OFFSET 0x00000010 464 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_LSB 9 465 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MSB 9 466 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MASK 0x00000200 467 468 469 /* Description FW_TX_NOTIFY_FRAME 470 471 Field only valid when SW_release_details_valid is set. 472 473 Consumer: SW 474 Producer: WBM 475 476 This is the FW_tx_notify_frame field from the TX_MSDU_DETAILS 477 for this frame from the MSDU link descriptor 478 <legal all> 479 */ 480 481 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 482 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 483 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 484 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 485 486 487 /* Description BUFFER_TIMESTAMP 488 489 Field only valid when SW_release_details_valid is set. 490 491 Consumer: SW 492 Producer: WBM 493 494 This is the Buffer_timestamp field from the TX_MSDU_DETAILS 495 for this frame from the MSDU link descriptor. 496 497 Timestamp in units determined by the UMCMN 'TX_TIMESTAMP_RESOLUTION_SELECT' 498 register 499 500 Waikiki v1 and Hamilton used units of 1024 µs. 501 <legal all> 502 */ 503 504 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 505 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_LSB 13 506 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MSB 31 507 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 508 509 510 /* Description TX_RATE_STATS 511 512 Consumer: TQM/SW 513 Producer: SW/SCH(from TXPCU, PDG) /WBM (from RXDMA) 514 515 Details for command execution tracking purposes. 516 */ 517 518 519 /* Description TX_RATE_STATS_INFO_VALID 520 521 When set all other fields in this STRUCT contain valid info. 522 523 524 When clear, none of the other fields contain valid info. 525 526 <legal all> 527 */ 528 529 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 530 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 531 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 532 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 533 534 535 /* Description TRANSMIT_BW 536 537 Field only valid when Tx_rate_stats_info_valid is set 538 539 Indicates the BW of the upcoming transmission that shall 540 likely start in about 3 -4 us on the medium 541 542 <enum_type BW_ENUM> 543 */ 544 545 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 546 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 547 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 548 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e 549 550 551 /* Description TRANSMIT_PKT_TYPE 552 553 Field only valid when Tx_rate_stats_info_valid is set 554 555 Field filled in by PDG. 556 Not valid when in SW transmit mode 557 558 The packet type 559 <enum_type PKT_TYPE_ENUM> 560 */ 561 562 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 563 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 564 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 565 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 566 567 568 /* Description TRANSMIT_STBC 569 570 Field only valid when Tx_rate_stats_info_valid is set 571 572 Field filled in by PDG. 573 Not valid when in SW transmit mode 574 575 When set, STBC transmission rate was used. 576 */ 577 578 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 579 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 580 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 581 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 582 583 584 /* Description TRANSMIT_LDPC 585 586 Field only valid when Tx_rate_stats_info_valid is set 587 588 Field filled in by PDG. 589 Not valid when in SW transmit mode 590 591 When set, use LDPC transmission rates 592 */ 593 594 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 595 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 596 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 597 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 598 599 600 /* Description TRANSMIT_SGI 601 602 Field only valid when Tx_rate_stats_info_valid is set 603 604 Field filled in by PDG. 605 Not valid when in SW transmit mode 606 607 Specify the right GI for HE-Ranging NDPs (11az)/Short NDP. 608 609 610 <enum 0 0_8_us_sgi > Legacy normal GI. Can also be used 611 for HE 612 <enum 1 0_4_us_sgi > Legacy short GI. Can also be used 613 for HE 614 <enum 2 1_6_us_sgi > HE related GI 615 <enum 3 3_2_us_sgi > HE related GI 616 <legal 0 - 3> 617 */ 618 619 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 620 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 621 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 622 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 623 624 625 /* Description TRANSMIT_MCS 626 627 Field only valid when Tx_rate_stats_info_valid is set 628 629 Field filled in by PDG. 630 Not valid when in SW transmit mode 631 632 For details, refer to MCS_TYPE description 633 <legal all> 634 */ 635 636 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 637 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 638 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 639 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 640 641 642 /* Description OFDMA_TRANSMISSION 643 644 Field only valid when Tx_rate_stats_info_valid is set 645 646 Field filled in by PDG. 647 648 Set when the transmission was an OFDMA transmission (DL 649 or UL). 650 <legal all> 651 */ 652 653 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 654 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 655 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 656 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 657 658 659 /* Description TONES_IN_RU 660 661 Field only valid when Tx_rate_stats_info_valid is set 662 663 Field filled in by PDG. 664 Not valid when in SW transmit mode 665 666 The number of tones in the RU used. 667 <legal all> 668 */ 669 670 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 671 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 672 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 673 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 674 675 676 /* Description RESERVED_0A 677 678 <legal 0> 679 */ 680 681 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014 682 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_RESERVED_0A_LSB 29 683 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_RESERVED_0A_MSB 31 684 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_RESERVED_0A_MASK 0xe0000000 685 686 687 /* Description PPDU_TRANSMISSION_TSF 688 689 Field only valid when Tx_rate_stats_info_valid is set 690 691 Based on a HWSCH configuration register setting, this field 692 either contains: 693 694 Lower 32 bits of the TSF, snapshot of this value when transmission 695 of the PPDU containing the frame finished. 696 OR 697 Lower 32 bits of the TSF, snapshot of this value when transmission 698 of the PPDU containing the frame started 699 700 <legal all> 701 */ 702 703 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 704 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 705 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 706 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff 707 708 709 /* Description SW_PEER_ID 710 711 Field only valid when Release_source_module is set to release_source_TQM 712 713 714 1) Release of msdu buffer due to drop_frame = 1. Flow is 715 not fetched and hence sw_peer_id and tid = 0 716 buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason 717 = e_num 1 tqm_rr_rem_cmd_rem 718 719 720 2) Release of msdu buffer due to Flow is not fetched and 721 hence sw_peer_id and tid = 0 722 buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason 723 = e_num 1 tqm_rr_rem_cmd_rem 724 725 726 3) Release of msdu link due to remove_mpdu or acked_mpdu 727 command. 728 buffer_or_desc_type = e_num1 msdu_link_descriptortqm_release_reason 729 can be:e_num 1 tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx 730 731 e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged (this 732 e_num is used for REMOVE_MPDU as well as REMOVE_MSDU). 733 734 Sw_peer_id from the TX_MSDU_FLOW descriptor or TX_MPDU_QUEUE 735 descriptor 736 <legal all> 737 */ 738 739 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_OFFSET 0x0000001c 740 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_LSB 0 741 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MSB 15 742 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MASK 0x0000ffff 743 744 745 /* Description TID 746 747 Field only valid when Release_source_module is set to release_source_TQM 748 749 750 1) Release of msdu buffer due to drop_frame = 1. Flow is 751 not fetched and hence sw_peer_id and tid = 0 752 buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason 753 = e_num 1 tqm_rr_rem_cmd_rem 754 755 756 2) Release of msdu buffer due to Flow is not fetched and 757 hence sw_peer_id and tid = 0 758 buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason 759 = e_num 1 tqm_rr_rem_cmd_rem 760 761 762 3) Release of msdu link due to remove_mpdu or acked_mpdu 763 command. 764 buffer_or_desc_type = e_num1 msdu_link_descriptortqm_release_reason 765 can be:e_num 1 tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx 766 767 e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged (this 768 e_num is used for REMOVE_MPDU as well as REMOVE_MSDU). 769 770 771 This field represents the TID from the TX_MSDU_FLOW descriptor 772 or TX_MPDU_QUEUE descriptor 773 774 <legal all> 775 */ 776 777 #define WBM2SW_COMPLETION_RING_TX_TID_OFFSET 0x0000001c 778 #define WBM2SW_COMPLETION_RING_TX_TID_LSB 16 779 #define WBM2SW_COMPLETION_RING_TX_TID_MSB 19 780 #define WBM2SW_COMPLETION_RING_TX_TID_MASK 0x000f0000 781 782 783 /* Description SW_BUFFER_COOKIE_19_12 784 785 MSB 8 bits of the 'Sw_buffer_cookie' field of the MSDU's 786 buffer address info used to fill 'Buffer_virt_addr_*,' 787 for debug. 788 WBM shall have configuration to copy 'TQM_Status_Number_31_24' 789 from the WBM input descriptor here instead. 790 */ 791 792 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_OFFSET 0x0000001c 793 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_LSB 20 794 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MSB 27 795 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MASK 0x0ff00000 796 797 798 /* Description LOOPING_COUNT 799 800 Consumer: WBM/SW/FW 801 Producer: SW/TQM/RXDMA/REO/SWITCH 802 803 If WBM_internal_error is set, this descriptor is sent to 804 the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count 805 is used to indicate an error code. 806 807 The values reported are documented further in the WBM MLD 808 doc. 809 810 If WBM_internal_error is not set, the following holds. 811 812 A count value that indicates the number of times the producer 813 of entries into the Buffer Manager Ring has looped around 814 the ring. 815 At initialization time, this value is set to 0. On the first 816 loop, this value is set to 1. After the max value is reached 817 allowed by the number of bits for this field, the count 818 value continues with 0 again. 819 820 In case SW is the consumer of the ring entries, it can use 821 this field to figure out up to where the producer of entries 822 has created new entries. This eliminates the need to check 823 where the "head pointer' of the ring is located once the 824 SW starts processing an interrupt indicating that new entries 825 have been put into this ring... 826 827 Also note that SW if it wants only needs to look at the 828 LSB bit of this count value. 829 <legal all> 830 */ 831 832 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c 833 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_LSB 28 834 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MSB 31 835 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MASK 0xf0000000 836 837 838 839 #endif // WBM2SW_COMPLETION_RING_TX 840