1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _WBM_LINK_DESCRIPTOR_RING_H_ 27 #define _WBM_LINK_DESCRIPTOR_RING_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "buffer_addr_info.h" 32 #define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2 33 34 35 struct wbm_link_descriptor_ring { 36 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 37 struct buffer_addr_info desc_addr_info; 38 #else 39 struct buffer_addr_info desc_addr_info; 40 #endif 41 }; 42 43 44 /* Description DESC_ADDR_INFO 45 46 Consumer: WBM 47 Producer: WBM 48 49 Details of the physical address of the buffer + source buffer 50 owner + some SW meta data 51 All modules getting this link descriptor address info, shall 52 keep all the 64 bits in this descriptor together and eventually 53 all 64 bits shall be given back to WBM when the link descriptor 54 is released. 55 */ 56 57 58 /* Description BUFFER_ADDR_31_0 59 60 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 61 descriptor OR Link Descriptor 62 63 In case of 'NULL' pointer, this field is set to 0 64 <legal all> 65 */ 66 67 #define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 68 #define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 69 #define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 70 #define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 71 72 73 /* Description BUFFER_ADDR_39_32 74 75 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 76 descriptor OR Link Descriptor 77 78 In case of 'NULL' pointer, this field is set to 0 79 <legal all> 80 */ 81 82 #define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 83 #define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 84 #define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 85 #define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 86 87 88 /* Description RETURN_BUFFER_MANAGER 89 90 Consumer: WBM 91 Producer: SW/FW 92 93 In case of 'NULL' pointer, this field is set to 0 94 95 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 96 descriptor OR link descriptor that is being pointed to 97 shall be returned after the frame has been processed. It 98 is used by WBM for routing purposes. 99 100 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 101 to the WMB buffer idle list 102 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 103 to the WBM idle link descriptor idle list, where the chip 104 0 WBM is chosen in case of a multi-chip config 105 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 106 to the chip 1 WBM idle link descriptor idle list 107 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 108 to the chip 2 WBM idle link descriptor idle list 109 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 110 returned to chip 3 WBM idle link descriptor idle list 111 <enum 4 FW_BM> This buffer shall be returned to the FW 112 <enum 5 SW0_BM> This buffer shall be returned to the SW, 113 ring 0 114 <enum 6 SW1_BM> This buffer shall be returned to the SW, 115 ring 1 116 <enum 7 SW2_BM> This buffer shall be returned to the SW, 117 ring 2 118 <enum 8 SW3_BM> This buffer shall be returned to the SW, 119 ring 3 120 <enum 9 SW4_BM> This buffer shall be returned to the SW, 121 ring 4 122 <enum 10 SW5_BM> This buffer shall be returned to the SW, 123 ring 5 124 <enum 11 SW6_BM> This buffer shall be returned to the SW, 125 ring 6 126 127 <legal 0-12> 128 */ 129 130 #define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 131 #define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 132 #define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 133 #define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 134 135 136 /* Description SW_BUFFER_COOKIE 137 138 Cookie field exclusively used by SW. 139 140 In case of 'NULL' pointer, this field is set to 0 141 142 HW ignores the contents, accept that it passes the programmed 143 value on to other descriptors together with the physical 144 address 145 146 Field can be used by SW to for example associate the buffers 147 physical address with the virtual address 148 The bit definitions as used by SW are within SW HLD specification 149 150 151 NOTE1: 152 The three most significant bits can have a special meaning 153 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 154 and field transmit_bw_restriction is set 155 156 In case of NON punctured transmission: 157 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 158 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 159 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 160 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 161 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 162 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 163 Sw_buffer_cookie[19:18] = 2'b11: reserved 164 165 In case of punctured transmission: 166 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 167 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 168 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 169 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 170 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 171 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 172 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 173 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 174 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 175 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 176 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 177 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 178 Sw_buffer_cookie[19:18] = 2'b11: reserved 179 180 Note: a punctured transmission is indicated by the presence 181 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 182 183 <legal all> 184 */ 185 186 #define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 187 #define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 188 #define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 189 #define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 190 191 192 193 #endif // WBM_LINK_DESCRIPTOR_RING 194