1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _WBM_RELEASE_RING_TX_H_ 27 #define _WBM_RELEASE_RING_TX_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "tx_rate_stats_info.h" 32 #include "buffer_addr_info.h" 33 #define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 8 34 35 36 struct wbm_release_ring_tx { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 struct buffer_addr_info released_buff_or_desc_addr_info; 39 uint32_t release_source_module : 3, // [2:0] 40 bm_action : 3, // [5:3] 41 buffer_or_desc_type : 3, // [8:6] 42 first_msdu_index : 4, // [12:9] 43 tqm_release_reason : 4, // [16:13] 44 rbm_override_valid : 1, // [17:17] 45 rbm_override : 4, // [21:18] 46 reserved_2a : 7, // [28:22] 47 cache_id : 1, // [29:29] 48 cookie_conversion_status : 1, // [30:30] 49 wbm_internal_error : 1; // [31:31] 50 uint32_t tqm_status_number : 24, // [23:0] 51 transmit_count : 7, // [30:24] 52 sw_release_details_valid : 1; // [31:31] 53 uint32_t ack_frame_rssi : 8, // [7:0] 54 first_msdu : 1, // [8:8] 55 last_msdu : 1, // [9:9] 56 fw_tx_notify_frame : 3, // [12:10] 57 buffer_timestamp : 19; // [31:13] 58 struct tx_rate_stats_info tx_rate_stats; 59 uint32_t sw_peer_id : 16, // [15:0] 60 tid : 4, // [19:16] 61 tqm_status_number_31_24 : 8, // [27:20] 62 looping_count : 4; // [31:28] 63 #else 64 struct buffer_addr_info released_buff_or_desc_addr_info; 65 uint32_t wbm_internal_error : 1, // [31:31] 66 cookie_conversion_status : 1, // [30:30] 67 cache_id : 1, // [29:29] 68 reserved_2a : 7, // [28:22] 69 rbm_override : 4, // [21:18] 70 rbm_override_valid : 1, // [17:17] 71 tqm_release_reason : 4, // [16:13] 72 first_msdu_index : 4, // [12:9] 73 buffer_or_desc_type : 3, // [8:6] 74 bm_action : 3, // [5:3] 75 release_source_module : 3; // [2:0] 76 uint32_t sw_release_details_valid : 1, // [31:31] 77 transmit_count : 7, // [30:24] 78 tqm_status_number : 24; // [23:0] 79 uint32_t buffer_timestamp : 19, // [31:13] 80 fw_tx_notify_frame : 3, // [12:10] 81 last_msdu : 1, // [9:9] 82 first_msdu : 1, // [8:8] 83 ack_frame_rssi : 8; // [7:0] 84 struct tx_rate_stats_info tx_rate_stats; 85 uint32_t looping_count : 4, // [31:28] 86 tqm_status_number_31_24 : 8, // [27:20] 87 tid : 4, // [19:16] 88 sw_peer_id : 16; // [15:0] 89 #endif 90 }; 91 92 93 /* Description RELEASED_BUFF_OR_DESC_ADDR_INFO 94 95 Consumer: WBM/SW/FW 96 Producer: SW/TQM/RXDMA/REO/SWITCH 97 98 Details of the physical address of the buffer or link descriptor 99 that is being released. Note that within this descriptor, 100 WBM will look at the 'owner' of the released buffer/descriptor 101 and forward it to SW/FW is WBM is not the owner. 102 */ 103 104 105 /* Description BUFFER_ADDR_31_0 106 107 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 108 descriptor OR Link Descriptor 109 110 In case of 'NULL' pointer, this field is set to 0 111 <legal all> 112 */ 113 114 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 115 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 116 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 117 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 118 119 120 /* Description BUFFER_ADDR_39_32 121 122 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 123 descriptor OR Link Descriptor 124 125 In case of 'NULL' pointer, this field is set to 0 126 <legal all> 127 */ 128 129 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 130 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 131 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 132 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 133 134 135 /* Description RETURN_BUFFER_MANAGER 136 137 Consumer: WBM 138 Producer: SW/FW 139 140 In case of 'NULL' pointer, this field is set to 0 141 142 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 143 descriptor OR link descriptor that is being pointed to 144 shall be returned after the frame has been processed. It 145 is used by WBM for routing purposes. 146 147 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 148 to the WMB buffer idle list 149 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 150 to the WBM idle link descriptor idle list, where the chip 151 0 WBM is chosen in case of a multi-chip config 152 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 153 to the chip 1 WBM idle link descriptor idle list 154 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 155 to the chip 2 WBM idle link descriptor idle list 156 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 157 returned to chip 3 WBM idle link descriptor idle list 158 <enum 4 FW_BM> This buffer shall be returned to the FW 159 <enum 5 SW0_BM> This buffer shall be returned to the SW, 160 ring 0 161 <enum 6 SW1_BM> This buffer shall be returned to the SW, 162 ring 1 163 <enum 7 SW2_BM> This buffer shall be returned to the SW, 164 ring 2 165 <enum 8 SW3_BM> This buffer shall be returned to the SW, 166 ring 3 167 <enum 9 SW4_BM> This buffer shall be returned to the SW, 168 ring 4 169 <enum 10 SW5_BM> This buffer shall be returned to the SW, 170 ring 5 171 <enum 11 SW6_BM> This buffer shall be returned to the SW, 172 ring 6 173 174 <legal 0-12> 175 */ 176 177 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 178 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 179 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 180 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 181 182 183 /* Description SW_BUFFER_COOKIE 184 185 Cookie field exclusively used by SW. 186 187 In case of 'NULL' pointer, this field is set to 0 188 189 HW ignores the contents, accept that it passes the programmed 190 value on to other descriptors together with the physical 191 address 192 193 Field can be used by SW to for example associate the buffers 194 physical address with the virtual address 195 The bit definitions as used by SW are within SW HLD specification 196 197 198 NOTE1: 199 The three most significant bits can have a special meaning 200 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 201 and field transmit_bw_restriction is set 202 203 In case of NON punctured transmission: 204 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 205 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 206 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 207 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 208 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 209 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 210 Sw_buffer_cookie[19:18] = 2'b11: reserved 211 212 In case of punctured transmission: 213 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 214 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 215 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 216 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 217 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 218 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 219 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 220 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 221 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 222 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 223 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 224 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 225 Sw_buffer_cookie[19:18] = 2'b11: reserved 226 227 Note: a punctured transmission is indicated by the presence 228 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 229 230 <legal all> 231 */ 232 233 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 234 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 235 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 236 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 237 238 239 /* Description RELEASE_SOURCE_MODULE 240 241 Indicates which module initiated the release of this buffer 242 or descriptor 243 244 <enum 1 release_source_RXDMA> DO NOT USE 245 <enum 2 release_source_REO> DO NOT USE 246 <enum 5 release_source_FW_RX> DO NOT USE 247 <enum 4 release_source_SW_RX> DO NOT USE 248 <enum 0 release_source_TQM> TQM released this buffer or 249 descriptor 250 <enum 3 release_source_FW_TX> FW released this buffer or 251 descriptor 252 <enum 6 release_source_SW_TX> SW released this buffer or 253 descriptor 254 <legal 0-6> 255 */ 256 257 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 258 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 259 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 260 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 261 262 263 /* Description BM_ACTION 264 265 Consumer: WBM/SW/FW 266 Producer: SW/TQM/RXDMA/REO/SWITCH 267 268 Field only valid when the field return_buffer_manager in 269 the Released_buff_or_desc_addr_info indicates: 270 WBM_IDLE_BUF_LIST or 271 WBM_IDLE_DESC_LIST 272 273 An MSDU extension descriptor shall never be marked as WBM 274 being the 'owner', and thus WBM will forward it to FW/SW 275 276 277 <enum 0 Put_in_idle_list> Put the buffer or descriptor back 278 in the idle list. In case of MSDU or MDPU link descriptor, 279 BM does not need to check to release any individual MSDU 280 buffers 281 282 <enum 1 release_msdu_list > This BM action can only be used 283 in combination with buffer_or_desc_type being msdu_link_descriptor. 284 Field first_msdu_index points out which MSDU pointer in 285 the MSDU link descriptor is the first of an MPDU that is 286 released. 287 BM shall release all the MSDU buffers linked to this first 288 MSDU buffer pointer. All related MSDU buffer pointer entries 289 shall be set to value 0, which represents the 'NULL" pointer. 290 When all MSDU buffer pointers in the MSDU link descriptor 291 are 'NULL', the MSDU link descriptor itself shall also 292 be released. 293 294 <enum 2 Put_in_idle_list_expanded> CURRENTLY NOT IMPLEMENTED.... 295 296 Put the buffer or descriptor back in the idle list. Only 297 valid in combination with buffer_or_desc_type indicating 298 MDPU_link_descriptor. 299 BM shall release the MPDU link descriptor as well as all 300 MSDUs that are linked to the MPDUs in this descriptor. 301 302 303 <legal 0-2> 304 */ 305 306 #define WBM_RELEASE_RING_TX_BM_ACTION_OFFSET 0x00000008 307 #define WBM_RELEASE_RING_TX_BM_ACTION_LSB 3 308 #define WBM_RELEASE_RING_TX_BM_ACTION_MSB 5 309 #define WBM_RELEASE_RING_TX_BM_ACTION_MASK 0x00000038 310 311 312 /* Description BUFFER_OR_DESC_TYPE 313 314 Consumer: WBM/SW/FW 315 Producer: SW/TQM/RXDMA/REO/SWITCH 316 317 Field only valid when WBM is marked as the return_buffer_manager 318 in the Released_Buffer_address_info 319 320 Indicates that type of buffer or descriptor is being released 321 322 323 <enum 0 MSDU_rel_buffer> The address points to an MSDU buffer 324 325 <enum 1 msdu_link_descriptor> The address points to an TX 326 MSDU link descriptor 327 <enum 2 mpdu_link_descriptor> The address points to an MPDU 328 link descriptor 329 <enum 3 msdu_ext_descriptor > The address points to an MSDU 330 extension descriptor. 331 In case BM finds this one in a release ring, it passes it 332 on to FW... 333 <enum 4 queue_ext_descriptor> The address points to an TQM 334 queue extension descriptor. WBM should treat this is the 335 same way as a link descriptor. That is, put the 128 byte 336 buffer back in the link buffer idle list. 337 338 <legal 0-4> 339 */ 340 341 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 342 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 343 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 344 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 345 346 347 /* Description FIRST_MSDU_INDEX 348 349 Consumer: WBM/SW/FW 350 Producer: SW/TQM/RXDMA/REO/SWITCH 351 352 Field only valid for the bm_action release_msdu_list. 353 354 The index of the first MSDU in an MSDU link descriptor all 355 belonging to the same MPDU. 356 357 <legal 0-6> 358 */ 359 360 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_OFFSET 0x00000008 361 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_LSB 9 362 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MSB 12 363 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MASK 0x00001e00 364 365 366 /* Description TQM_RELEASE_REASON 367 368 Consumer: WBM/SW/FW 369 Producer: TQM 370 371 Field only valid when Release_source_module is set to release_source_TQM 372 373 374 (rr = Release Reason) 375 <enum 0 tqm_rr_frame_acked> frame is removed because an 376 ACK of BA for it was received 377 <enum 1 tqm_rr_rem_cmd_rem> frame is removed because a remove 378 command of type "Remove_mpdus" initiated by SW 379 <enum 2 tqm_rr_rem_cmd_tx> frame is removed because a remove 380 command of type "Remove_transmitted_mpdus" initiated by 381 SW 382 <enum 3 tqm_rr_rem_cmd_notx> frame is removed because a 383 remove command of type "Remove_untransmitted_mpdus" initiated 384 by SW 385 <enum 4 tqm_rr_rem_cmd_aged> frame is removed because a 386 remove command of type "Remove_aged_mpdus" or "Remove_aged_msdus" 387 initiated by SW 388 <enum 5 tqm_fw_reason1> frame is removed because a remove 389 command where fw indicated that remove reason is fw_reason1 390 391 <enum 6 tqm_fw_reason2> frame is removed because a remove 392 command where fw indicated that remove reason is fw_reason1 393 394 <enum 7 tqm_fw_reason3> frame is removed because a remove 395 command where fw indicated that remove reason is fw_reason1 396 397 <enum 8 tqm_rr_rem_cmd_disable_queue> frame is removed because 398 a remove command of type "remove_mpdus_and_disable_queue" 399 or "remove_msdus_and_disable_flow" initiated by SW 400 <enum 9 tqm_rr_rem_cmd_till_nonmatching> frame is removed 401 because remove command of type "remove_till_nonmatching_mpdu" 402 initiated by SW 403 <enum 10 tqm_rr_drop_threshold> frame is dropped at TQM 404 entrance due to one of slow/medium/hard drop threshold criteria 405 406 <enum 11 tqm_rr_link_desc_unavailable> frame is dropped 407 at TQM entrance due to the WBM2TQM_LINK_RING having fewer 408 descriptors than a threshold programmed in TQM 409 <enum 12 tqm_rr_drop_or_invalid_msdu> frame is dropped at 410 TQM entrance due to 'TQM_Drop_frame' being set or "null" 411 MSDU flow pointer or MSDU flow pointer 'Flow_valid' being 412 zero or MSDU length being zero 413 <enum 13 tqm_rr_multicast_drop> frame is dropped at TQM 414 entrance due to 'TQM_Drop_frame' being set with 'TCL_drop_reason' 415 set to TCL_multicast_drop_for_vdev. 416 <enum 14 tqm_rr_vdev_mismatch_drop> frame is dropped at 417 TQM entrance due to 'TQM_Drop_frame' being set with 'TCL_drop_reason' 418 set to TCL_vdev_id_mismatch_drop. 419 Waikiki v1 and Hamilton v2 used value 12 for this. 420 421 <legal 0-14> 422 */ 423 424 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 425 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_LSB 13 426 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MSB 16 427 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 428 429 430 /* Description RBM_OVERRIDE_VALID 431 432 This is set to 0 for Tx cases not involving reinjection, 433 and set to 1 for TQM release cases requiring FW reinjection 434 (HastingsPrime FR54309). 435 436 When set to 1, WBM releases the MSDU buffers to FW and overrides 437 the tx_rate_stats field with words 2 and 3 of the 'TX_MSDU_DETAILS' 438 structure, for FW reinjection of these MSDUs (HastingsPrime 439 FR54309). 440 441 <legal 0-1> 442 */ 443 444 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 445 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_LSB 17 446 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MSB 17 447 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 448 449 450 /* Description RBM_OVERRIDE 451 452 Field only valid when rbm_override_valid = 1 453 454 WBM releases the MSDU buffers to FW and overrides the tx_rate_stats 455 field with words 2 and 3 of the 'TX_MSDU_DETAILS' structure, 456 for FW reinjection of these MSDUs (HastingsPrime FR54309). 457 458 459 In Beryllium, rbm_override gives the 'return_buffer_manager' 460 and whence the WBM output ring corresponding to the FW reinjection 461 path. 462 */ 463 464 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_OFFSET 0x00000008 465 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_LSB 18 466 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MSB 21 467 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MASK 0x003c0000 468 469 470 /* Description RESERVED_2A 471 472 <legal 0> 473 */ 474 475 #define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET 0x00000008 476 #define WBM_RELEASE_RING_TX_RESERVED_2A_LSB 22 477 #define WBM_RELEASE_RING_TX_RESERVED_2A_MSB 28 478 #define WBM_RELEASE_RING_TX_RESERVED_2A_MASK 0x1fc00000 479 480 481 /* Description CACHE_ID 482 483 To improve WBM performance, out-of-order completions may 484 be allowed to process multiple MPDUs in parallel. 485 486 The MSDUs released from each cache would be in order so 'First_msdu' 487 and this field together can be used by SW to reorder the 488 completions back to the original order by keeping all MSDUs 489 of an MPDU from one cache together before switching to 490 the next MPDU (from either cache). 491 <legal all> 492 */ 493 494 #define WBM_RELEASE_RING_TX_CACHE_ID_OFFSET 0x00000008 495 #define WBM_RELEASE_RING_TX_CACHE_ID_LSB 29 496 #define WBM_RELEASE_RING_TX_CACHE_ID_MSB 29 497 #define WBM_RELEASE_RING_TX_CACHE_ID_MASK 0x20000000 498 499 500 /* Description COOKIE_CONVERSION_STATUS 501 502 0: 'Sw_buffer_cookie' not converted to 'Buffer_virt_addr' 503 504 1: 'Sw_buffer_cookie' coverted to 'Buffer_virt_addr' 505 <legal 0> 506 */ 507 508 #define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 509 #define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 510 #define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 511 #define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 512 513 514 /* Description WBM_INTERNAL_ERROR 515 516 Can only be set by WBM. 517 518 Is set when WBM got a buffer pointer but the action was 519 to push it to the idle link descriptor ring or do link related 520 activity 521 OR 522 Is set when WBM got a link buffer pointer but the action 523 was to push it to the buffer descriptor ring 524 525 <legal all> 526 */ 527 528 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 529 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_LSB 31 530 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MSB 31 531 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 532 533 534 /* Description TQM_STATUS_NUMBER 535 536 Field only valid when Release_source_module is set to release_source_TQM 537 538 539 The value in this field is equal to value of the 'TQM_CMD_Number' 540 field from the TQM command or the 'TQM_add_cmd_Number' field 541 from the TQM entrance ring descriptor LSB 24-bits. 542 543 This field helps to correlate the statuses with the TQM 544 commands. 545 546 NOTE that SW could program this number to be equal to the 547 PPDU_ID number in case direct correlation with the PPDU 548 ID is desired 549 550 <legal all> 551 */ 552 553 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c 554 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB 0 555 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB 23 556 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff 557 558 559 /* Description TRANSMIT_COUNT 560 561 Field only valid when Release_source_module is set to release_source_TQM 562 563 564 The number of times this frame has been transmitted 565 */ 566 567 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c 568 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_LSB 24 569 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MSB 30 570 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 571 572 573 /* Description SW_RELEASE_DETAILS_VALID 574 575 Consumer: SW 576 Producer: WBM 577 578 When set, some WBM specific release info for SW is valid. 579 580 This is set when WMB got a 'release_msdu_list' command from 581 TQM and the return buffer manager is not WMB. WBM will 582 then de-aggregate all the MSDUs and pass them one at a time 583 on to the 'buffer owner' 584 585 <legal all> 586 */ 587 588 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c 589 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 590 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 591 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 592 593 594 /* Description ACK_FRAME_RSSI 595 596 This field is only valid when the source is TQM. 597 598 If this frame is removed as the result of the reception 599 of an ACK or BA, this field indicates the RSSI of the received 600 ACK or BA frame. 601 602 When the frame is removed as result of a direct remove command 603 from the SW, this field is set to 0x0 (which is never 604 a valid value when real RSSI is available) 605 606 <legal all> 607 */ 608 609 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 610 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_LSB 0 611 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MSB 7 612 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff 613 614 615 /* Description FIRST_MSDU 616 617 Field only valid when SW_release_details_valid is set. 618 619 Consumer: SW 620 Producer: WBM 621 622 When set, this MSDU is the first MSDU pointed to in the 'release_msdu_list' 623 command. 624 625 First_msdu ≠ last_msdu indicates the MSDU was part of 626 an A-MSDU. 627 <legal all> 628 */ 629 630 #define WBM_RELEASE_RING_TX_FIRST_MSDU_OFFSET 0x00000010 631 #define WBM_RELEASE_RING_TX_FIRST_MSDU_LSB 8 632 #define WBM_RELEASE_RING_TX_FIRST_MSDU_MSB 8 633 #define WBM_RELEASE_RING_TX_FIRST_MSDU_MASK 0x00000100 634 635 636 /* Description LAST_MSDU 637 638 Field only valid when SW_release_details_valid is set. 639 640 Consumer: SW 641 Producer: WBM 642 643 When set, this MSDU is the last MSDU pointed to in the 'release_msdu_list' 644 command. 645 646 First_msdu ≠ last_msdu indicates the MSDU was part of 647 an A-MSDU. 648 <legal all> 649 */ 650 651 #define WBM_RELEASE_RING_TX_LAST_MSDU_OFFSET 0x00000010 652 #define WBM_RELEASE_RING_TX_LAST_MSDU_LSB 9 653 #define WBM_RELEASE_RING_TX_LAST_MSDU_MSB 9 654 #define WBM_RELEASE_RING_TX_LAST_MSDU_MASK 0x00000200 655 656 657 /* Description FW_TX_NOTIFY_FRAME 658 659 Field only valid when SW_release_details_valid is set. 660 661 Consumer: SW 662 Producer: WBM 663 664 This is the FW_tx_notify_frame field from the TX_MSDU_DETAILS 665 for this frame from the MSDU link descriptor 666 <legal all> 667 */ 668 669 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 670 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 671 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 672 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 673 674 675 /* Description BUFFER_TIMESTAMP 676 677 Field only valid when SW_release_details_valid is set. 678 679 Consumer: SW 680 Producer: WBM 681 682 This is the Buffer_timestamp field from the TX_MSDU_DETAILS 683 for this frame from the MSDU link descriptor. 684 685 Timestamp in units determined by the UMCMN 'TX_TIMESTAMP_RESOLUTION_SELECT' 686 register 687 688 Waikiki v1 and Hamilton used units of 1024 µs. 689 <legal all> 690 */ 691 692 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 693 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_LSB 13 694 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MSB 31 695 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 696 697 698 /* Description TX_RATE_STATS 699 700 Consumer: TQM/SW 701 Producer: SW/SCH(from TXPCU, PDG) /WBM (from RXDMA) 702 703 Details for command execution tracking purposes. 704 */ 705 706 707 /* Description TX_RATE_STATS_INFO_VALID 708 709 When set all other fields in this STRUCT contain valid info. 710 711 712 When clear, none of the other fields contain valid info. 713 714 <legal all> 715 */ 716 717 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 718 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 719 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 720 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 721 722 723 /* Description TRANSMIT_BW 724 725 Field only valid when Tx_rate_stats_info_valid is set 726 727 Indicates the BW of the upcoming transmission that shall 728 likely start in about 3 -4 us on the medium 729 730 <enum 0 20_mhz>20 Mhz BW 731 <enum 1 40_mhz>40 Mhz BW 732 <enum 2 80_mhz>80 Mhz BW 733 <enum 3 160_mhz>160 Mhz BW 734 <enum 4 320_mhz>320 Mhz BW 735 <enum 5 240_mhz>240 Mhz BW 736 */ 737 738 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 739 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 740 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 741 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e 742 743 744 /* Description TRANSMIT_PKT_TYPE 745 746 Field only valid when Tx_rate_stats_info_valid is set 747 748 Field filled in by PDG. 749 Not valid when in SW transmit mode 750 751 The packet type 752 <enum 0 dot11a>802.11a PPDU type 753 <enum 1 dot11b>802.11b PPDU type 754 <enum 2 dot11n_mm>802.11n Mixed Mode PPDU type 755 <enum 3 dot11ac>802.11ac PPDU type 756 <enum 4 dot11ax>802.11ax PPDU type 757 <enum 5 dot11ba>802.11ba (WUR) PPDU type 758 <enum 6 dot11be>802.11be PPDU type 759 <enum 7 dot11az>802.11az (ranging) PPDU type 760 <enum 8 dot11n_gf>802.11n Green Field PPDU type (unsupported 761 & aborted) 762 */ 763 764 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 765 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 766 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 767 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 768 769 770 /* Description TRANSMIT_STBC 771 772 Field only valid when Tx_rate_stats_info_valid is set 773 774 Field filled in by PDG. 775 Not valid when in SW transmit mode 776 777 When set, STBC transmission rate was used. 778 */ 779 780 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 781 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 782 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 783 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 784 785 786 /* Description TRANSMIT_LDPC 787 788 Field only valid when Tx_rate_stats_info_valid is set 789 790 Field filled in by PDG. 791 Not valid when in SW transmit mode 792 793 When set, use LDPC transmission rates 794 */ 795 796 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 797 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 798 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 799 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 800 801 802 /* Description TRANSMIT_SGI 803 804 Field only valid when Tx_rate_stats_info_valid is set 805 806 Field filled in by PDG. 807 Not valid when in SW transmit mode 808 809 Specify the right GI for HE-Ranging NDPs (11az)/Short NDP. 810 811 812 <enum 0 0_8_us_sgi > Legacy normal GI. Can also be used 813 for HE 814 <enum 1 0_4_us_sgi > Legacy short GI. Can also be used 815 for HE 816 <enum 2 1_6_us_sgi > HE related GI 817 <enum 3 3_2_us_sgi > HE related GI 818 <legal 0 - 3> 819 */ 820 821 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 822 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 823 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 824 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 825 826 827 /* Description TRANSMIT_MCS 828 829 Field only valid when Tx_rate_stats_info_valid is set 830 831 Field filled in by PDG. 832 Not valid when in SW transmit mode 833 834 For details, refer to MCS_TYPE description 835 <legal all> 836 */ 837 838 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 839 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 840 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 841 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 842 843 844 /* Description OFDMA_TRANSMISSION 845 846 Field only valid when Tx_rate_stats_info_valid is set 847 848 Field filled in by PDG. 849 850 Set when the transmission was an OFDMA transmission (DL 851 or UL). 852 <legal all> 853 */ 854 855 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 856 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 857 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 858 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 859 860 861 /* Description TONES_IN_RU 862 863 Field only valid when Tx_rate_stats_info_valid is set 864 865 Field filled in by PDG. 866 Not valid when in SW transmit mode 867 868 The number of tones in the RU used. 869 <legal all> 870 */ 871 872 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 873 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 874 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 875 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 876 877 878 /* Description RESERVED_0A 879 880 <legal 0> 881 */ 882 883 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014 884 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_LSB 29 885 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_MSB 31 886 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_MASK 0xe0000000 887 888 889 /* Description PPDU_TRANSMISSION_TSF 890 891 Field only valid when Tx_rate_stats_info_valid is set 892 893 Based on a HWSCH configuration register setting, this field 894 either contains: 895 896 Lower 32 bits of the TSF, snapshot of this value when transmission 897 of the PPDU containing the frame finished. 898 OR 899 Lower 32 bits of the TSF, snapshot of this value when transmission 900 of the PPDU containing the frame started 901 902 <legal all> 903 */ 904 905 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 906 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 907 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 908 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff 909 910 911 /* Description SW_PEER_ID 912 913 Field only valid when Release_source_module is set to release_source_TQM 914 915 916 1) Release of msdu buffer due to drop_frame = 1. Flow is 917 not fetched and hence sw_peer_id and tid = 0 918 buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason 919 = e_num 1 tqm_rr_rem_cmd_rem 920 921 922 2) Release of msdu buffer due to Flow is not fetched and 923 hence sw_peer_id and tid = 0 924 buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason 925 = e_num 1 tqm_rr_rem_cmd_rem 926 927 928 3) Release of msdu link due to remove_mpdu or acked_mpdu 929 command. 930 buffer_or_desc_type = e_num1 msdu_link_descriptortqm_release_reason 931 can be:e_num 1 tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx 932 933 e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged (this 934 e_num is used for REMOVE_MPDU as well as REMOVE_MSDU). 935 936 Sw_peer_id from the TX_MSDU_FLOW descriptor or TX_MPDU_QUEUE 937 descriptor 938 <legal all> 939 */ 940 941 #define WBM_RELEASE_RING_TX_SW_PEER_ID_OFFSET 0x0000001c 942 #define WBM_RELEASE_RING_TX_SW_PEER_ID_LSB 0 943 #define WBM_RELEASE_RING_TX_SW_PEER_ID_MSB 15 944 #define WBM_RELEASE_RING_TX_SW_PEER_ID_MASK 0x0000ffff 945 946 947 /* Description TID 948 949 Field only valid when Release_source_module is set to release_source_TQM 950 951 952 1) Release of msdu buffer due to drop_frame = 1. Flow is 953 not fetched and hence sw_peer_id and tid = 0 954 buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason 955 = e_num 1 tqm_rr_rem_cmd_rem 956 957 958 2) Release of msdu buffer due to Flow is not fetched and 959 hence sw_peer_id and tid = 0 960 buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason 961 = e_num 1 tqm_rr_rem_cmd_rem 962 963 964 3) Release of msdu link due to remove_mpdu or acked_mpdu 965 command. 966 buffer_or_desc_type = e_num1 msdu_link_descriptortqm_release_reason 967 can be:e_num 1 tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx 968 969 e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged (this 970 e_num is used for REMOVE_MPDU as well as REMOVE_MSDU). 971 972 973 This field represents the TID from the TX_MSDU_FLOW descriptor 974 or TX_MPDU_QUEUE descriptor 975 976 <legal all> 977 */ 978 979 #define WBM_RELEASE_RING_TX_TID_OFFSET 0x0000001c 980 #define WBM_RELEASE_RING_TX_TID_LSB 16 981 #define WBM_RELEASE_RING_TX_TID_MSB 19 982 #define WBM_RELEASE_RING_TX_TID_MASK 0x000f0000 983 984 985 /* Description TQM_STATUS_NUMBER_31_24 986 987 Field only valid when Release_source_module is set to release_source_TQM 988 989 990 The value in this field is equal to value of the 'TQM_CMD_Number' 991 field from the TQM command or the 'TQM_add_cmd_Number' field 992 from the TQM entrance ring descriptor MSB 8-bits. 993 994 This field helps to correlate the statuses with the TQM 995 commands. 996 997 <legal all> 998 */ 999 1000 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_OFFSET 0x0000001c 1001 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_LSB 20 1002 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MSB 27 1003 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MASK 0x0ff00000 1004 1005 1006 /* Description LOOPING_COUNT 1007 1008 Consumer: WBM/SW/FW 1009 Producer: SW/TQM/RXDMA/REO/SWITCH 1010 1011 If WBM_internal_error is set, this descriptor is sent to 1012 the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count 1013 is used to indicate an error code. 1014 1015 The values reported are documented further in the WBM MLD 1016 doc. 1017 1018 If WBM_internal_error is not set, the following holds. 1019 1020 A count value that indicates the number of times the producer 1021 of entries into the Buffer Manager Ring has looped around 1022 the ring. 1023 At initialization time, this value is set to 0. On the first 1024 loop, this value is set to 1. After the max value is reached 1025 allowed by the number of bits for this field, the count 1026 value continues with 0 again. 1027 1028 In case SW is the consumer of the ring entries, it can use 1029 this field to figure out up to where the producer of entries 1030 has created new entries. This eliminates the need to check 1031 where the "head pointer' of the ring is located once the 1032 SW starts processing an interrupt indicating that new entries 1033 have been put into this ring... 1034 1035 Also note that SW if it wants only needs to look at the 1036 LSB bit of this count value. 1037 <legal all> 1038 */ 1039 1040 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c 1041 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_LSB 28 1042 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_MSB 31 1043 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_MASK 0xf0000000 1044 1045 1046 1047 #endif // WBM_RELEASE_RING_TX 1048