1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _BUFFER_ADDR_INFO_H_ 20 #define _BUFFER_ADDR_INFO_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 25 26 27 struct buffer_addr_info { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t buffer_addr_31_0 : 32; 30 uint32_t buffer_addr_39_32 : 8, 31 return_buffer_manager : 4, 32 sw_buffer_cookie : 20; 33 #else 34 uint32_t buffer_addr_31_0 : 32; 35 uint32_t sw_buffer_cookie : 20, 36 return_buffer_manager : 4, 37 buffer_addr_39_32 : 8; 38 #endif 39 }; 40 41 42 43 44 #define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 45 #define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 46 #define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 47 #define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 48 49 50 51 52 #define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 53 #define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 54 #define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 55 #define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 56 57 58 59 60 #define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 61 #define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 62 #define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 63 #define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 64 65 66 67 68 #define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 69 #define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 70 #define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 71 #define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 72 73 74 75 #endif 76