1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _COEX_RX_STATUS_H_ 20 #define _COEX_RX_STATUS_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_COEX_RX_STATUS 2 25 26 #define NUM_OF_QWORDS_COEX_RX_STATUS 1 27 28 29 struct coex_rx_status { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t rx_mac_frame_status : 2, 32 rx_with_tx_response : 1, 33 rx_rate : 5, 34 rx_bw : 3, 35 single_mpdu : 1, 36 filter_status : 1, 37 ampdu : 1, 38 directed : 1, 39 reserved_0 : 1, 40 rx_nss : 3, 41 rx_rssi : 8, 42 rx_type : 3, 43 retry_bit_setting : 1, 44 more_data_bit_setting : 1; 45 uint32_t remain_rx_packet_time : 16, 46 rx_remaining_fes_time : 16; 47 #else 48 uint32_t more_data_bit_setting : 1, 49 retry_bit_setting : 1, 50 rx_type : 3, 51 rx_rssi : 8, 52 rx_nss : 3, 53 reserved_0 : 1, 54 directed : 1, 55 ampdu : 1, 56 filter_status : 1, 57 single_mpdu : 1, 58 rx_bw : 3, 59 rx_rate : 5, 60 rx_with_tx_response : 1, 61 rx_mac_frame_status : 2; 62 uint32_t rx_remaining_fes_time : 16, 63 remain_rx_packet_time : 16; 64 #endif 65 }; 66 67 68 69 70 #define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x0000000000000000 71 #define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0 72 #define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1 73 #define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x0000000000000003 74 75 76 77 78 #define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x0000000000000000 79 #define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2 80 #define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2 81 #define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x0000000000000004 82 83 84 85 86 #define COEX_RX_STATUS_RX_RATE_OFFSET 0x0000000000000000 87 #define COEX_RX_STATUS_RX_RATE_LSB 3 88 #define COEX_RX_STATUS_RX_RATE_MSB 7 89 #define COEX_RX_STATUS_RX_RATE_MASK 0x00000000000000f8 90 91 92 93 94 #define COEX_RX_STATUS_RX_BW_OFFSET 0x0000000000000000 95 #define COEX_RX_STATUS_RX_BW_LSB 8 96 #define COEX_RX_STATUS_RX_BW_MSB 10 97 #define COEX_RX_STATUS_RX_BW_MASK 0x0000000000000700 98 99 100 101 102 #define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x0000000000000000 103 #define COEX_RX_STATUS_SINGLE_MPDU_LSB 11 104 #define COEX_RX_STATUS_SINGLE_MPDU_MSB 11 105 #define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x0000000000000800 106 107 108 109 110 #define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x0000000000000000 111 #define COEX_RX_STATUS_FILTER_STATUS_LSB 12 112 #define COEX_RX_STATUS_FILTER_STATUS_MSB 12 113 #define COEX_RX_STATUS_FILTER_STATUS_MASK 0x0000000000001000 114 115 116 117 118 #define COEX_RX_STATUS_AMPDU_OFFSET 0x0000000000000000 119 #define COEX_RX_STATUS_AMPDU_LSB 13 120 #define COEX_RX_STATUS_AMPDU_MSB 13 121 #define COEX_RX_STATUS_AMPDU_MASK 0x0000000000002000 122 123 124 125 126 #define COEX_RX_STATUS_DIRECTED_OFFSET 0x0000000000000000 127 #define COEX_RX_STATUS_DIRECTED_LSB 14 128 #define COEX_RX_STATUS_DIRECTED_MSB 14 129 #define COEX_RX_STATUS_DIRECTED_MASK 0x0000000000004000 130 131 132 133 134 #define COEX_RX_STATUS_RESERVED_0_OFFSET 0x0000000000000000 135 #define COEX_RX_STATUS_RESERVED_0_LSB 15 136 #define COEX_RX_STATUS_RESERVED_0_MSB 15 137 #define COEX_RX_STATUS_RESERVED_0_MASK 0x0000000000008000 138 139 140 141 142 #define COEX_RX_STATUS_RX_NSS_OFFSET 0x0000000000000000 143 #define COEX_RX_STATUS_RX_NSS_LSB 16 144 #define COEX_RX_STATUS_RX_NSS_MSB 18 145 #define COEX_RX_STATUS_RX_NSS_MASK 0x0000000000070000 146 147 148 149 150 #define COEX_RX_STATUS_RX_RSSI_OFFSET 0x0000000000000000 151 #define COEX_RX_STATUS_RX_RSSI_LSB 19 152 #define COEX_RX_STATUS_RX_RSSI_MSB 26 153 #define COEX_RX_STATUS_RX_RSSI_MASK 0x0000000007f80000 154 155 156 157 158 #define COEX_RX_STATUS_RX_TYPE_OFFSET 0x0000000000000000 159 #define COEX_RX_STATUS_RX_TYPE_LSB 27 160 #define COEX_RX_STATUS_RX_TYPE_MSB 29 161 #define COEX_RX_STATUS_RX_TYPE_MASK 0x0000000038000000 162 163 164 165 166 #define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x0000000000000000 167 #define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30 168 #define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30 169 #define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x0000000040000000 170 171 172 173 174 #define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x0000000000000000 175 #define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31 176 #define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31 177 #define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x0000000080000000 178 179 180 181 182 #define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x0000000000000000 183 #define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 32 184 #define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 47 185 #define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff00000000 186 187 188 189 190 #define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x0000000000000000 191 #define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 48 192 #define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 63 193 #define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff000000000000 194 195 196 197 #endif 198