1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _COEX_TX_REQ_H_ 20 #define _COEX_TX_REQ_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_COEX_TX_REQ 4 25 26 #define NUM_OF_QWORDS_COEX_TX_REQ 2 27 28 29 struct coex_tx_req { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t tx_pwr : 8, 32 min_tx_pwr : 8, 33 nss : 3, 34 tx_chain_mask : 8, 35 bw : 3, 36 reserved_0 : 2; 37 uint32_t alt_tx_pwr : 8, 38 alt_min_tx_pwr : 8, 39 alt_nss : 3, 40 alt_tx_chain_mask : 8, 41 alt_bw : 3, 42 reserved_1 : 2; 43 uint32_t tx_pwr_1 : 8, 44 alt_tx_pwr_1 : 8, 45 wlan_request_duration : 16; 46 uint32_t wlan_pkt_type : 4, 47 coex_tx_reason : 2, 48 response_frame_type : 5, 49 wlan_low_priority_slicing_allowed : 1, 50 wlan_high_priority_slicing_allowed : 1, 51 sch_tx_burst_ongoing : 1, 52 coex_tx_priority : 4, 53 reserved_3a : 14; 54 #else 55 uint32_t reserved_0 : 2, 56 bw : 3, 57 tx_chain_mask : 8, 58 nss : 3, 59 min_tx_pwr : 8, 60 tx_pwr : 8; 61 uint32_t reserved_1 : 2, 62 alt_bw : 3, 63 alt_tx_chain_mask : 8, 64 alt_nss : 3, 65 alt_min_tx_pwr : 8, 66 alt_tx_pwr : 8; 67 uint32_t wlan_request_duration : 16, 68 alt_tx_pwr_1 : 8, 69 tx_pwr_1 : 8; 70 uint32_t reserved_3a : 14, 71 coex_tx_priority : 4, 72 sch_tx_burst_ongoing : 1, 73 wlan_high_priority_slicing_allowed : 1, 74 wlan_low_priority_slicing_allowed : 1, 75 response_frame_type : 5, 76 coex_tx_reason : 2, 77 wlan_pkt_type : 4; 78 #endif 79 }; 80 81 82 83 84 #define COEX_TX_REQ_TX_PWR_OFFSET 0x0000000000000000 85 #define COEX_TX_REQ_TX_PWR_LSB 0 86 #define COEX_TX_REQ_TX_PWR_MSB 7 87 #define COEX_TX_REQ_TX_PWR_MASK 0x00000000000000ff 88 89 90 91 92 #define COEX_TX_REQ_MIN_TX_PWR_OFFSET 0x0000000000000000 93 #define COEX_TX_REQ_MIN_TX_PWR_LSB 8 94 #define COEX_TX_REQ_MIN_TX_PWR_MSB 15 95 #define COEX_TX_REQ_MIN_TX_PWR_MASK 0x000000000000ff00 96 97 98 99 100 #define COEX_TX_REQ_NSS_OFFSET 0x0000000000000000 101 #define COEX_TX_REQ_NSS_LSB 16 102 #define COEX_TX_REQ_NSS_MSB 18 103 #define COEX_TX_REQ_NSS_MASK 0x0000000000070000 104 105 106 107 108 #define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET 0x0000000000000000 109 #define COEX_TX_REQ_TX_CHAIN_MASK_LSB 19 110 #define COEX_TX_REQ_TX_CHAIN_MASK_MSB 26 111 #define COEX_TX_REQ_TX_CHAIN_MASK_MASK 0x0000000007f80000 112 113 114 115 116 #define COEX_TX_REQ_BW_OFFSET 0x0000000000000000 117 #define COEX_TX_REQ_BW_LSB 27 118 #define COEX_TX_REQ_BW_MSB 29 119 #define COEX_TX_REQ_BW_MASK 0x0000000038000000 120 121 122 123 124 #define COEX_TX_REQ_RESERVED_0_OFFSET 0x0000000000000000 125 #define COEX_TX_REQ_RESERVED_0_LSB 30 126 #define COEX_TX_REQ_RESERVED_0_MSB 31 127 #define COEX_TX_REQ_RESERVED_0_MASK 0x00000000c0000000 128 129 130 131 132 #define COEX_TX_REQ_ALT_TX_PWR_OFFSET 0x0000000000000000 133 #define COEX_TX_REQ_ALT_TX_PWR_LSB 32 134 #define COEX_TX_REQ_ALT_TX_PWR_MSB 39 135 #define COEX_TX_REQ_ALT_TX_PWR_MASK 0x000000ff00000000 136 137 138 139 140 #define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 141 #define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB 40 142 #define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB 47 143 #define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 144 145 146 147 148 #define COEX_TX_REQ_ALT_NSS_OFFSET 0x0000000000000000 149 #define COEX_TX_REQ_ALT_NSS_LSB 48 150 #define COEX_TX_REQ_ALT_NSS_MSB 50 151 #define COEX_TX_REQ_ALT_NSS_MASK 0x0007000000000000 152 153 154 155 156 #define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 157 #define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB 51 158 #define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB 58 159 #define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 160 161 162 163 164 #define COEX_TX_REQ_ALT_BW_OFFSET 0x0000000000000000 165 #define COEX_TX_REQ_ALT_BW_LSB 59 166 #define COEX_TX_REQ_ALT_BW_MSB 61 167 #define COEX_TX_REQ_ALT_BW_MASK 0x3800000000000000 168 169 170 171 172 #define COEX_TX_REQ_RESERVED_1_OFFSET 0x0000000000000000 173 #define COEX_TX_REQ_RESERVED_1_LSB 62 174 #define COEX_TX_REQ_RESERVED_1_MSB 63 175 #define COEX_TX_REQ_RESERVED_1_MASK 0xc000000000000000 176 177 178 179 180 #define COEX_TX_REQ_TX_PWR_1_OFFSET 0x0000000000000008 181 #define COEX_TX_REQ_TX_PWR_1_LSB 0 182 #define COEX_TX_REQ_TX_PWR_1_MSB 7 183 #define COEX_TX_REQ_TX_PWR_1_MASK 0x00000000000000ff 184 185 186 187 188 #define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET 0x0000000000000008 189 #define COEX_TX_REQ_ALT_TX_PWR_1_LSB 8 190 #define COEX_TX_REQ_ALT_TX_PWR_1_MSB 15 191 #define COEX_TX_REQ_ALT_TX_PWR_1_MASK 0x000000000000ff00 192 193 194 195 196 #define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET 0x0000000000000008 197 #define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB 16 198 #define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB 31 199 #define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK 0x00000000ffff0000 200 201 202 203 204 #define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET 0x0000000000000008 205 #define COEX_TX_REQ_WLAN_PKT_TYPE_LSB 32 206 #define COEX_TX_REQ_WLAN_PKT_TYPE_MSB 35 207 #define COEX_TX_REQ_WLAN_PKT_TYPE_MASK 0x0000000f00000000 208 209 210 211 212 #define COEX_TX_REQ_COEX_TX_REASON_OFFSET 0x0000000000000008 213 #define COEX_TX_REQ_COEX_TX_REASON_LSB 36 214 #define COEX_TX_REQ_COEX_TX_REASON_MSB 37 215 #define COEX_TX_REQ_COEX_TX_REASON_MASK 0x0000003000000000 216 217 218 219 220 #define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000008 221 #define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB 38 222 #define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB 42 223 #define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK 0x000007c000000000 224 225 226 227 228 #define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 229 #define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB 43 230 #define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB 43 231 #define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK 0x0000080000000000 232 233 234 235 236 #define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 237 #define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB 44 238 #define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB 44 239 #define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK 0x0000100000000000 240 241 242 243 244 #define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000008 245 #define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB 45 246 #define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB 45 247 #define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK 0x0000200000000000 248 249 250 251 252 #define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET 0x0000000000000008 253 #define COEX_TX_REQ_COEX_TX_PRIORITY_LSB 46 254 #define COEX_TX_REQ_COEX_TX_PRIORITY_MSB 49 255 #define COEX_TX_REQ_COEX_TX_PRIORITY_MASK 0x0003c00000000000 256 257 258 259 260 #define COEX_TX_REQ_RESERVED_3A_OFFSET 0x0000000000000008 261 #define COEX_TX_REQ_RESERVED_3A_LSB 50 262 #define COEX_TX_REQ_RESERVED_3A_MSB 63 263 #define COEX_TX_REQ_RESERVED_3A_MASK 0xfffc000000000000 264 265 266 267 #endif 268