1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _COEX_TX_STATUS_H_ 20 #define _COEX_TX_STATUS_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_COEX_TX_STATUS 4 25 26 #define NUM_OF_QWORDS_COEX_TX_STATUS 2 27 28 29 struct coex_tx_status { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t reserved_0a : 7, 32 tx_bw : 3, 33 tx_status_reason : 3, 34 tx_wait_ack : 1, 35 fes_tx_is_gen_frame : 1, 36 sch_tx_burst_ongoing : 1, 37 current_tx_duration : 16; 38 uint32_t next_rx_active_time : 16, 39 remaining_fes_time : 16; 40 uint32_t tx_antenna_mask : 8, 41 shared_ant_tx_pwr : 8, 42 other_ant_tx_pwr : 8, 43 reserved_2 : 8; 44 uint32_t tlv64_padding : 32; 45 #else 46 uint32_t current_tx_duration : 16, 47 sch_tx_burst_ongoing : 1, 48 fes_tx_is_gen_frame : 1, 49 tx_wait_ack : 1, 50 tx_status_reason : 3, 51 tx_bw : 3, 52 reserved_0a : 7; 53 uint32_t remaining_fes_time : 16, 54 next_rx_active_time : 16; 55 uint32_t reserved_2 : 8, 56 other_ant_tx_pwr : 8, 57 shared_ant_tx_pwr : 8, 58 tx_antenna_mask : 8; 59 uint32_t tlv64_padding : 32; 60 #endif 61 }; 62 63 64 65 66 #define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x0000000000000000 67 #define COEX_TX_STATUS_RESERVED_0A_LSB 0 68 #define COEX_TX_STATUS_RESERVED_0A_MSB 6 69 #define COEX_TX_STATUS_RESERVED_0A_MASK 0x000000000000007f 70 71 72 73 74 #define COEX_TX_STATUS_TX_BW_OFFSET 0x0000000000000000 75 #define COEX_TX_STATUS_TX_BW_LSB 7 76 #define COEX_TX_STATUS_TX_BW_MSB 9 77 #define COEX_TX_STATUS_TX_BW_MASK 0x0000000000000380 78 79 80 81 82 #define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x0000000000000000 83 #define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10 84 #define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12 85 #define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x0000000000001c00 86 87 88 89 90 #define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x0000000000000000 91 #define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13 92 #define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13 93 #define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x0000000000002000 94 95 96 97 98 #define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x0000000000000000 99 #define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14 100 #define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14 101 #define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x0000000000004000 102 103 104 105 106 #define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000000 107 #define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15 108 #define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15 109 #define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x0000000000008000 110 111 112 113 114 #define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x0000000000000000 115 #define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16 116 #define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31 117 #define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0x00000000ffff0000 118 119 120 121 122 #define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x0000000000000000 123 #define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 32 124 #define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 47 125 #define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff00000000 126 127 128 129 130 #define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x0000000000000000 131 #define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 48 132 #define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 63 133 #define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff000000000000 134 135 136 137 138 #define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x0000000000000008 139 #define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0 140 #define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7 141 #define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x00000000000000ff 142 143 144 145 146 #define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x0000000000000008 147 #define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8 148 #define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15 149 #define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x000000000000ff00 150 151 152 153 154 #define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x0000000000000008 155 #define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16 156 #define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23 157 #define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x0000000000ff0000 158 159 160 161 162 #define COEX_TX_STATUS_RESERVED_2_OFFSET 0x0000000000000008 163 #define COEX_TX_STATUS_RESERVED_2_LSB 24 164 #define COEX_TX_STATUS_RESERVED_2_MSB 31 165 #define COEX_TX_STATUS_RESERVED_2_MASK 0x00000000ff000000 166 167 168 169 170 #define COEX_TX_STATUS_TLV64_PADDING_OFFSET 0x0000000000000008 171 #define COEX_TX_STATUS_TLV64_PADDING_LSB 32 172 #define COEX_TX_STATUS_TLV64_PADDING_MSB 63 173 #define COEX_TX_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 174 175 176 177 #endif 178