1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_ 20 #define _EHT_SIG_USR_MU_MIMO_INFO_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2 25 26 27 struct eht_sig_usr_mu_mimo_info { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t sta_id : 11, 30 sta_mcs : 4, 31 sta_coding : 1, 32 sta_spatial_config : 6, 33 reserved_0a : 1, 34 rx_integrity_check_passed : 1, 35 subband80_cc_mask : 8; 36 uint32_t user_order_subband80_0 : 8, 37 user_order_subband80_1 : 8, 38 user_order_subband80_2 : 8, 39 user_order_subband80_3 : 8; 40 #else 41 uint32_t subband80_cc_mask : 8, 42 rx_integrity_check_passed : 1, 43 reserved_0a : 1, 44 sta_spatial_config : 6, 45 sta_coding : 1, 46 sta_mcs : 4, 47 sta_id : 11; 48 uint32_t user_order_subband80_3 : 8, 49 user_order_subband80_2 : 8, 50 user_order_subband80_1 : 8, 51 user_order_subband80_0 : 8; 52 #endif 53 }; 54 55 56 57 58 #define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET 0x00000000 59 #define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB 0 60 #define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB 10 61 #define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK 0x000007ff 62 63 64 65 66 #define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET 0x00000000 67 #define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB 11 68 #define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB 14 69 #define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK 0x00007800 70 71 72 73 74 #define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET 0x00000000 75 #define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB 15 76 #define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB 15 77 #define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK 0x00008000 78 79 80 81 82 #define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 83 #define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB 16 84 #define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB 21 85 #define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK 0x003f0000 86 87 88 89 90 #define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET 0x00000000 91 #define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB 22 92 #define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB 22 93 #define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK 0x00400000 94 95 96 97 98 #define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 99 #define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 100 #define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 101 #define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 102 103 104 105 106 #define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 107 #define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB 24 108 #define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB 31 109 #define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 110 111 112 113 114 #define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 115 #define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB 0 116 #define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB 7 117 #define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff 118 119 120 121 122 #define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 123 #define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB 8 124 #define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB 15 125 #define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 126 127 128 129 130 #define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 131 #define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB 16 132 #define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB 23 133 #define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 134 135 136 137 138 #define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 139 #define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB 24 140 #define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB 31 141 #define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 142 143 144 145 #endif 146