1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _EXPECTED_RESPONSE_H_ 20 #define _EXPECTED_RESPONSE_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_EXPECTED_RESPONSE 6 25 26 #define NUM_OF_QWORDS_EXPECTED_RESPONSE 3 27 28 29 struct expected_response { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t tx_ad2_31_0 : 32; 32 uint32_t tx_ad2_47_32 : 16, 33 expected_response_type : 5, 34 response_to_response : 3, 35 su_ba_user_number : 1, 36 response_info_part2_required : 1, 37 transmitted_bssid_check_en : 1, 38 reserved_1 : 5; 39 uint32_t ndp_sta_partial_aid_2_8_0 : 11, 40 reserved_2 : 10, 41 ndp_sta_partial_aid1_8_0 : 11; 42 uint32_t ast_index : 16, 43 capture_ack_ba_sounding : 1, 44 capture_sounding_1str_20mhz : 1, 45 capture_sounding_1str_40mhz : 1, 46 capture_sounding_1str_80mhz : 1, 47 capture_sounding_1str_160mhz : 1, 48 capture_sounding_1str_240mhz : 1, 49 capture_sounding_1str_320mhz : 1, 50 reserved_3a : 9; 51 uint32_t fcs : 9, 52 reserved_4a : 1, 53 crc : 4, 54 scrambler_seed : 7, 55 reserved_4b : 11; 56 uint32_t tlv64_padding : 32; 57 #else 58 uint32_t tx_ad2_31_0 : 32; 59 uint32_t reserved_1 : 5, 60 transmitted_bssid_check_en : 1, 61 response_info_part2_required : 1, 62 su_ba_user_number : 1, 63 response_to_response : 3, 64 expected_response_type : 5, 65 tx_ad2_47_32 : 16; 66 uint32_t ndp_sta_partial_aid1_8_0 : 11, 67 reserved_2 : 10, 68 ndp_sta_partial_aid_2_8_0 : 11; 69 uint32_t reserved_3a : 9, 70 capture_sounding_1str_320mhz : 1, 71 capture_sounding_1str_240mhz : 1, 72 capture_sounding_1str_160mhz : 1, 73 capture_sounding_1str_80mhz : 1, 74 capture_sounding_1str_40mhz : 1, 75 capture_sounding_1str_20mhz : 1, 76 capture_ack_ba_sounding : 1, 77 ast_index : 16; 78 uint32_t reserved_4b : 11, 79 scrambler_seed : 7, 80 crc : 4, 81 reserved_4a : 1, 82 fcs : 9; 83 uint32_t tlv64_padding : 32; 84 #endif 85 }; 86 87 88 89 90 #define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x0000000000000000 91 #define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0 92 #define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31 93 #define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0x00000000ffffffff 94 95 96 97 98 #define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x0000000000000000 99 #define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 32 100 #define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 47 101 #define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff00000000 102 103 104 105 106 #define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x0000000000000000 107 #define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 48 108 #define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 52 109 #define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f000000000000 110 111 112 113 114 #define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 115 #define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 53 116 #define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 55 117 #define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e0000000000000 118 119 120 121 122 #define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x0000000000000000 123 #define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 56 124 #define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 56 125 #define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x0100000000000000 126 127 128 129 130 #define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 131 #define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 57 132 #define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 57 133 #define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0200000000000000 134 135 136 137 138 #define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 139 #define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 58 140 #define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 58 141 #define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0400000000000000 142 143 144 145 146 #define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x0000000000000000 147 #define EXPECTED_RESPONSE_RESERVED_1_LSB 59 148 #define EXPECTED_RESPONSE_RESERVED_1_MSB 63 149 #define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf800000000000000 150 151 152 153 154 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x0000000000000008 155 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0 156 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10 157 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x00000000000007ff 158 159 160 161 162 #define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x0000000000000008 163 #define EXPECTED_RESPONSE_RESERVED_2_LSB 11 164 #define EXPECTED_RESPONSE_RESERVED_2_MSB 20 165 #define EXPECTED_RESPONSE_RESERVED_2_MASK 0x00000000001ff800 166 167 168 169 170 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x0000000000000008 171 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21 172 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31 173 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0x00000000ffe00000 174 175 176 177 178 #define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000000000008 179 #define EXPECTED_RESPONSE_AST_INDEX_LSB 32 180 #define EXPECTED_RESPONSE_AST_INDEX_MSB 47 181 #define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff00000000 182 183 184 185 186 #define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000000000008 187 #define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 48 188 #define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 48 189 #define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x0001000000000000 190 191 192 193 194 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000000000008 195 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 49 196 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 49 197 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x0002000000000000 198 199 200 201 202 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000000000008 203 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 50 204 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 50 205 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x0004000000000000 206 207 208 209 210 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000000000008 211 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 51 212 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 51 213 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x0008000000000000 214 215 216 217 218 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000000000008 219 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 52 220 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 52 221 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x0010000000000000 222 223 224 225 226 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000000000008 227 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 53 228 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 53 229 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x0020000000000000 230 231 232 233 234 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000000000008 235 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 54 236 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 54 237 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x0040000000000000 238 239 240 241 242 #define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000000000008 243 #define EXPECTED_RESPONSE_RESERVED_3A_LSB 55 244 #define EXPECTED_RESPONSE_RESERVED_3A_MSB 63 245 #define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff80000000000000 246 247 248 249 250 #define EXPECTED_RESPONSE_FCS_OFFSET 0x0000000000000010 251 #define EXPECTED_RESPONSE_FCS_LSB 0 252 #define EXPECTED_RESPONSE_FCS_MSB 8 253 #define EXPECTED_RESPONSE_FCS_MASK 0x00000000000001ff 254 255 256 257 258 #define EXPECTED_RESPONSE_RESERVED_4A_OFFSET 0x0000000000000010 259 #define EXPECTED_RESPONSE_RESERVED_4A_LSB 9 260 #define EXPECTED_RESPONSE_RESERVED_4A_MSB 9 261 #define EXPECTED_RESPONSE_RESERVED_4A_MASK 0x0000000000000200 262 263 264 265 266 #define EXPECTED_RESPONSE_CRC_OFFSET 0x0000000000000010 267 #define EXPECTED_RESPONSE_CRC_LSB 10 268 #define EXPECTED_RESPONSE_CRC_MSB 13 269 #define EXPECTED_RESPONSE_CRC_MASK 0x0000000000003c00 270 271 272 273 274 #define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x0000000000000010 275 #define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14 276 #define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20 277 #define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x00000000001fc000 278 279 280 281 282 #define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x0000000000000010 283 #define EXPECTED_RESPONSE_RESERVED_4B_LSB 21 284 #define EXPECTED_RESPONSE_RESERVED_4B_MSB 31 285 #define EXPECTED_RESPONSE_RESERVED_4B_MASK 0x00000000ffe00000 286 287 288 289 290 #define EXPECTED_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000010 291 #define EXPECTED_RESPONSE_TLV64_PADDING_LSB 32 292 #define EXPECTED_RESPONSE_TLV64_PADDING_MSB 63 293 #define EXPECTED_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000 294 295 296 297 #endif 298