1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _HE_SIG_A_MU_UL_INFO_H_ 20 #define _HE_SIG_A_MU_UL_INFO_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2 25 26 27 struct he_sig_a_mu_ul_info { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t format_indication : 1, 30 bss_color_id : 6, 31 spatial_reuse : 16, 32 reserved_0a : 1, 33 transmit_bw : 2, 34 reserved_0b : 6; 35 uint32_t txop_duration : 7, 36 reserved_1a : 9, 37 crc : 4, 38 tail : 6, 39 reserved_1b : 5, 40 rx_integrity_check_passed : 1; 41 #else 42 uint32_t reserved_0b : 6, 43 transmit_bw : 2, 44 reserved_0a : 1, 45 spatial_reuse : 16, 46 bss_color_id : 6, 47 format_indication : 1; 48 uint32_t rx_integrity_check_passed : 1, 49 reserved_1b : 5, 50 tail : 6, 51 crc : 4, 52 reserved_1a : 9, 53 txop_duration : 7; 54 #endif 55 }; 56 57 58 59 60 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000 61 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0 62 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0 63 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001 64 65 66 67 68 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 69 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1 70 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6 71 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e 72 73 74 75 76 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 77 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7 78 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22 79 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80 80 81 82 83 84 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000 85 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23 86 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23 87 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000 88 89 90 91 92 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000 93 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24 94 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25 95 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000 96 97 98 99 100 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000 101 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26 102 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31 103 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000 104 105 106 107 108 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004 109 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0 110 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6 111 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f 112 113 114 115 116 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004 117 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7 118 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15 119 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80 120 121 122 123 124 #define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004 125 #define HE_SIG_A_MU_UL_INFO_CRC_LSB 16 126 #define HE_SIG_A_MU_UL_INFO_CRC_MSB 19 127 #define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000 128 129 130 131 132 #define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004 133 #define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20 134 #define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25 135 #define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000 136 137 138 139 140 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004 141 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26 142 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30 143 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000 144 145 146 147 148 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 149 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 150 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 151 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 152 153 154 155 #endif 156