1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _HE_SIG_B1_MU_INFO_H_ 20 #define _HE_SIG_B1_MU_INFO_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1 25 26 27 struct he_sig_b1_mu_info { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t ru_allocation : 8, 30 reserved_0 : 23, 31 rx_integrity_check_passed : 1; 32 #else 33 uint32_t rx_integrity_check_passed : 1, 34 reserved_0 : 23, 35 ru_allocation : 8; 36 #endif 37 }; 38 39 40 41 42 #define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET 0x00000000 43 #define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB 0 44 #define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB 7 45 #define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK 0x000000ff 46 47 48 49 50 #define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET 0x00000000 51 #define HE_SIG_B1_MU_INFO_RESERVED_0_LSB 8 52 #define HE_SIG_B1_MU_INFO_RESERVED_0_MSB 30 53 #define HE_SIG_B1_MU_INFO_RESERVED_0_MASK 0x7fffff00 54 55 56 57 58 #define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 59 #define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 60 #define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 61 #define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 62 63 64 65 #endif 66