1*5113495bSYour Name 2*5113495bSYour Name /* 3*5113495bSYour Name * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4*5113495bSYour Name * SPDX-License-Identifier: ISC 5*5113495bSYour Name */ 6*5113495bSYour Name 7*5113495bSYour Name 8*5113495bSYour Name 9*5113495bSYour Name 10*5113495bSYour Name 11*5113495bSYour Name 12*5113495bSYour Name 13*5113495bSYour Name 14*5113495bSYour Name 15*5113495bSYour Name 16*5113495bSYour Name 17*5113495bSYour Name 18*5113495bSYour Name 19*5113495bSYour Name #ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_ 20*5113495bSYour Name #define _MACTX_EHT_SIG_USR_MU_MIMO_H_ 21*5113495bSYour Name #if !defined(__ASSEMBLER__) 22*5113495bSYour Name #endif 23*5113495bSYour Name 24*5113495bSYour Name #include "eht_sig_usr_mu_mimo_info.h" 25*5113495bSYour Name #define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2 26*5113495bSYour Name 27*5113495bSYour Name #define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_MU_MIMO 1 28*5113495bSYour Name 29*5113495bSYour Name 30*5113495bSYour Name struct mactx_eht_sig_usr_mu_mimo { 31*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32*5113495bSYour Name struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; 33*5113495bSYour Name #else 34*5113495bSYour Name struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; 35*5113495bSYour Name #endif 36*5113495bSYour Name }; 37*5113495bSYour Name 38*5113495bSYour Name 39*5113495bSYour Name 40*5113495bSYour Name 41*5113495bSYour Name 42*5113495bSYour Name 43*5113495bSYour Name 44*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 45*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0 46*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10 47*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff 48*5113495bSYour Name 49*5113495bSYour Name 50*5113495bSYour Name 51*5113495bSYour Name 52*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 53*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11 54*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14 55*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 56*5113495bSYour Name 57*5113495bSYour Name 58*5113495bSYour Name 59*5113495bSYour Name 60*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 61*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15 62*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15 63*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x0000000000008000 64*5113495bSYour Name 65*5113495bSYour Name 66*5113495bSYour Name 67*5113495bSYour Name 68*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 69*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16 70*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21 71*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00000000003f0000 72*5113495bSYour Name 73*5113495bSYour Name 74*5113495bSYour Name 75*5113495bSYour Name 76*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 77*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22 78*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22 79*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000400000 80*5113495bSYour Name 81*5113495bSYour Name 82*5113495bSYour Name 83*5113495bSYour Name 84*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 85*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 86*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 87*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 88*5113495bSYour Name 89*5113495bSYour Name 90*5113495bSYour Name 91*5113495bSYour Name 92*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 93*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 94*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 95*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 96*5113495bSYour Name 97*5113495bSYour Name 98*5113495bSYour Name 99*5113495bSYour Name 100*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 101*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 102*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 103*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 104*5113495bSYour Name 105*5113495bSYour Name 106*5113495bSYour Name 107*5113495bSYour Name 108*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 109*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 110*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 111*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 112*5113495bSYour Name 113*5113495bSYour Name 114*5113495bSYour Name 115*5113495bSYour Name 116*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 117*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 118*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 119*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 120*5113495bSYour Name 121*5113495bSYour Name 122*5113495bSYour Name 123*5113495bSYour Name 124*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 125*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 126*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 127*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 128*5113495bSYour Name 129*5113495bSYour Name 130*5113495bSYour Name 131*5113495bSYour Name #endif 132