1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _MACTX_HE_SIG_B1_MU_H_ 20 #define _MACTX_HE_SIG_B1_MU_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "he_sig_b1_mu_info.h" 25 #define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 2 26 27 #define NUM_OF_QWORDS_MACTX_HE_SIG_B1_MU 1 28 29 30 struct mactx_he_sig_b1_mu { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; 33 uint32_t tlv64_padding : 32; 34 #else 35 struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; 36 uint32_t tlv64_padding : 32; 37 #endif 38 }; 39 40 41 42 43 44 45 46 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 47 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 48 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 49 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff 50 51 52 53 54 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 55 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 56 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 57 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 58 59 60 61 62 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 63 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 64 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 65 #define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 66 67 68 69 70 #define MACTX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 71 #define MACTX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 72 #define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 73 #define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 74 75 76 77 #endif 78