xref: /wlan-driver/fw-api/hw/qca5424/mactx_phy_desc.h (revision 5113495b16420b49004c444715d2daae2066e7dc) 
1*5113495bSYour Name 
2*5113495bSYour Name /*
3*5113495bSYour Name  * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4*5113495bSYour Name  * SPDX-License-Identifier: ISC
5*5113495bSYour Name  */
6*5113495bSYour Name 
7*5113495bSYour Name 
8*5113495bSYour Name 
9*5113495bSYour Name 
10*5113495bSYour Name 
11*5113495bSYour Name 
12*5113495bSYour Name 
13*5113495bSYour Name 
14*5113495bSYour Name 
15*5113495bSYour Name 
16*5113495bSYour Name 
17*5113495bSYour Name 
18*5113495bSYour Name 
19*5113495bSYour Name #ifndef _MACTX_PHY_DESC_H_
20*5113495bSYour Name #define _MACTX_PHY_DESC_H_
21*5113495bSYour Name #if !defined(__ASSEMBLER__)
22*5113495bSYour Name #endif
23*5113495bSYour Name 
24*5113495bSYour Name #define NUM_OF_DWORDS_MACTX_PHY_DESC 4
25*5113495bSYour Name 
26*5113495bSYour Name #define NUM_OF_QWORDS_MACTX_PHY_DESC 2
27*5113495bSYour Name 
28*5113495bSYour Name 
29*5113495bSYour Name struct mactx_phy_desc {
30*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
31*5113495bSYour Name              uint32_t reserved_0a                                             : 16,
32*5113495bSYour Name                       bf_type                                                 :  2,
33*5113495bSYour Name                       wait_sifs                                               :  2,
34*5113495bSYour Name                       dot11b_preamble_type                                    :  1,
35*5113495bSYour Name                       pkt_type                                                :  4,
36*5113495bSYour Name                       su_or_mu                                                :  2,
37*5113495bSYour Name                       mu_type                                                 :  1,
38*5113495bSYour Name                       bandwidth                                               :  3,
39*5113495bSYour Name                       channel_capture                                         :  1;
40*5113495bSYour Name              uint32_t mcs                                                     :  4,
41*5113495bSYour Name                       global_ofdma_mimo_enable                                :  1,
42*5113495bSYour Name                       reserved_1a                                             :  1,
43*5113495bSYour Name                       stbc                                                    :  1,
44*5113495bSYour Name                       dot11ax_su_extended                                     :  1,
45*5113495bSYour Name                       dot11ax_trigger_frame_embedded                          :  1,
46*5113495bSYour Name                       tx_pwr_shared                                           :  8,
47*5113495bSYour Name                       tx_pwr_unshared                                         :  8,
48*5113495bSYour Name                       measure_power                                           :  1,
49*5113495bSYour Name                       tpc_glut_self_cal                                       :  1,
50*5113495bSYour Name                       back_to_back_transmission_expected                      :  1,
51*5113495bSYour Name                       heavy_clip_nss                                          :  3,
52*5113495bSYour Name                       txbf_per_packet_no_csd_no_walsh                         :  1;
53*5113495bSYour Name              uint32_t ndp                                                     :  2,
54*5113495bSYour Name                       ul_flag                                                 :  1,
55*5113495bSYour Name                       triggered                                               :  1,
56*5113495bSYour Name                       ap_pkt_bw                                               :  3,
57*5113495bSYour Name                       ru_position_start                                       :  8,
58*5113495bSYour Name                       pcu_ppdu_setup_start_reason                             :  3,
59*5113495bSYour Name                       tlv_source                                              :  1,
60*5113495bSYour Name                       reserved_2a                                             :  2,
61*5113495bSYour Name                       nss                                                     :  3,
62*5113495bSYour Name                       stream_offset                                           :  3,
63*5113495bSYour Name                       reserved_2b                                             :  2,
64*5113495bSYour Name                       clpc_enable                                             :  1,
65*5113495bSYour Name                       mu_ndp                                                  :  1,
66*5113495bSYour Name                       response_expected                                       :  1;
67*5113495bSYour Name              uint32_t rx_chain_mask                                           :  8,
68*5113495bSYour Name                       rx_chain_mask_valid                                     :  1,
69*5113495bSYour Name                       ant_sel_valid                                           :  1,
70*5113495bSYour Name                       ant_sel                                                 :  1,
71*5113495bSYour Name                       cp_setting                                              :  2,
72*5113495bSYour Name                       he_ppdu_subtype                                         :  2,
73*5113495bSYour Name                       active_channel                                          :  3,
74*5113495bSYour Name                       generate_phyrx_tx_start_timing                          :  1,
75*5113495bSYour Name                       ltf_size                                                :  2,
76*5113495bSYour Name                       ru_size_updated_v2                                      :  4,
77*5113495bSYour Name                       reserved_3c                                             :  1,
78*5113495bSYour Name                       u_sig_puncture_pattern_encoding                         :  6;
79*5113495bSYour Name #else
80*5113495bSYour Name              uint32_t channel_capture                                         :  1,
81*5113495bSYour Name                       bandwidth                                               :  3,
82*5113495bSYour Name                       mu_type                                                 :  1,
83*5113495bSYour Name                       su_or_mu                                                :  2,
84*5113495bSYour Name                       pkt_type                                                :  4,
85*5113495bSYour Name                       dot11b_preamble_type                                    :  1,
86*5113495bSYour Name                       wait_sifs                                               :  2,
87*5113495bSYour Name                       bf_type                                                 :  2,
88*5113495bSYour Name                       reserved_0a                                             : 16;
89*5113495bSYour Name              uint32_t txbf_per_packet_no_csd_no_walsh                         :  1,
90*5113495bSYour Name                       heavy_clip_nss                                          :  3,
91*5113495bSYour Name                       back_to_back_transmission_expected                      :  1,
92*5113495bSYour Name                       tpc_glut_self_cal                                       :  1,
93*5113495bSYour Name                       measure_power                                           :  1,
94*5113495bSYour Name                       tx_pwr_unshared                                         :  8,
95*5113495bSYour Name                       tx_pwr_shared                                           :  8,
96*5113495bSYour Name                       dot11ax_trigger_frame_embedded                          :  1,
97*5113495bSYour Name                       dot11ax_su_extended                                     :  1,
98*5113495bSYour Name                       stbc                                                    :  1,
99*5113495bSYour Name                       reserved_1a                                             :  1,
100*5113495bSYour Name                       global_ofdma_mimo_enable                                :  1,
101*5113495bSYour Name                       mcs                                                     :  4;
102*5113495bSYour Name              uint32_t response_expected                                       :  1,
103*5113495bSYour Name                       mu_ndp                                                  :  1,
104*5113495bSYour Name                       clpc_enable                                             :  1,
105*5113495bSYour Name                       reserved_2b                                             :  2,
106*5113495bSYour Name                       stream_offset                                           :  3,
107*5113495bSYour Name                       nss                                                     :  3,
108*5113495bSYour Name                       reserved_2a                                             :  2,
109*5113495bSYour Name                       tlv_source                                              :  1,
110*5113495bSYour Name                       pcu_ppdu_setup_start_reason                             :  3,
111*5113495bSYour Name                       ru_position_start                                       :  8,
112*5113495bSYour Name                       ap_pkt_bw                                               :  3,
113*5113495bSYour Name                       triggered                                               :  1,
114*5113495bSYour Name                       ul_flag                                                 :  1,
115*5113495bSYour Name                       ndp                                                     :  2;
116*5113495bSYour Name              uint32_t u_sig_puncture_pattern_encoding                         :  6,
117*5113495bSYour Name                       reserved_3c                                             :  1,
118*5113495bSYour Name                       ru_size_updated_v2                                      :  4,
119*5113495bSYour Name                       ltf_size                                                :  2,
120*5113495bSYour Name                       generate_phyrx_tx_start_timing                          :  1,
121*5113495bSYour Name                       active_channel                                          :  3,
122*5113495bSYour Name                       he_ppdu_subtype                                         :  2,
123*5113495bSYour Name                       cp_setting                                              :  2,
124*5113495bSYour Name                       ant_sel                                                 :  1,
125*5113495bSYour Name                       ant_sel_valid                                           :  1,
126*5113495bSYour Name                       rx_chain_mask_valid                                     :  1,
127*5113495bSYour Name                       rx_chain_mask                                           :  8;
128*5113495bSYour Name #endif
129*5113495bSYour Name };
130*5113495bSYour Name 
131*5113495bSYour Name 
132*5113495bSYour Name 
133*5113495bSYour Name 
134*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_0A_OFFSET                                           0x0000000000000000
135*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_0A_LSB                                              0
136*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_0A_MSB                                              15
137*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_0A_MASK                                             0x000000000000ffff
138*5113495bSYour Name 
139*5113495bSYour Name 
140*5113495bSYour Name 
141*5113495bSYour Name 
142*5113495bSYour Name #define MACTX_PHY_DESC_BF_TYPE_OFFSET                                               0x0000000000000000
143*5113495bSYour Name #define MACTX_PHY_DESC_BF_TYPE_LSB                                                  16
144*5113495bSYour Name #define MACTX_PHY_DESC_BF_TYPE_MSB                                                  17
145*5113495bSYour Name #define MACTX_PHY_DESC_BF_TYPE_MASK                                                 0x0000000000030000
146*5113495bSYour Name 
147*5113495bSYour Name 
148*5113495bSYour Name 
149*5113495bSYour Name 
150*5113495bSYour Name #define MACTX_PHY_DESC_WAIT_SIFS_OFFSET                                             0x0000000000000000
151*5113495bSYour Name #define MACTX_PHY_DESC_WAIT_SIFS_LSB                                                18
152*5113495bSYour Name #define MACTX_PHY_DESC_WAIT_SIFS_MSB                                                19
153*5113495bSYour Name #define MACTX_PHY_DESC_WAIT_SIFS_MASK                                               0x00000000000c0000
154*5113495bSYour Name 
155*5113495bSYour Name 
156*5113495bSYour Name 
157*5113495bSYour Name 
158*5113495bSYour Name #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET                                  0x0000000000000000
159*5113495bSYour Name #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB                                     20
160*5113495bSYour Name #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB                                     20
161*5113495bSYour Name #define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK                                    0x0000000000100000
162*5113495bSYour Name 
163*5113495bSYour Name 
164*5113495bSYour Name 
165*5113495bSYour Name 
166*5113495bSYour Name #define MACTX_PHY_DESC_PKT_TYPE_OFFSET                                              0x0000000000000000
167*5113495bSYour Name #define MACTX_PHY_DESC_PKT_TYPE_LSB                                                 21
168*5113495bSYour Name #define MACTX_PHY_DESC_PKT_TYPE_MSB                                                 24
169*5113495bSYour Name #define MACTX_PHY_DESC_PKT_TYPE_MASK                                                0x0000000001e00000
170*5113495bSYour Name 
171*5113495bSYour Name 
172*5113495bSYour Name 
173*5113495bSYour Name 
174*5113495bSYour Name #define MACTX_PHY_DESC_SU_OR_MU_OFFSET                                              0x0000000000000000
175*5113495bSYour Name #define MACTX_PHY_DESC_SU_OR_MU_LSB                                                 25
176*5113495bSYour Name #define MACTX_PHY_DESC_SU_OR_MU_MSB                                                 26
177*5113495bSYour Name #define MACTX_PHY_DESC_SU_OR_MU_MASK                                                0x0000000006000000
178*5113495bSYour Name 
179*5113495bSYour Name 
180*5113495bSYour Name 
181*5113495bSYour Name 
182*5113495bSYour Name #define MACTX_PHY_DESC_MU_TYPE_OFFSET                                               0x0000000000000000
183*5113495bSYour Name #define MACTX_PHY_DESC_MU_TYPE_LSB                                                  27
184*5113495bSYour Name #define MACTX_PHY_DESC_MU_TYPE_MSB                                                  27
185*5113495bSYour Name #define MACTX_PHY_DESC_MU_TYPE_MASK                                                 0x0000000008000000
186*5113495bSYour Name 
187*5113495bSYour Name 
188*5113495bSYour Name 
189*5113495bSYour Name 
190*5113495bSYour Name #define MACTX_PHY_DESC_BANDWIDTH_OFFSET                                             0x0000000000000000
191*5113495bSYour Name #define MACTX_PHY_DESC_BANDWIDTH_LSB                                                28
192*5113495bSYour Name #define MACTX_PHY_DESC_BANDWIDTH_MSB                                                30
193*5113495bSYour Name #define MACTX_PHY_DESC_BANDWIDTH_MASK                                               0x0000000070000000
194*5113495bSYour Name 
195*5113495bSYour Name 
196*5113495bSYour Name 
197*5113495bSYour Name 
198*5113495bSYour Name #define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET                                       0x0000000000000000
199*5113495bSYour Name #define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB                                          31
200*5113495bSYour Name #define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB                                          31
201*5113495bSYour Name #define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK                                         0x0000000080000000
202*5113495bSYour Name 
203*5113495bSYour Name 
204*5113495bSYour Name 
205*5113495bSYour Name 
206*5113495bSYour Name #define MACTX_PHY_DESC_MCS_OFFSET                                                   0x0000000000000000
207*5113495bSYour Name #define MACTX_PHY_DESC_MCS_LSB                                                      32
208*5113495bSYour Name #define MACTX_PHY_DESC_MCS_MSB                                                      35
209*5113495bSYour Name #define MACTX_PHY_DESC_MCS_MASK                                                     0x0000000f00000000
210*5113495bSYour Name 
211*5113495bSYour Name 
212*5113495bSYour Name 
213*5113495bSYour Name 
214*5113495bSYour Name #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET                              0x0000000000000000
215*5113495bSYour Name #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB                                 36
216*5113495bSYour Name #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB                                 36
217*5113495bSYour Name #define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK                                0x0000001000000000
218*5113495bSYour Name 
219*5113495bSYour Name 
220*5113495bSYour Name 
221*5113495bSYour Name 
222*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_1A_OFFSET                                           0x0000000000000000
223*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_1A_LSB                                              37
224*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_1A_MSB                                              37
225*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_1A_MASK                                             0x0000002000000000
226*5113495bSYour Name 
227*5113495bSYour Name 
228*5113495bSYour Name 
229*5113495bSYour Name 
230*5113495bSYour Name #define MACTX_PHY_DESC_STBC_OFFSET                                                  0x0000000000000000
231*5113495bSYour Name #define MACTX_PHY_DESC_STBC_LSB                                                     38
232*5113495bSYour Name #define MACTX_PHY_DESC_STBC_MSB                                                     38
233*5113495bSYour Name #define MACTX_PHY_DESC_STBC_MASK                                                    0x0000004000000000
234*5113495bSYour Name 
235*5113495bSYour Name 
236*5113495bSYour Name 
237*5113495bSYour Name 
238*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET                                   0x0000000000000000
239*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB                                      39
240*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB                                      39
241*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK                                     0x0000008000000000
242*5113495bSYour Name 
243*5113495bSYour Name 
244*5113495bSYour Name 
245*5113495bSYour Name 
246*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET                        0x0000000000000000
247*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB                           40
248*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB                           40
249*5113495bSYour Name #define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK                          0x0000010000000000
250*5113495bSYour Name 
251*5113495bSYour Name 
252*5113495bSYour Name 
253*5113495bSYour Name 
254*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET                                         0x0000000000000000
255*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_SHARED_LSB                                            41
256*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_SHARED_MSB                                            48
257*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_SHARED_MASK                                           0x0001fe0000000000
258*5113495bSYour Name 
259*5113495bSYour Name 
260*5113495bSYour Name 
261*5113495bSYour Name 
262*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET                                       0x0000000000000000
263*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB                                          49
264*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB                                          56
265*5113495bSYour Name #define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK                                         0x01fe000000000000
266*5113495bSYour Name 
267*5113495bSYour Name 
268*5113495bSYour Name 
269*5113495bSYour Name 
270*5113495bSYour Name #define MACTX_PHY_DESC_MEASURE_POWER_OFFSET                                         0x0000000000000000
271*5113495bSYour Name #define MACTX_PHY_DESC_MEASURE_POWER_LSB                                            57
272*5113495bSYour Name #define MACTX_PHY_DESC_MEASURE_POWER_MSB                                            57
273*5113495bSYour Name #define MACTX_PHY_DESC_MEASURE_POWER_MASK                                           0x0200000000000000
274*5113495bSYour Name 
275*5113495bSYour Name 
276*5113495bSYour Name 
277*5113495bSYour Name 
278*5113495bSYour Name #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET                                     0x0000000000000000
279*5113495bSYour Name #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB                                        58
280*5113495bSYour Name #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB                                        58
281*5113495bSYour Name #define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK                                       0x0400000000000000
282*5113495bSYour Name 
283*5113495bSYour Name 
284*5113495bSYour Name 
285*5113495bSYour Name 
286*5113495bSYour Name #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET                    0x0000000000000000
287*5113495bSYour Name #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB                       59
288*5113495bSYour Name #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB                       59
289*5113495bSYour Name #define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK                      0x0800000000000000
290*5113495bSYour Name 
291*5113495bSYour Name 
292*5113495bSYour Name 
293*5113495bSYour Name 
294*5113495bSYour Name #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET                                        0x0000000000000000
295*5113495bSYour Name #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB                                           60
296*5113495bSYour Name #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB                                           62
297*5113495bSYour Name #define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK                                          0x7000000000000000
298*5113495bSYour Name 
299*5113495bSYour Name 
300*5113495bSYour Name 
301*5113495bSYour Name 
302*5113495bSYour Name #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET                       0x0000000000000000
303*5113495bSYour Name #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB                          63
304*5113495bSYour Name #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB                          63
305*5113495bSYour Name #define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK                         0x8000000000000000
306*5113495bSYour Name 
307*5113495bSYour Name 
308*5113495bSYour Name 
309*5113495bSYour Name 
310*5113495bSYour Name #define MACTX_PHY_DESC_NDP_OFFSET                                                   0x0000000000000008
311*5113495bSYour Name #define MACTX_PHY_DESC_NDP_LSB                                                      0
312*5113495bSYour Name #define MACTX_PHY_DESC_NDP_MSB                                                      1
313*5113495bSYour Name #define MACTX_PHY_DESC_NDP_MASK                                                     0x0000000000000003
314*5113495bSYour Name 
315*5113495bSYour Name 
316*5113495bSYour Name 
317*5113495bSYour Name 
318*5113495bSYour Name #define MACTX_PHY_DESC_UL_FLAG_OFFSET                                               0x0000000000000008
319*5113495bSYour Name #define MACTX_PHY_DESC_UL_FLAG_LSB                                                  2
320*5113495bSYour Name #define MACTX_PHY_DESC_UL_FLAG_MSB                                                  2
321*5113495bSYour Name #define MACTX_PHY_DESC_UL_FLAG_MASK                                                 0x0000000000000004
322*5113495bSYour Name 
323*5113495bSYour Name 
324*5113495bSYour Name 
325*5113495bSYour Name 
326*5113495bSYour Name #define MACTX_PHY_DESC_TRIGGERED_OFFSET                                             0x0000000000000008
327*5113495bSYour Name #define MACTX_PHY_DESC_TRIGGERED_LSB                                                3
328*5113495bSYour Name #define MACTX_PHY_DESC_TRIGGERED_MSB                                                3
329*5113495bSYour Name #define MACTX_PHY_DESC_TRIGGERED_MASK                                               0x0000000000000008
330*5113495bSYour Name 
331*5113495bSYour Name 
332*5113495bSYour Name 
333*5113495bSYour Name 
334*5113495bSYour Name #define MACTX_PHY_DESC_AP_PKT_BW_OFFSET                                             0x0000000000000008
335*5113495bSYour Name #define MACTX_PHY_DESC_AP_PKT_BW_LSB                                                4
336*5113495bSYour Name #define MACTX_PHY_DESC_AP_PKT_BW_MSB                                                6
337*5113495bSYour Name #define MACTX_PHY_DESC_AP_PKT_BW_MASK                                               0x0000000000000070
338*5113495bSYour Name 
339*5113495bSYour Name 
340*5113495bSYour Name 
341*5113495bSYour Name 
342*5113495bSYour Name #define MACTX_PHY_DESC_RU_POSITION_START_OFFSET                                     0x0000000000000008
343*5113495bSYour Name #define MACTX_PHY_DESC_RU_POSITION_START_LSB                                        7
344*5113495bSYour Name #define MACTX_PHY_DESC_RU_POSITION_START_MSB                                        14
345*5113495bSYour Name #define MACTX_PHY_DESC_RU_POSITION_START_MASK                                       0x0000000000007f80
346*5113495bSYour Name 
347*5113495bSYour Name 
348*5113495bSYour Name 
349*5113495bSYour Name 
350*5113495bSYour Name #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET                           0x0000000000000008
351*5113495bSYour Name #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB                              15
352*5113495bSYour Name #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB                              17
353*5113495bSYour Name #define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK                             0x0000000000038000
354*5113495bSYour Name 
355*5113495bSYour Name 
356*5113495bSYour Name 
357*5113495bSYour Name 
358*5113495bSYour Name #define MACTX_PHY_DESC_TLV_SOURCE_OFFSET                                            0x0000000000000008
359*5113495bSYour Name #define MACTX_PHY_DESC_TLV_SOURCE_LSB                                               18
360*5113495bSYour Name #define MACTX_PHY_DESC_TLV_SOURCE_MSB                                               18
361*5113495bSYour Name #define MACTX_PHY_DESC_TLV_SOURCE_MASK                                              0x0000000000040000
362*5113495bSYour Name 
363*5113495bSYour Name 
364*5113495bSYour Name 
365*5113495bSYour Name 
366*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2A_OFFSET                                           0x0000000000000008
367*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2A_LSB                                              19
368*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2A_MSB                                              20
369*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2A_MASK                                             0x0000000000180000
370*5113495bSYour Name 
371*5113495bSYour Name 
372*5113495bSYour Name 
373*5113495bSYour Name 
374*5113495bSYour Name #define MACTX_PHY_DESC_NSS_OFFSET                                                   0x0000000000000008
375*5113495bSYour Name #define MACTX_PHY_DESC_NSS_LSB                                                      21
376*5113495bSYour Name #define MACTX_PHY_DESC_NSS_MSB                                                      23
377*5113495bSYour Name #define MACTX_PHY_DESC_NSS_MASK                                                     0x0000000000e00000
378*5113495bSYour Name 
379*5113495bSYour Name 
380*5113495bSYour Name 
381*5113495bSYour Name 
382*5113495bSYour Name #define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET                                         0x0000000000000008
383*5113495bSYour Name #define MACTX_PHY_DESC_STREAM_OFFSET_LSB                                            24
384*5113495bSYour Name #define MACTX_PHY_DESC_STREAM_OFFSET_MSB                                            26
385*5113495bSYour Name #define MACTX_PHY_DESC_STREAM_OFFSET_MASK                                           0x0000000007000000
386*5113495bSYour Name 
387*5113495bSYour Name 
388*5113495bSYour Name 
389*5113495bSYour Name 
390*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2B_OFFSET                                           0x0000000000000008
391*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2B_LSB                                              27
392*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2B_MSB                                              28
393*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_2B_MASK                                             0x0000000018000000
394*5113495bSYour Name 
395*5113495bSYour Name 
396*5113495bSYour Name 
397*5113495bSYour Name 
398*5113495bSYour Name #define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET                                           0x0000000000000008
399*5113495bSYour Name #define MACTX_PHY_DESC_CLPC_ENABLE_LSB                                              29
400*5113495bSYour Name #define MACTX_PHY_DESC_CLPC_ENABLE_MSB                                              29
401*5113495bSYour Name #define MACTX_PHY_DESC_CLPC_ENABLE_MASK                                             0x0000000020000000
402*5113495bSYour Name 
403*5113495bSYour Name 
404*5113495bSYour Name 
405*5113495bSYour Name 
406*5113495bSYour Name #define MACTX_PHY_DESC_MU_NDP_OFFSET                                                0x0000000000000008
407*5113495bSYour Name #define MACTX_PHY_DESC_MU_NDP_LSB                                                   30
408*5113495bSYour Name #define MACTX_PHY_DESC_MU_NDP_MSB                                                   30
409*5113495bSYour Name #define MACTX_PHY_DESC_MU_NDP_MASK                                                  0x0000000040000000
410*5113495bSYour Name 
411*5113495bSYour Name 
412*5113495bSYour Name 
413*5113495bSYour Name 
414*5113495bSYour Name #define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET                                     0x0000000000000008
415*5113495bSYour Name #define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB                                        31
416*5113495bSYour Name #define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB                                        31
417*5113495bSYour Name #define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK                                       0x0000000080000000
418*5113495bSYour Name 
419*5113495bSYour Name 
420*5113495bSYour Name 
421*5113495bSYour Name 
422*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET                                         0x0000000000000008
423*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB                                            32
424*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB                                            39
425*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK                                           0x000000ff00000000
426*5113495bSYour Name 
427*5113495bSYour Name 
428*5113495bSYour Name 
429*5113495bSYour Name 
430*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET                                   0x0000000000000008
431*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB                                      40
432*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB                                      40
433*5113495bSYour Name #define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK                                     0x0000010000000000
434*5113495bSYour Name 
435*5113495bSYour Name 
436*5113495bSYour Name 
437*5113495bSYour Name 
438*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET                                         0x0000000000000008
439*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_VALID_LSB                                            41
440*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_VALID_MSB                                            41
441*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_VALID_MASK                                           0x0000020000000000
442*5113495bSYour Name 
443*5113495bSYour Name 
444*5113495bSYour Name 
445*5113495bSYour Name 
446*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_OFFSET                                               0x0000000000000008
447*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_LSB                                                  42
448*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_MSB                                                  42
449*5113495bSYour Name #define MACTX_PHY_DESC_ANT_SEL_MASK                                                 0x0000040000000000
450*5113495bSYour Name 
451*5113495bSYour Name 
452*5113495bSYour Name 
453*5113495bSYour Name 
454*5113495bSYour Name #define MACTX_PHY_DESC_CP_SETTING_OFFSET                                            0x0000000000000008
455*5113495bSYour Name #define MACTX_PHY_DESC_CP_SETTING_LSB                                               43
456*5113495bSYour Name #define MACTX_PHY_DESC_CP_SETTING_MSB                                               44
457*5113495bSYour Name #define MACTX_PHY_DESC_CP_SETTING_MASK                                              0x0000180000000000
458*5113495bSYour Name 
459*5113495bSYour Name 
460*5113495bSYour Name 
461*5113495bSYour Name 
462*5113495bSYour Name #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET                                       0x0000000000000008
463*5113495bSYour Name #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB                                          45
464*5113495bSYour Name #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB                                          46
465*5113495bSYour Name #define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK                                         0x0000600000000000
466*5113495bSYour Name 
467*5113495bSYour Name 
468*5113495bSYour Name 
469*5113495bSYour Name 
470*5113495bSYour Name #define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET                                        0x0000000000000008
471*5113495bSYour Name #define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB                                           47
472*5113495bSYour Name #define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB                                           49
473*5113495bSYour Name #define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK                                          0x0003800000000000
474*5113495bSYour Name 
475*5113495bSYour Name 
476*5113495bSYour Name 
477*5113495bSYour Name 
478*5113495bSYour Name #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET                        0x0000000000000008
479*5113495bSYour Name #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB                           50
480*5113495bSYour Name #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB                           50
481*5113495bSYour Name #define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK                          0x0004000000000000
482*5113495bSYour Name 
483*5113495bSYour Name 
484*5113495bSYour Name 
485*5113495bSYour Name 
486*5113495bSYour Name #define MACTX_PHY_DESC_LTF_SIZE_OFFSET                                              0x0000000000000008
487*5113495bSYour Name #define MACTX_PHY_DESC_LTF_SIZE_LSB                                                 51
488*5113495bSYour Name #define MACTX_PHY_DESC_LTF_SIZE_MSB                                                 52
489*5113495bSYour Name #define MACTX_PHY_DESC_LTF_SIZE_MASK                                                0x0018000000000000
490*5113495bSYour Name 
491*5113495bSYour Name 
492*5113495bSYour Name 
493*5113495bSYour Name 
494*5113495bSYour Name #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET                                    0x0000000000000008
495*5113495bSYour Name #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB                                       53
496*5113495bSYour Name #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB                                       56
497*5113495bSYour Name #define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK                                      0x01e0000000000000
498*5113495bSYour Name 
499*5113495bSYour Name 
500*5113495bSYour Name 
501*5113495bSYour Name 
502*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_3C_OFFSET                                           0x0000000000000008
503*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_3C_LSB                                              57
504*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_3C_MSB                                              57
505*5113495bSYour Name #define MACTX_PHY_DESC_RESERVED_3C_MASK                                             0x0200000000000000
506*5113495bSYour Name 
507*5113495bSYour Name 
508*5113495bSYour Name 
509*5113495bSYour Name 
510*5113495bSYour Name #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET                       0x0000000000000008
511*5113495bSYour Name #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB                          58
512*5113495bSYour Name #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB                          63
513*5113495bSYour Name #define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK                         0xfc00000000000000
514*5113495bSYour Name 
515*5113495bSYour Name 
516*5113495bSYour Name 
517*5113495bSYour Name #endif
518